JPS54126577U - - Google Patents
Info
- Publication number
- JPS54126577U JPS54126577U JP1978022224U JP2222478U JPS54126577U JP S54126577 U JPS54126577 U JP S54126577U JP 1978022224 U JP1978022224 U JP 1978022224U JP 2222478 U JP2222478 U JP 2222478U JP S54126577 U JPS54126577 U JP S54126577U
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
Landscapes
- Thyristors (AREA)
- Die Bonding (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1978022224U JPS54126577U (zh) | 1978-02-24 | 1978-02-24 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1978022224U JPS54126577U (zh) | 1978-02-24 | 1978-02-24 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54126577U true JPS54126577U (zh) | 1979-09-04 |
Family
ID=28856582
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1978022224U Pending JPS54126577U (zh) | 1978-02-24 | 1978-02-24 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54126577U (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018163599A1 (ja) * | 2017-03-08 | 2018-09-13 | 三菱電機株式会社 | 半導体装置、その製造方法および半導体モジュール |
-
1978
- 1978-02-24 JP JP1978022224U patent/JPS54126577U/ja active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018163599A1 (ja) * | 2017-03-08 | 2018-09-13 | 三菱電機株式会社 | 半導体装置、その製造方法および半導体モジュール |
JP6477975B2 (ja) * | 2017-03-08 | 2019-03-06 | 三菱電機株式会社 | 半導体装置、その製造方法および半導体モジュール |
JPWO2018163599A1 (ja) * | 2017-03-08 | 2019-03-14 | 三菱電機株式会社 | 半導体装置、その製造方法および半導体モジュール |