JPS54124950A - Divider - Google Patents

Divider

Info

Publication number
JPS54124950A
JPS54124950A JP3232778A JP3232778A JPS54124950A JP S54124950 A JPS54124950 A JP S54124950A JP 3232778 A JP3232778 A JP 3232778A JP 3232778 A JP3232778 A JP 3232778A JP S54124950 A JPS54124950 A JP S54124950A
Authority
JP
Japan
Prior art keywords
divider
circuit
signal
input
amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3232778A
Other languages
Japanese (ja)
Inventor
Tokuhito Nakahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3232778A priority Critical patent/JPS54124950A/en
Publication of JPS54124950A publication Critical patent/JPS54124950A/en
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To improve the precision of a divider with its constitution simplified without adding a special divider circuit to the divider which uses an automatic gain control circuit, by switching the automatic gain control circuit by an analog switch. CONSTITUTION:This divider is equipped with the automatic gain control circuit composed of operation amplifiers OP1, OP2 and OP3 whose gains are controlled automatically, analog switches S1 to Sn which divide an input signal applied to input point VIN of the circuit into a divisor signal and a dividend signal, analog switch S0 which conducts the feedback circuit of the circuit in a divisor input state and cuts off it in a dividend input state connecting to the output of amplifier OP1, and a FET. Further, capacitor C1 which holds the gain after the divisor signal input until a dividend signal is inputted is provided to the feedback circuit of amplifier OP1. Then, the output side of amplifier OP2 is connected to output point VOUT from which a division value is outputted, thereby constituting the divider.
JP3232778A 1978-03-23 1978-03-23 Divider Pending JPS54124950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3232778A JPS54124950A (en) 1978-03-23 1978-03-23 Divider

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3232778A JPS54124950A (en) 1978-03-23 1978-03-23 Divider

Publications (1)

Publication Number Publication Date
JPS54124950A true JPS54124950A (en) 1979-09-28

Family

ID=12355841

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3232778A Pending JPS54124950A (en) 1978-03-23 1978-03-23 Divider

Country Status (1)

Country Link
JP (1) JPS54124950A (en)

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