JPS54124915A - Phase controller - Google Patents

Phase controller

Info

Publication number
JPS54124915A
JPS54124915A JP3329278A JP3329278A JPS54124915A JP S54124915 A JPS54124915 A JP S54124915A JP 3329278 A JP3329278 A JP 3329278A JP 3329278 A JP3329278 A JP 3329278A JP S54124915 A JPS54124915 A JP S54124915A
Authority
JP
Japan
Prior art keywords
signal
phase
reference timing
receiving data
change point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3329278A
Other languages
Japanese (ja)
Inventor
Masaharu Hirooka
Masunori Kosaka
Susumu Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3329278A priority Critical patent/JPS54124915A/en
Publication of JPS54124915A publication Critical patent/JPS54124915A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0079Receiver details
    • H04L7/0083Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To remove disturbance caused by noises by controlling a reference timing signal to a fixed phase, by generating a stop signal by receiving data and the reference timing signal by comparing the phase of a conversion signal with that of the reference timing by a phase comparator circuit. CONSTITUTION:By detecting the voltage change point of a receiving data signal, change point detection circuit 2 outputs a change point signal, and reference timing generating circuit 5 generates a reference timing signal under the control with the phase either advanced or delayed by a control signal for phase advancing, phase-delaying or stopping. For the purpose, phase comparator circuit 3 compares the phase of a conversion signal with that of the reference timing signal; and the reference timing generating circuit is supplied with a phase-advancing control signal when the conversion signal leads or a phase delaying control signal when lagging, so that stop signal generating circuit 4 will generate a stop signal controlled by the receiving data signal and reference timing signal. Consequently, the reference timing signal can be controlled to a fixed phase in order to remove disturbance caused by noises, etc.
JP3329278A 1978-03-22 1978-03-22 Phase controller Pending JPS54124915A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3329278A JPS54124915A (en) 1978-03-22 1978-03-22 Phase controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3329278A JPS54124915A (en) 1978-03-22 1978-03-22 Phase controller

Publications (1)

Publication Number Publication Date
JPS54124915A true JPS54124915A (en) 1979-09-28

Family

ID=12382455

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3329278A Pending JPS54124915A (en) 1978-03-22 1978-03-22 Phase controller

Country Status (1)

Country Link
JP (1) JPS54124915A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62178035A (en) * 1986-01-31 1987-08-05 Hitachi Ltd Bit synchronizing circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62178035A (en) * 1986-01-31 1987-08-05 Hitachi Ltd Bit synchronizing circuit

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