JPS54124914A - Phase controller - Google Patents
Phase controllerInfo
- Publication number
- JPS54124914A JPS54124914A JP3329178A JP3329178A JPS54124914A JP S54124914 A JPS54124914 A JP S54124914A JP 3329178 A JP3329178 A JP 3329178A JP 3329178 A JP3329178 A JP 3329178A JP S54124914 A JPS54124914 A JP S54124914A
- Authority
- JP
- Japan
- Prior art keywords
- phase
- signal
- receiving data
- delaying
- timing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
- H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To maintain timing with no hindrance to extraction of receiving data even if the receiving data signal intermits by controlling a reference-timing generating circuit to a fixed phase by a phase-advancing signal, a phase-delaying signal and a phase-delaying control stop signal. CONSTITUTION:Receiving data, which has the voltage change point detected by change point detection circuit 2, is phase-compared with a reference timing signal from reference-timing generating circuit 5 incorporated in phase comparator circuit 3. As a result, a phase-advancing signal when the receiving data leads a phase- delaying signal when lagging is outputted. Phase-delaying control stop circuit 4, on the other hand, stops the phase-delaying control of the phase-delaying signal when the receiving data signal is not detected for more than two bits. Consequently, the reference timing generating circuit is controlled to a fixed phase, so that even if the receiving data signal intermits, timing with no hindrance to the extraction of the receiving data can be maintained.
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3329178A JPS54124914A (en) | 1978-03-22 | 1978-03-22 | Phase controller |
FI790900A FI77955C (en) | 1978-03-22 | 1979-03-16 | ANPASSNINGSFILTER. |
NO790941A NO148013C (en) | 1978-03-22 | 1979-03-20 | FITTING FILTER. |
SE7902524A SE447616B (en) | 1978-03-22 | 1979-03-20 | MATCHING FILTER |
DK118179A DK155109C (en) | 1978-03-22 | 1979-03-22 | ADAPTATION FILTER |
SE8602660A SE504036C2 (en) | 1978-03-22 | 1986-06-13 | Matching filters |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3329178A JPS54124914A (en) | 1978-03-22 | 1978-03-22 | Phase controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54124914A true JPS54124914A (en) | 1979-09-28 |
Family
ID=12382424
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3329178A Pending JPS54124914A (en) | 1978-03-22 | 1978-03-22 | Phase controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54124914A (en) |
-
1978
- 1978-03-22 JP JP3329178A patent/JPS54124914A/en active Pending
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