JPS54121624A - Memory unit - Google Patents

Memory unit

Info

Publication number
JPS54121624A
JPS54121624A JP2868678A JP2868678A JPS54121624A JP S54121624 A JPS54121624 A JP S54121624A JP 2868678 A JP2868678 A JP 2868678A JP 2868678 A JP2868678 A JP 2868678A JP S54121624 A JPS54121624 A JP S54121624A
Authority
JP
Japan
Prior art keywords
reading
time
output line
start signal
cycle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2868678A
Other languages
Japanese (ja)
Inventor
Seiji Izumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2868678A priority Critical patent/JPS54121624A/en
Publication of JPS54121624A publication Critical patent/JPS54121624A/en
Pending legal-status Critical Current

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  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To shorten the access time at the reading retrial time to reduce the increment of the process time of the logic unit and thus to avoid the lowering of performance by generating the start signal for re-execution of the reading cycle of the same address by the memory unit itself.
CONSTITUTION: With application of the start signal of the reading cycle to input line 30 from the logic unit, the reading data is sent out from output line 35 regardless of existence of the error. When the error of the data is detected by detector circuit 24, the data use inhibition signal for reading is transmitted from output line 36. At the same time, the restart signal is produced at restart signal generator circuit 29 and then delivered to output line 38 immediately after the end of the memory cycle which was started by the preceding start signal applied to input line 30. Thus the re-execution of reading can be given for the same address with no queuing time, preventing the lowering of performance at the reading retrial time.
COPYRIGHT: (C)1979,JPO&Japio
JP2868678A 1978-03-15 1978-03-15 Memory unit Pending JPS54121624A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2868678A JPS54121624A (en) 1978-03-15 1978-03-15 Memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2868678A JPS54121624A (en) 1978-03-15 1978-03-15 Memory unit

Publications (1)

Publication Number Publication Date
JPS54121624A true JPS54121624A (en) 1979-09-20

Family

ID=12255361

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2868678A Pending JPS54121624A (en) 1978-03-15 1978-03-15 Memory unit

Country Status (1)

Country Link
JP (1) JPS54121624A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006336267A (en) * 2005-06-01 2006-12-14 Sugikou:Kk Main rope post system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006336267A (en) * 2005-06-01 2006-12-14 Sugikou:Kk Main rope post system

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