JPS54119829A - Redundant bit additional system in facsimile coding - Google Patents

Redundant bit additional system in facsimile coding

Info

Publication number
JPS54119829A
JPS54119829A JP2659078A JP2659078A JPS54119829A JP S54119829 A JPS54119829 A JP S54119829A JP 2659078 A JP2659078 A JP 2659078A JP 2659078 A JP2659078 A JP 2659078A JP S54119829 A JPS54119829 A JP S54119829A
Authority
JP
Japan
Prior art keywords
signal
coder
constitution
length
outputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2659078A
Other languages
Japanese (ja)
Inventor
Norihiko Fukinuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2659078A priority Critical patent/JPS54119829A/en
Publication of JPS54119829A publication Critical patent/JPS54119829A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable the addition of redundancy bit, by performing the identification of line synchronous signal in high speed facsimile signal through the insertio of codes corresponding to the length 0 as the redundancy bit with a required number, when the coding of specified video information is finished.
CONSTITUTION: After the scanning signal of picture is converted into binary electric signal with the video reader 1 and it is ones tored in the input buffer memory 2, the signal from the memory 2 is coded at the coder 3 and outputted to the output terminal via the output buffer memory 4. The counter 6 and the dummy 7 are provided with the output of the coder 3 with this circuit constitution. Further, the counter 6 counts the number of bits per one line and if the count value is less than the specified value, constitution is taken that the coder 7 is driven until the specified value is exceeded. The code of run length having length 0 outputted with the coder 7 is repetitively added to the end part of the video signal of the buffer 4.
COPYRIGHT: (C)1979,JPO&Japio
JP2659078A 1978-03-10 1978-03-10 Redundant bit additional system in facsimile coding Pending JPS54119829A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2659078A JPS54119829A (en) 1978-03-10 1978-03-10 Redundant bit additional system in facsimile coding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2659078A JPS54119829A (en) 1978-03-10 1978-03-10 Redundant bit additional system in facsimile coding

Publications (1)

Publication Number Publication Date
JPS54119829A true JPS54119829A (en) 1979-09-18

Family

ID=12197744

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2659078A Pending JPS54119829A (en) 1978-03-10 1978-03-10 Redundant bit additional system in facsimile coding

Country Status (1)

Country Link
JP (1) JPS54119829A (en)

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