JPS54116979A - Sound stop watch - Google Patents

Sound stop watch

Info

Publication number
JPS54116979A
JPS54116979A JP2463978A JP2463978A JPS54116979A JP S54116979 A JPS54116979 A JP S54116979A JP 2463978 A JP2463978 A JP 2463978A JP 2463978 A JP2463978 A JP 2463978A JP S54116979 A JPS54116979 A JP S54116979A
Authority
JP
Japan
Prior art keywords
counter
time
register
sound
fff
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2463978A
Other languages
Japanese (ja)
Inventor
Akiyoshi Tanimoto
Mitsuhiro Saiji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP2463978A priority Critical patent/JPS54116979A/en
Publication of JPS54116979A publication Critical patent/JPS54116979A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To provide a stop watch capable of informing the time in sounds by applying the counted values of a time counter for preset time intervals to a register to generate address signals so that the sound quantitized data read out of a memory.
CONSTITUTION: When a key SK is operated, an AND gate A1 is opened, and the reset output of an FFF1 becomes a down counting signal so that a time counter TC count down the initial value, which is preset by a register R, in rsponse to each time signal from a frequency divider DV. When the initial preset time is reached, starting signals are generated through a judging circuit JTC from a speaker SP1, and the counter TC counts up in response to the set output of the FFF1. The outed value of the counter TC counts up in response to the set output of the FFF1. The outed value of the counter TC is counted for each preset time interval by a register B so that address signals are generated through a buffer register D from a sound initial address circuit CC. As a result, the sound quantitized data are read o-t of a ROMRM so that they are informed in sounds from a speaker SP2 during the period while the elapsed time reoperates the switch SK.
COPYRIGHT: (C)1979,JPO&Japio
JP2463978A 1978-03-03 1978-03-03 Sound stop watch Pending JPS54116979A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2463978A JPS54116979A (en) 1978-03-03 1978-03-03 Sound stop watch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2463978A JPS54116979A (en) 1978-03-03 1978-03-03 Sound stop watch

Publications (1)

Publication Number Publication Date
JPS54116979A true JPS54116979A (en) 1979-09-11

Family

ID=12143693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2463978A Pending JPS54116979A (en) 1978-03-03 1978-03-03 Sound stop watch

Country Status (1)

Country Link
JP (1) JPS54116979A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56122983U (en) * 1980-02-19 1981-09-18

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56122983U (en) * 1980-02-19 1981-09-18
JPS6245193Y2 (en) * 1980-02-19 1987-12-02

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