JPS54108540A - Memory circuit device - Google Patents

Memory circuit device

Info

Publication number
JPS54108540A
JPS54108540A JP1523478A JP1523478A JPS54108540A JP S54108540 A JPS54108540 A JP S54108540A JP 1523478 A JP1523478 A JP 1523478A JP 1523478 A JP1523478 A JP 1523478A JP S54108540 A JPS54108540 A JP S54108540A
Authority
JP
Japan
Prior art keywords
phif
inversion
capacitor
memory circuit
clocked inverter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1523478A
Other languages
Japanese (ja)
Other versions
JPS615239B2 (en
Inventor
Masataka Hirasawa
Akira Hashimoto
Kenichi Nagao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1523478A priority Critical patent/JPS54108540A/en
Publication of JPS54108540A publication Critical patent/JPS54108540A/en
Publication of JPS615239B2 publication Critical patent/JPS615239B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Abstract

PURPOSE:To make it possible to reduce wires for clock pulses in number at the time of integration, and also to miniaturize a chip size, by supplying a common clock pulse to switching methods of 1st and 2nd stabilizing methods. CONSTITUTION:The 1st memory circuit 105 composed of clocked inverter 100, capacitor 101 and stabilization circuit 104 (holding stably information stored in capacitor 101 by clocked inverter 102 and MOS type inverter 103- and 2nd memory circuit 205 composed of clocked inverter 200, capacitor 201 and stabilization circuit 204 are cascaded in order to obtain the function of a one-bit shift register, and clock pulse CP wiring needed to be arranged closely and in parallel to the earth power supply and negative power wiring requires only turee kinds of phi1, phi2, phiF and inversion phi1, inversion phi2, and inversion phiF, which are reduced by two in number as compared with conventional one. This results from that CP phiF and inversion phiF supplied to stabilization circuits 104 and 204 can be used in common among respective stages without necessity of constituting into individual shift registers.
JP1523478A 1978-02-13 1978-02-13 Memory circuit device Granted JPS54108540A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1523478A JPS54108540A (en) 1978-02-13 1978-02-13 Memory circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1523478A JPS54108540A (en) 1978-02-13 1978-02-13 Memory circuit device

Publications (2)

Publication Number Publication Date
JPS54108540A true JPS54108540A (en) 1979-08-25
JPS615239B2 JPS615239B2 (en) 1986-02-17

Family

ID=11883167

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1523478A Granted JPS54108540A (en) 1978-02-13 1978-02-13 Memory circuit device

Country Status (1)

Country Link
JP (1) JPS54108540A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6580631B1 (en) 1997-05-30 2003-06-17 Micron Technology, Inc. 256 Meg dynamic random access memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6580631B1 (en) 1997-05-30 2003-06-17 Micron Technology, Inc. 256 Meg dynamic random access memory
US6934173B2 (en) * 1997-05-30 2005-08-23 Micron Technology, Inc. 256 Meg dynamic random access memory

Also Published As

Publication number Publication date
JPS615239B2 (en) 1986-02-17

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