JPS54106136A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS54106136A
JPS54106136A JP1316278A JP1316278A JPS54106136A JP S54106136 A JPS54106136 A JP S54106136A JP 1316278 A JP1316278 A JP 1316278A JP 1316278 A JP1316278 A JP 1316278A JP S54106136 A JPS54106136 A JP S54106136A
Authority
JP
Japan
Prior art keywords
wire
turned
circuit
line array
low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1316278A
Other languages
Japanese (ja)
Inventor
Toshio Hayashi
Kuniyasu Kawarada
Masao Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP1316278A priority Critical patent/JPS54106136A/en
Publication of JPS54106136A publication Critical patent/JPS54106136A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/415—Address circuits

Abstract

PURPOSE:To ensure the high-speed address access by giving the level shift to the signal detected by the collector of the transistor which drives the semiconductor memory device and then using the shifted signal at the input of the line array wire discharge current switch circuit. CONSTITUTION:Signal detecting load resistance R is connected between the collectors and the earth of line array wire driving transistor T1 and T2 of the emitter follower, and voltage V6 and V7 of node 6 and 7 are connected to the bases of current switching TrT5 and T6 whose emitters are connected to discharge power source IDC via level shift circuit 22. When the address input signal varies with output V3 of line decoder circuit 2 varied from High to Low and output V4 varied from Low to High, TrT1 is immediately turned off with collector potential Vb turned to the earth potential. This potential turns on only T5 amoung current switching Tr's via circuit 22 and continues to absorb the current dischared from lower line array wire 11 to promote the change of wire 11 to low level VL of the steady condition, thus contributing to the high speed. When wire 11 reaches VL, TrT1 is turned on again.
JP1316278A 1978-02-08 1978-02-08 Semiconductor memory device Pending JPS54106136A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1316278A JPS54106136A (en) 1978-02-08 1978-02-08 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1316278A JPS54106136A (en) 1978-02-08 1978-02-08 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS54106136A true JPS54106136A (en) 1979-08-20

Family

ID=11825466

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1316278A Pending JPS54106136A (en) 1978-02-08 1978-02-08 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS54106136A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0056206A1 (en) * 1980-12-11 1982-07-21 FAIRCHILD CAMERA & INSTRUMENT CORPORATION Adaptive word line pull down
JPS58128088A (en) * 1982-01-18 1983-07-30 フエアチアイルド・カメラ・アンド・インストルメント・コ−ポレ−シヨン Current damping circuit for bipola random access memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0056206A1 (en) * 1980-12-11 1982-07-21 FAIRCHILD CAMERA & INSTRUMENT CORPORATION Adaptive word line pull down
JPS58128088A (en) * 1982-01-18 1983-07-30 フエアチアイルド・カメラ・アンド・インストルメント・コ−ポレ−シヨン Current damping circuit for bipola random access memory

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