JPS5383440A - Memory unit for information delay - Google Patents

Memory unit for information delay

Info

Publication number
JPS5383440A
JPS5383440A JP15943876A JP15943876A JPS5383440A JP S5383440 A JPS5383440 A JP S5383440A JP 15943876 A JP15943876 A JP 15943876A JP 15943876 A JP15943876 A JP 15943876A JP S5383440 A JPS5383440 A JP S5383440A
Authority
JP
Japan
Prior art keywords
memory unit
information delay
parallel
serial
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15943876A
Other languages
Japanese (ja)
Inventor
Nobuo Amano
Tetsusuke Mise
Tominobu Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP15943876A priority Critical patent/JPS5383440A/en
Publication of JPS5383440A publication Critical patent/JPS5383440A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers

Landscapes

  • Shift Register Type Memory (AREA)

Abstract

PURPOSE:To achieve an information delay memory unit by using shift register SR and RAM plus the serial-parallel and parallel-serial conversion SR, and to ensure a variable control of the memory capacity by using a low-speed SR with increased economical performance.
JP15943876A 1976-12-28 1976-12-28 Memory unit for information delay Pending JPS5383440A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15943876A JPS5383440A (en) 1976-12-28 1976-12-28 Memory unit for information delay

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15943876A JPS5383440A (en) 1976-12-28 1976-12-28 Memory unit for information delay

Publications (1)

Publication Number Publication Date
JPS5383440A true JPS5383440A (en) 1978-07-22

Family

ID=15693745

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15943876A Pending JPS5383440A (en) 1976-12-28 1976-12-28 Memory unit for information delay

Country Status (1)

Country Link
JP (1) JPS5383440A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60263400A (en) * 1984-06-08 1985-12-26 Nippon Telegr & Teleph Corp <Ntt> Shift register array

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49131550A (en) * 1973-04-05 1974-12-17
JPS50126140A (en) * 1974-03-22 1975-10-03

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49131550A (en) * 1973-04-05 1974-12-17
JPS50126140A (en) * 1974-03-22 1975-10-03

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60263400A (en) * 1984-06-08 1985-12-26 Nippon Telegr & Teleph Corp <Ntt> Shift register array

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