JPS5352064A - Method and unit for wire bonding - Google Patents

Method and unit for wire bonding

Info

Publication number
JPS5352064A
JPS5352064A JP12611376A JP12611376A JPS5352064A JP S5352064 A JPS5352064 A JP S5352064A JP 12611376 A JP12611376 A JP 12611376A JP 12611376 A JP12611376 A JP 12611376A JP S5352064 A JPS5352064 A JP S5352064A
Authority
JP
Japan
Prior art keywords
unit
wire bonding
wire
bonding
accelerate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12611376A
Other languages
Japanese (ja)
Inventor
Shunei Uematsu
Shunichiro Fujioka
Michio Tanimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12611376A priority Critical patent/JPS5352064A/en
Publication of JPS5352064A publication Critical patent/JPS5352064A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Pressure Welding/Diffusion-Bonding (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: To accelerate a work speed and improve efficiency by wire-bonding between two points by the ultrasonic bonding method while rotating a successive lead frame.
COPYRIGHT: (C)1978,JPO&Japio
JP12611376A 1976-10-22 1976-10-22 Method and unit for wire bonding Pending JPS5352064A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12611376A JPS5352064A (en) 1976-10-22 1976-10-22 Method and unit for wire bonding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12611376A JPS5352064A (en) 1976-10-22 1976-10-22 Method and unit for wire bonding

Publications (1)

Publication Number Publication Date
JPS5352064A true JPS5352064A (en) 1978-05-12

Family

ID=14926943

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12611376A Pending JPS5352064A (en) 1976-10-22 1976-10-22 Method and unit for wire bonding

Country Status (1)

Country Link
JP (1) JPS5352064A (en)

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