JPS53110437A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPS53110437A
JPS53110437A JP2620977A JP2620977A JPS53110437A JP S53110437 A JPS53110437 A JP S53110437A JP 2620977 A JP2620977 A JP 2620977A JP 2620977 A JP2620977 A JP 2620977A JP S53110437 A JPS53110437 A JP S53110437A
Authority
JP
Japan
Prior art keywords
logic circuit
circuit
circuits
input
speed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2620977A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5713174B2 (enExample
Inventor
Hirohiko Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2620977A priority Critical patent/JPS53110437A/ja
Publication of JPS53110437A publication Critical patent/JPS53110437A/ja
Publication of JPS5713174B2 publication Critical patent/JPS5713174B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
JP2620977A 1977-03-09 1977-03-09 Logic circuit Granted JPS53110437A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2620977A JPS53110437A (en) 1977-03-09 1977-03-09 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2620977A JPS53110437A (en) 1977-03-09 1977-03-09 Logic circuit

Publications (2)

Publication Number Publication Date
JPS53110437A true JPS53110437A (en) 1978-09-27
JPS5713174B2 JPS5713174B2 (enExample) 1982-03-16

Family

ID=12187050

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2620977A Granted JPS53110437A (en) 1977-03-09 1977-03-09 Logic circuit

Country Status (1)

Country Link
JP (1) JPS53110437A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6331313A (ja) * 1986-07-21 1988-02-10 シ−メンス、アクチエンゲゼルシヤフト レベル変換のための集積可能な回路装置
JPH05103961A (ja) * 1991-10-14 1993-04-27 Kyowa Densen Kk ペレツトの落下混合方法と装置

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6036179U (ja) * 1983-08-12 1985-03-12 株式会社　潤工社 書類綴じ具
JPS60133843U (ja) * 1984-02-16 1985-09-06 コニカ株式会社 給紙装置
JPS63196387A (ja) * 1987-02-12 1988-08-15 谷口　喜秋 針の散乱防止
JPH0340086U (enExample) * 1989-08-31 1991-04-17
JPH0344570U (enExample) * 1989-09-07 1991-04-25
JPH0365678U (enExample) * 1989-10-30 1991-06-26

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6331313A (ja) * 1986-07-21 1988-02-10 シ−メンス、アクチエンゲゼルシヤフト レベル変換のための集積可能な回路装置
JPH05103961A (ja) * 1991-10-14 1993-04-27 Kyowa Densen Kk ペレツトの落下混合方法と装置

Also Published As

Publication number Publication date
JPS5713174B2 (enExample) 1982-03-16

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