JPS5223064B2 - - Google Patents

Info

Publication number
JPS5223064B2
JPS5223064B2 JP46104939A JP10493971A JPS5223064B2 JP S5223064 B2 JPS5223064 B2 JP S5223064B2 JP 46104939 A JP46104939 A JP 46104939A JP 10493971 A JP10493971 A JP 10493971A JP S5223064 B2 JPS5223064 B2 JP S5223064B2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP46104939A
Other languages
Japanese (ja)
Other versions
JPS4869057A (en:Method
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP46104939A priority Critical patent/JPS5223064B2/ja
Publication of JPS4869057A publication Critical patent/JPS4869057A/ja
Publication of JPS5223064B2 publication Critical patent/JPS5223064B2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)
JP46104939A 1971-12-23 1971-12-23 Expired JPS5223064B2 (en:Method)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP46104939A JPS5223064B2 (en:Method) 1971-12-23 1971-12-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP46104939A JPS5223064B2 (en:Method) 1971-12-23 1971-12-23

Publications (2)

Publication Number Publication Date
JPS4869057A JPS4869057A (en:Method) 1973-09-20
JPS5223064B2 true JPS5223064B2 (en:Method) 1977-06-22

Family

ID=14394047

Family Applications (1)

Application Number Title Priority Date Filing Date
JP46104939A Expired JPS5223064B2 (en:Method) 1971-12-23 1971-12-23

Country Status (1)

Country Link
JP (1) JPS5223064B2 (en:Method)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59109910A (ja) * 1982-12-15 1984-06-25 Komatsu Ltd ロボツトのテイ−チング方法
JPS60132208A (ja) * 1983-12-21 1985-07-15 Amada Co Ltd 可動体の移動範囲制御方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5640513B2 (en:Method) * 1973-12-04 1981-09-21
JPS5145761A (en) * 1974-10-18 1976-04-19 Nippon Electric Co Denkibuhinno setsuzokuhoho
JPS5416669A (en) * 1977-07-07 1979-02-07 Mitsubishi Electric Corp Method of manufacturing hybrid integrated circuit device
JPS58223396A (ja) * 1982-06-18 1983-12-24 ウラジミ−ル・イオシフオウイツチ・リブシツ 超小型電子装置に使用するパネルを製造する方法
JP2753746B2 (ja) * 1989-11-06 1998-05-20 日本メクトロン株式会社 Ic搭載用可撓性回路基板及びその製造法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59109910A (ja) * 1982-12-15 1984-06-25 Komatsu Ltd ロボツトのテイ−チング方法
JPS60132208A (ja) * 1983-12-21 1985-07-15 Amada Co Ltd 可動体の移動範囲制御方法

Also Published As

Publication number Publication date
JPS4869057A (en:Method) 1973-09-20

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