JPS5416669A - Method of manufacturing hybrid integrated circuit device - Google Patents

Method of manufacturing hybrid integrated circuit device

Info

Publication number
JPS5416669A
JPS5416669A JP8162277A JP8162277A JPS5416669A JP S5416669 A JPS5416669 A JP S5416669A JP 8162277 A JP8162277 A JP 8162277A JP 8162277 A JP8162277 A JP 8162277A JP S5416669 A JPS5416669 A JP S5416669A
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
hybrid integrated
manufacturing hybrid
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8162277A
Other languages
Japanese (ja)
Inventor
Masayuki Kataoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8162277A priority Critical patent/JPS5416669A/en
Publication of JPS5416669A publication Critical patent/JPS5416669A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
JP8162277A 1977-07-07 1977-07-07 Method of manufacturing hybrid integrated circuit device Pending JPS5416669A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8162277A JPS5416669A (en) 1977-07-07 1977-07-07 Method of manufacturing hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8162277A JPS5416669A (en) 1977-07-07 1977-07-07 Method of manufacturing hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5416669A true JPS5416669A (en) 1979-02-07

Family

ID=13751419

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8162277A Pending JPS5416669A (en) 1977-07-07 1977-07-07 Method of manufacturing hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5416669A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56138979A (en) * 1980-03-31 1981-10-29 Nippon Electric Co Circuit board
JPS61164072U (en) * 1986-03-19 1986-10-11
JP2017022228A (en) * 2015-07-09 2017-01-26 ローム株式会社 Semiconductor device and manufacturing method of the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4869057A (en) * 1971-12-23 1973-09-20
JPS4939933A (en) * 1972-08-25 1974-04-15

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4869057A (en) * 1971-12-23 1973-09-20
JPS4939933A (en) * 1972-08-25 1974-04-15

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56138979A (en) * 1980-03-31 1981-10-29 Nippon Electric Co Circuit board
JPS61164072U (en) * 1986-03-19 1986-10-11
JP2017022228A (en) * 2015-07-09 2017-01-26 ローム株式会社 Semiconductor device and manufacturing method of the same

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