JPS52155027A - Multi-input adder for single-width data and double-width data - Google Patents

Multi-input adder for single-width data and double-width data

Info

Publication number
JPS52155027A
JPS52155027A JP7194276A JP7194276A JPS52155027A JP S52155027 A JPS52155027 A JP S52155027A JP 7194276 A JP7194276 A JP 7194276A JP 7194276 A JP7194276 A JP 7194276A JP S52155027 A JPS52155027 A JP S52155027A
Authority
JP
Japan
Prior art keywords
width data
double
input adder
adder
width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7194276A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5521376B2 (cs
Inventor
Satoru Kawai
Tetsuo Okamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7194276A priority Critical patent/JPS52155027A/ja
Publication of JPS52155027A publication Critical patent/JPS52155027A/ja
Publication of JPS5521376B2 publication Critical patent/JPS5521376B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3812—Devices capable of handling different types of numbers
    • G06F2207/382—Reconfigurable for different fixed word lengths
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
JP7194276A 1976-06-18 1976-06-18 Multi-input adder for single-width data and double-width data Granted JPS52155027A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7194276A JPS52155027A (en) 1976-06-18 1976-06-18 Multi-input adder for single-width data and double-width data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7194276A JPS52155027A (en) 1976-06-18 1976-06-18 Multi-input adder for single-width data and double-width data

Publications (2)

Publication Number Publication Date
JPS52155027A true JPS52155027A (en) 1977-12-23
JPS5521376B2 JPS5521376B2 (cs) 1980-06-09

Family

ID=13475053

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7194276A Granted JPS52155027A (en) 1976-06-18 1976-06-18 Multi-input adder for single-width data and double-width data

Country Status (1)

Country Link
JP (1) JPS52155027A (cs)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5599648A (en) * 1979-01-24 1980-07-29 Toshiba Corp Data processor
JPS58132862A (ja) * 1982-01-30 1983-08-08 Sairatsuku:Kk 座標変換回路
JPS6152740A (ja) * 1984-08-22 1986-03-15 Hitachi Ltd マージ・ソート方法および装置
JPS623329A (ja) * 1985-06-28 1987-01-09 Nec Corp 演算回路
EP1052568A1 (en) * 1999-05-12 2000-11-15 Lucent Technologies Inc. Three input split-adder

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5043851A (cs) * 1973-08-21 1975-04-19

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5043851A (cs) * 1973-08-21 1975-04-19

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5599648A (en) * 1979-01-24 1980-07-29 Toshiba Corp Data processor
JPS58132862A (ja) * 1982-01-30 1983-08-08 Sairatsuku:Kk 座標変換回路
JPS6152740A (ja) * 1984-08-22 1986-03-15 Hitachi Ltd マージ・ソート方法および装置
JPS623329A (ja) * 1985-06-28 1987-01-09 Nec Corp 演算回路
EP1052568A1 (en) * 1999-05-12 2000-11-15 Lucent Technologies Inc. Three input split-adder
EP1052568B1 (en) * 1999-05-12 2004-01-28 Agere Systems Optoelectronics Guardian Corporation Three input split-adder

Also Published As

Publication number Publication date
JPS5521376B2 (cs) 1980-06-09

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