JPS52152132A - Carry siganl generator circuit - Google Patents

Carry siganl generator circuit

Info

Publication number
JPS52152132A
JPS52152132A JP6996576A JP6996576A JPS52152132A JP S52152132 A JPS52152132 A JP S52152132A JP 6996576 A JP6996576 A JP 6996576A JP 6996576 A JP6996576 A JP 6996576A JP S52152132 A JPS52152132 A JP S52152132A
Authority
JP
Japan
Prior art keywords
generator circuit
carry
siganl
carry signal
shortened
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6996576A
Other languages
Japanese (ja)
Other versions
JPS5442573B2 (en
Inventor
Teruhiko Kyogoku
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP6996576A priority Critical patent/JPS52152132A/en
Publication of JPS52152132A publication Critical patent/JPS52152132A/en
Publication of JPS5442573B2 publication Critical patent/JPS5442573B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:The CMOS logical circuit is constituted in the symmetric geometrical arrangement to realize a carry signal generator circuit and the operation time at each digit of the carry signal is shortened, so that the operation timerequired for the whole carry signal generation can be shortened.
JP6996576A 1976-06-14 1976-06-14 Carry siganl generator circuit Granted JPS52152132A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6996576A JPS52152132A (en) 1976-06-14 1976-06-14 Carry siganl generator circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6996576A JPS52152132A (en) 1976-06-14 1976-06-14 Carry siganl generator circuit

Publications (2)

Publication Number Publication Date
JPS52152132A true JPS52152132A (en) 1977-12-17
JPS5442573B2 JPS5442573B2 (en) 1979-12-14

Family

ID=13417862

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6996576A Granted JPS52152132A (en) 1976-06-14 1976-06-14 Carry siganl generator circuit

Country Status (1)

Country Link
JP (1) JPS52152132A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5518706A (en) * 1978-07-24 1980-02-09 Hitachi Ltd Parallel adder circuit
JPS5876947A (en) * 1981-10-27 1983-05-10 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Digital adder
JPS5981736A (en) * 1982-09-30 1984-05-11 アールシーエー　ライセンシング　コーポレーシヨン Carry signal generation circuit for digital adder
JPS6039240A (en) * 1983-08-10 1985-03-01 Mitsubishi Electric Corp Adder
JPS60215238A (en) * 1984-04-10 1985-10-28 Mitsubishi Electric Corp Adder
JPS61110237A (en) * 1984-11-01 1986-05-28 レイセオン　カンパニ− Multi-bit digital adder
EP0291963A2 (en) * 1987-05-20 1988-11-23 CSELT Centro Studi e Laboratori Telecomunicazioni S.p.A. Fast C-MOS adder

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5518706A (en) * 1978-07-24 1980-02-09 Hitachi Ltd Parallel adder circuit
JPS5876947A (en) * 1981-10-27 1983-05-10 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Digital adder
JPH0310973B2 (en) * 1981-10-27 1991-02-14 Intaanashonaru Bijinesu Mashiinzu Corp
JPS5981736A (en) * 1982-09-30 1984-05-11 アールシーエー　ライセンシング　コーポレーシヨン Carry signal generation circuit for digital adder
JPS6039240A (en) * 1983-08-10 1985-03-01 Mitsubishi Electric Corp Adder
JPH0236006B2 (en) * 1983-08-10 1990-08-15 Mitsubishi Electric Corp
JPS60215238A (en) * 1984-04-10 1985-10-28 Mitsubishi Electric Corp Adder
JPS61110237A (en) * 1984-11-01 1986-05-28 レイセオン　カンパニ− Multi-bit digital adder
EP0291963A2 (en) * 1987-05-20 1988-11-23 CSELT Centro Studi e Laboratori Telecomunicazioni S.p.A. Fast C-MOS adder
EP0291963A3 (en) * 1987-05-20 1991-03-06 CSELT Centro Studi e Laboratori Telecomunicazioni S.p.A. Fast c-mos adder

Also Published As

Publication number Publication date
JPS5442573B2 (en) 1979-12-14

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