JPS52122014A - Data processor - Google Patents

Data processor

Info

Publication number
JPS52122014A
JPS52122014A JP2372777A JP2372777A JPS52122014A JP S52122014 A JPS52122014 A JP S52122014A JP 2372777 A JP2372777 A JP 2372777A JP 2372777 A JP2372777 A JP 2372777A JP S52122014 A JPS52122014 A JP S52122014A
Authority
JP
Japan
Prior art keywords
devices
central processing
processing device
loop
display signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2372777A
Other languages
Japanese (ja)
Inventor
Barrie Leslie Brinkman
Peter John Newton
Robert David Hodson
David Victor Windsor
David George Norbury
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Post Office
Original Assignee
Post Office
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Post Office filed Critical Post Office
Publication of JPS52122014A publication Critical patent/JPS52122014A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
    • G06F11/2007—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication media
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/3495—Performance evaluation by tracing or monitoring for systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M15/00—Arrangements for metering, time-control or time indication ; Metering, charging or billing arrangements for voice wireline or wireless communications, e.g. VoIP
    • H04M15/04—Recording calls, or communications in printed, perforated or other permanent form
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges
    • H04M3/22—Arrangements for supervision, monitoring or testing
    • H04M3/24—Arrangements for supervision, monitoring or testing with provision for checking the normal operation
    • H04M3/241—Arrangements for supervision, monitoring or testing with provision for checking the normal operation for stored program controlled exchanges
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54575—Software application
    • H04Q3/54591—Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2035—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant without idle spare hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/2736—Tester hardware, i.e. output processing circuits using a dedicated service processor for test

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Meter Arrangements (AREA)
  • Monitoring And Testing Of Exchanges (AREA)
  • Financial Or Insurance-Related Operations Such As Payment And Settlement (AREA)
  • Debugging And Monitoring (AREA)

Abstract

In order to simplify the charging and accounting procedures in a telephone network and, at the same time, to carry these out in a more reliable manner, the system exhibits a multiplicity of switching devices (11, 12, 18; 21, 22, 28; 31, 32, 38) with keyboards and display devices. These are connected group by group to control devices (10, 20, 30) for the user which respond to commands keyed in in order to obtain data from peripheral storage devices and to record details of the telephone connections on magnetic tape. Each control and peripheral device exhibits microprocessors for controlling the individual functions and carrying out tests which determine the operating states of the devices and generate relevant display signals. All these devices are connected to a monitor (6) for recording these display signals. Each device can exhibit a monitoring clock generator with a counter. The latter is regularly incremented and periodically set to zero, responding to a software command. Thus, when a central processing device enters a software loop, the counter exceeds a threshold value and generates a signal indicating the presence of such a loop. The same timing generator can also reset the central processing device into a starting position and delete all data recorded as consequence of a program execution up to this time. Finally, there can be a diagnostics device so that a technician can carry out routine checks of the individual devices. <IMAGE>
JP2372777A 1976-03-04 1977-03-04 Data processor Pending JPS52122014A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8669/76A GB1572892A (en) 1976-03-04 1976-03-04 Data processing equipment

Publications (1)

Publication Number Publication Date
JPS52122014A true JPS52122014A (en) 1977-10-13

Family

ID=9856951

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2372777A Pending JPS52122014A (en) 1976-03-04 1977-03-04 Data processor

Country Status (13)

Country Link
JP (1) JPS52122014A (en)
AU (1) AU512449B2 (en)
CA (1) CA1094209A (en)
CH (1) CH623948A5 (en)
DE (1) DE2708983A1 (en)
DK (1) DK93077A (en)
ES (1) ES456515A1 (en)
FR (1) FR2343379A1 (en)
GB (1) GB1572892A (en)
IT (1) IT1080010B (en)
NL (1) NL7702371A (en)
NO (1) NO147853C (en)
SE (1) SE7702325L (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1572895A (en) * 1976-03-04 1980-08-06 Post Office Data processing equipment
GB1572894A (en) * 1976-03-04 1980-08-06 Post Office Data processing equipment
GB1572893A (en) * 1976-03-04 1980-08-06 Post Office Data processing equipment
DE2964624D1 (en) * 1978-10-23 1983-03-03 Ibm Data processing system with channel error logging
FR2440032A1 (en) * 1978-10-25 1980-05-23 Standard Telephones Cables Ltd Master and slaverocessor system - has monitoring and test routines and carries out addition processes on words from memory to be checked in cyclic order by control
IT8003504A0 (en) * 1980-09-05 1980-09-05 Sits Soc It Telecom Siemens EQUIPMENT FOR THE MANAGEMENT OF AUXILIARY INFORMATION RELEVANT TO A CENTRAL CONTROL OF A PLURALITY OF PERIPHERAL USERS AND FOR THE DIAGNOSIS OF THE SAME CENTRAL CONTROL
FR2490842A1 (en) * 1980-09-23 1982-03-26 Renix Electronique Sa ELECTRONIC ADAPTER DEVICE OF A DIAGNOSTIC SOCKET WITH INFORMATION PROVIDED BY AN ELECTRONIC CONTROL CIRCUIT
FR2606184B1 (en) * 1986-10-31 1991-11-29 Thomson Csf RECONFIGURABLE CALCULATION DEVICE

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL6704309A (en) * 1966-03-25 1967-09-26
US3921141A (en) * 1973-09-14 1975-11-18 Gte Automatic Electric Lab Inc Malfunction monitor control circuitry for central data processor of digital communication system
US3882455A (en) * 1973-09-14 1975-05-06 Gte Automatic Electric Lab Inc Configuration control circuit for control and maintenance complex of digital communications system

Also Published As

Publication number Publication date
SE7702325L (en) 1977-09-05
ES456515A1 (en) 1978-02-16
AU2275177A (en) 1978-09-07
CH623948A5 (en) 1981-06-30
DK93077A (en) 1977-09-05
AU512449B2 (en) 1980-10-09
FR2343379A1 (en) 1977-09-30
NO770729L (en) 1977-09-06
DE2708983A1 (en) 1977-09-08
NO147853B (en) 1983-03-14
NO147853C (en) 1983-06-22
IT1080010B (en) 1985-05-16
CA1094209A (en) 1981-01-20
GB1572892A (en) 1980-08-06
NL7702371A (en) 1977-09-06

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