JPS5142476A - Handotaisochino seizohoho - Google Patents

Handotaisochino seizohoho

Info

Publication number
JPS5142476A
JPS5142476A JP50096322A JP9632275A JPS5142476A JP S5142476 A JPS5142476 A JP S5142476A JP 50096322 A JP50096322 A JP 50096322A JP 9632275 A JP9632275 A JP 9632275A JP S5142476 A JPS5142476 A JP S5142476A
Authority
JP
Japan
Prior art keywords
handotaisochino seizohoho
handotaisochino
seizohoho
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP50096322A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5319900B2 (US07579456-20090825-P00002.png
Inventor
Do Purebison Mitsusheru
Jeraaru Monfure Arain
Mitsusheru Dekuroen Jan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of JPS5142476A publication Critical patent/JPS5142476A/ja
Publication of JPS5319900B2 publication Critical patent/JPS5319900B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/037—Diffusion-deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/102—Mask alignment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/136—Resistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/151—Simultaneous diffusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/975—Substrate or mask aligning feature

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Bipolar Transistors (AREA)
  • Drying Of Semiconductors (AREA)
JP50096322A 1974-08-12 1975-08-09 Handotaisochino seizohoho Granted JPS5142476A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7427905A FR2282162A1 (fr) 1974-08-12 1974-08-12 Procede de realisation de dispositifs semiconducteurs

Publications (2)

Publication Number Publication Date
JPS5142476A true JPS5142476A (en) 1976-04-10
JPS5319900B2 JPS5319900B2 (US07579456-20090825-P00002.png) 1978-06-23

Family

ID=9142340

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50096322A Granted JPS5142476A (en) 1974-08-12 1975-08-09 Handotaisochino seizohoho

Country Status (7)

Country Link
US (1) US4009057A (US07579456-20090825-P00002.png)
JP (1) JPS5142476A (US07579456-20090825-P00002.png)
CA (1) CA1035471A (US07579456-20090825-P00002.png)
DE (1) DE2534132C3 (US07579456-20090825-P00002.png)
FR (1) FR2282162A1 (US07579456-20090825-P00002.png)
GB (1) GB1515184A (US07579456-20090825-P00002.png)
NL (1) NL7509464A (US07579456-20090825-P00002.png)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4151019A (en) * 1974-12-27 1979-04-24 Tokyo Shibaura Electric Co., Ltd. Method of manufacturing integrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques
US4153487A (en) * 1974-12-27 1979-05-08 Tokyo Shibaura Electric Co., Ltd. Method of manufacturing intergrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques
US4110126A (en) * 1977-08-31 1978-08-29 International Business Machines Corporation NPN/PNP Fabrication process with improved alignment
US4118250A (en) * 1977-12-30 1978-10-03 International Business Machines Corporation Process for producing integrated circuit devices by ion implantation
US4201800A (en) * 1978-04-28 1980-05-06 International Business Machines Corp. Hardened photoresist master image mask process
US4244752A (en) * 1979-03-06 1981-01-13 Burroughs Corporation Single mask method of fabricating complementary integrated circuits
US5219770A (en) * 1983-11-30 1993-06-15 Fujitsu Limited Method for fabricating a MISFET including a common contact window
US4648909A (en) * 1984-11-28 1987-03-10 Fairchild Semiconductor Corporation Fabrication process employing special masks for the manufacture of high speed bipolar analog integrated circuits
US4829018A (en) * 1986-06-27 1989-05-09 Wahlstrom Sven E Multilevel integrated circuits employing fused oxide layers
US4843026A (en) * 1987-09-24 1989-06-27 Intel Corporation Architecture modification for improved ROM security
JP2575795B2 (ja) * 1988-04-28 1997-01-29 富士通株式会社 半導体装置の製造方法
JPH06101540B2 (ja) * 1989-05-19 1994-12-12 三洋電機株式会社 半導体集積回路の製造方法
DE69332006T2 (de) * 1992-03-25 2002-11-28 Texas Instruments Inc., Dallas Planares Verfahren unter Verwendung von gemeinsamen Ausrichtungsmarken für die Wannenimplantierungen

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3697318A (en) * 1967-05-23 1972-10-10 Ibm Monolithic integrated structure including fabrication thereof
US3640782A (en) * 1967-10-13 1972-02-08 Gen Electric Diffusion masking in semiconductor preparation
US3560278A (en) * 1968-11-29 1971-02-02 Motorola Inc Alignment process for fabricating semiconductor devices
GB1355806A (en) * 1970-12-09 1974-06-05 Mullard Ltd Methods of manufacturing a semiconductor device
DE2157633C3 (de) * 1971-11-20 1980-01-24 Deutsche Itt Industries Gmbh, 7800 Freiburg Verfahren zum Herstellen von Zonen einer monolithisch integrierten Festkörperschaltung
JPS5538823B2 (US07579456-20090825-P00002.png) * 1971-12-22 1980-10-07
GB1384028A (en) * 1972-08-21 1974-02-12 Hughes Aircraft Co Method of making a semiconductor device
US3793088A (en) * 1972-11-15 1974-02-19 Bell Telephone Labor Inc Compatible pnp and npn devices in an integrated circuit

Also Published As

Publication number Publication date
DE2534132C3 (de) 1978-06-01
CA1035471A (en) 1978-07-25
FR2282162B1 (US07579456-20090825-P00002.png) 1978-04-28
DE2534132B2 (de) 1977-10-13
GB1515184A (en) 1978-06-21
FR2282162A1 (fr) 1976-03-12
US4009057A (en) 1977-02-22
NL7509464A (nl) 1976-02-16
DE2534132A1 (de) 1976-02-26
JPS5319900B2 (US07579456-20090825-P00002.png) 1978-06-23

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