JPS5114257A - - Google Patents

Info

Publication number
JPS5114257A
JPS5114257A JP50072777A JP7277775A JPS5114257A JP S5114257 A JPS5114257 A JP S5114257A JP 50072777 A JP50072777 A JP 50072777A JP 7277775 A JP7277775 A JP 7277775A JP S5114257 A JPS5114257 A JP S5114257A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50072777A
Other languages
Japanese (ja)
Inventor
Aaru Meruzuin Kurodo
Emu Ruujo Kurodo
Jei Shii Uerunu Patoriisu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS5114257A publication Critical patent/JPS5114257A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C48/00—Extrusion moulding, i.e. expressing the moulding material through a die or nozzle which imparts the desired form; Apparatus therefor
    • B29C48/03—Extrusion moulding, i.e. expressing the moulding material through a die or nozzle which imparts the desired form; Apparatus therefor characterised by the shape of the extruded material at extrusion
    • B29C48/09—Articles with cross-sections having partially or fully enclosed cavities, e.g. pipes or channels
    • B29C48/10—Articles with cross-sections having partially or fully enclosed cavities, e.g. pipes or channels flexible, e.g. blown foils
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/858—Complementary IGFETs, e.g. CMOS comprising a P-type well but not an N-type well

Landscapes

  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
JP50072777A 1974-06-28 1975-06-17 Pending JPS5114257A (en:Method)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7424577*A FR2276694A1 (fr) 1974-06-28 1974-06-28 Circuit logique integre du genre ou exclusif a transistors complementaires mosfet

Publications (1)

Publication Number Publication Date
JPS5114257A true JPS5114257A (en:Method) 1976-02-04

Family

ID=9141290

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50072777A Pending JPS5114257A (en:Method) 1974-06-28 1975-06-17

Country Status (4)

Country Link
JP (1) JPS5114257A (en:Method)
DE (1) DE2519486A1 (en:Method)
FR (1) FR2276694A1 (en:Method)
GB (1) GB1489007A (en:Method)

Also Published As

Publication number Publication date
DE2519486A1 (de) 1976-01-15
FR2276694A1 (fr) 1976-01-23
FR2276694B1 (en:Method) 1976-12-24
GB1489007A (en) 1977-10-19

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