JPS505539B1 - - Google Patents

Info

Publication number
JPS505539B1
JPS505539B1 JP45003323A JP332370A JPS505539B1 JP S505539 B1 JPS505539 B1 JP S505539B1 JP 45003323 A JP45003323 A JP 45003323A JP 332370 A JP332370 A JP 332370A JP S505539 B1 JPS505539 B1 JP S505539B1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP45003323A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS505539B1 publication Critical patent/JPS505539B1/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3846—Speculative instruction execution using static prediction, e.g. branch taken strategy

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
JP45003323A 1969-01-15 1970-01-13 Pending JPS505539B1 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US79125569A 1969-01-15 1969-01-15

Publications (1)

Publication Number Publication Date
JPS505539B1 true JPS505539B1 (ja) 1975-03-05

Family

ID=25153135

Family Applications (1)

Application Number Title Priority Date Filing Date
JP45003323A Pending JPS505539B1 (ja) 1969-01-15 1970-01-13

Country Status (6)

Country Link
US (1) US3577189A (ja)
JP (1) JPS505539B1 (ja)
CA (1) CA931272A (ja)
DE (1) DE2001664B2 (ja)
FR (1) FR2031085A5 (ja)
GB (1) GB1282341A (ja)

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3725868A (en) * 1970-10-19 1973-04-03 Burroughs Corp Small reconfigurable processor for a variety of data processing applications
US3764988A (en) * 1971-03-01 1973-10-09 Hitachi Ltd Instruction processing device using advanced control system
US3699526A (en) * 1971-03-26 1972-10-17 Ibm Program selection based upon intrinsic characteristics of an instruction stream
US3728692A (en) * 1971-08-31 1973-04-17 Ibm Instruction selection in a two-program counter instruction unit
JPS54613B2 (ja) * 1971-10-04 1979-01-12
US3753236A (en) * 1972-03-31 1973-08-14 Honeywell Inf Systems Microprogrammable peripheral controller
US3959777A (en) * 1972-07-17 1976-05-25 International Business Machines Corporation Data processor for pattern recognition and the like
JPS545942B2 (ja) * 1972-10-07 1979-03-23
JPS5413949B2 (ja) * 1973-05-14 1979-06-04
US3881173A (en) * 1973-05-14 1975-04-29 Amdahl Corp Condition code determination and data processing
US3922538A (en) * 1973-09-13 1975-11-25 Texas Instruments Inc Calculator system featuring relative program memory
JPS50114944A (ja) * 1974-02-18 1975-09-09
US4212060A (en) * 1975-04-30 1980-07-08 Siemens Aktiengesellschaft Method and apparatus for controlling the sequence of instructions in stored-program computers
US4062058A (en) * 1976-02-13 1977-12-06 The United States Of America As Represented By The Secretary Of The Navy Next address subprocessor
ES474427A1 (es) * 1977-10-25 1979-04-16 Digital Equipment Corp Un aparato central de tratamiento para uso en un sistema de tratamiento de datos.
US4181942A (en) * 1978-03-31 1980-01-01 International Business Machines Corporation Program branching method and apparatus
JPS5927935B2 (ja) * 1980-02-29 1984-07-09 株式会社日立製作所 情報処理装置
US5440704A (en) * 1986-08-26 1995-08-08 Mitsubishi Denki Kabushiki Kaisha Data processor having branch predicting function
US4974155A (en) * 1988-08-15 1990-11-27 Evans & Sutherland Computer Corp. Variable delay branch system
DE4345028A1 (de) * 1993-05-06 1994-11-10 Hewlett Packard Co Vorrichtung zur Reduzierung von Verzögerungen aufgrund von Verzweigungen
GB9412487D0 (en) * 1994-06-22 1994-08-10 Inmos Ltd A computer system for executing branch instructions
JP2982618B2 (ja) * 1994-06-28 1999-11-29 日本電気株式会社 メモリ選択回路
US5664135A (en) * 1994-09-28 1997-09-02 Hewlett-Packard Company Apparatus and method for reducing delays due to branches
KR20010023562A (ko) 1997-09-02 2001-03-26 토레스 데이몬 씨. 자동화된 내용 스케줄러 및 디스플레이어
US6427179B1 (en) * 1997-10-01 2002-07-30 Globespanvirata, Inc. System and method for protocol conversion in a communications system
JP3741870B2 (ja) * 1998-08-07 2006-02-01 富士通株式会社 命令及びデータの先読み方法、マイクロコントローラ、疑似命令検出回路
US6243805B1 (en) * 1998-08-11 2001-06-05 Advanced Micro Devices, Inc. Programming paradigm and microprocessor architecture for exact branch targeting
US6289442B1 (en) 1998-10-05 2001-09-11 Advanced Micro Devices, Inc. Circuit and method for tagging and invalidating speculatively executed instructions
US6523110B1 (en) * 1999-07-23 2003-02-18 International Business Machines Corporation Decoupled fetch-execute engine with static branch prediction support
US6574728B1 (en) * 1999-08-10 2003-06-03 Cirrus Logic, Inc. Condition code stack architecture systems and methods
WO2001016702A1 (en) 1999-09-01 2001-03-08 Intel Corporation Register set used in multithreaded parallel processor architecture
WO2001016722A1 (en) * 1999-09-01 2001-03-08 Intel Corporation Branch instruction for processor
JP2001142692A (ja) * 1999-10-01 2001-05-25 Hitachi Ltd ２つの異なる固定長命令セットを実行するマイクロプロセッサ、マイクロコンピュータおよび命令実行方法
US6820193B1 (en) * 1999-12-17 2004-11-16 Koninklijke Philips Electronics N.V. Branch instructions with decoupled condition and address
US6594755B1 (en) * 2000-01-04 2003-07-15 National Semiconductor Corporation System and method for interleaved execution of multiple independent threads
US7085915B1 (en) * 2000-02-29 2006-08-01 International Business Machines Corporation Programmable prefetching of instructions for a processor executing a non-procedural program
JP3532835B2 (ja) * 2000-07-04 2004-05-31 松下電器産業株式会社 データ処理装置およびプログラム変換装置
US7681018B2 (en) * 2000-08-31 2010-03-16 Intel Corporation Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
US7114063B1 (en) * 2000-12-01 2006-09-26 Unisys Corporation Condition indicator for use by a conditional branch instruction
US6779108B2 (en) * 2000-12-15 2004-08-17 Intel Corporation Incorporating trigger loads in branch histories for branch prediction
US20030200342A1 (en) * 2001-07-02 2003-10-23 Globespan Virata Incorporated Communications system using rings architecture
US7167973B2 (en) * 2001-11-15 2007-01-23 Broadcom Corporation Method and system for performing multi-tests in processors using results to set a register and indexing based on the register
US7437724B2 (en) 2002-04-03 2008-10-14 Intel Corporation Registers for data transfers
US20050223385A1 (en) * 2004-03-31 2005-10-06 Christof Braun Method and structure for explicit software control of execution of a thread including a helper subthread
US20070006195A1 (en) * 2004-03-31 2007-01-04 Christof Braun Method and structure for explicit software control of data speculation
US7711928B2 (en) * 2004-03-31 2010-05-04 Oracle America, Inc. Method and structure for explicit software control using scoreboard status information
US7487334B2 (en) * 2005-02-03 2009-02-03 International Business Machines Corporation Branch encoding before instruction cache write
US20060212877A1 (en) * 2005-02-17 2006-09-21 Microsoft Corporation Cancellation mechanism
WO2008019528A1 (en) * 2006-08-08 2008-02-21 Intel Corporation Methods and apparatus to optimize computer instruction

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3297998A (en) * 1963-06-10 1967-01-10 Beckman Instruments Inc List control
GB1054725A (ja) * 1964-04-06
US3408630A (en) * 1966-03-25 1968-10-29 Burroughs Corp Digital computer having high speed branch operation
US3418638A (en) * 1966-09-21 1968-12-24 Ibm Instruction processing unit for program branches

Also Published As

Publication number Publication date
CA931272A (en) 1973-07-31
DE2001664B2 (de) 1971-12-16
GB1282341A (en) 1972-07-19
FR2031085A5 (ja) 1970-11-13
DE2001664A1 (de) 1970-07-23
US3577189A (en) 1971-05-04

Similar Documents

Publication Publication Date Title
FR2031085A5 (ja)
AU2270770A (ja)
AU465413B2 (ja)
AU450150B2 (ja)
CS151067B2 (ja)
CS153538B2 (ja)
AU470301B1 (ja)
AU5113869A (ja)
AU410358B2 (ja)
AT308690B (ja)
AU470661B1 (ja)
AU5228269A (ja)
AU5077469A (ja)
CS150090B1 (ja)
AU4540468A (ja)
CS151562B2 (ja)
CS149290B1 (ja)
CS148417B1 (ja)
AU1036070A (ja)
AU5598769A (ja)
AU4923469A (ja)
AR203167Q (ja)
AU5133369A (ja)
AU4949169A (ja)
AU5109569A (ja)