JPS50137484A - - Google Patents

Info

Publication number
JPS50137484A
JPS50137484A JP50026134A JP2613475A JPS50137484A JP S50137484 A JPS50137484 A JP S50137484A JP 50026134 A JP50026134 A JP 50026134A JP 2613475 A JP2613475 A JP 2613475A JP S50137484 A JPS50137484 A JP S50137484A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP50026134A
Other languages
Japanese (ja)
Other versions
JPS56945B2 (en:Method
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS50137484A publication Critical patent/JPS50137484A/ja
Publication of JPS56945B2 publication Critical patent/JPS56945B2/ja
Expired legal-status Critical Current

Links

Classifications

    • H10W70/60—
    • H10W70/05—
    • H10W70/611—
    • H10W70/69—
    • H10W70/698—
    • H10W90/724—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2613475A 1974-04-15 1975-03-05 Expired JPS56945B2 (en:Method)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US461078A US3918148A (en) 1974-04-15 1974-04-15 Integrated circuit chip carrier and method for forming the same

Publications (2)

Publication Number Publication Date
JPS50137484A true JPS50137484A (en:Method) 1975-10-31
JPS56945B2 JPS56945B2 (en:Method) 1981-01-10

Family

ID=23831131

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2613475A Expired JPS56945B2 (en:Method) 1974-04-15 1975-03-05

Country Status (7)

Country Link
US (1) US3918148A (en:Method)
JP (1) JPS56945B2 (en:Method)
CA (1) CA1026469A (en:Method)
DE (1) DE2510757C2 (en:Method)
FR (1) FR2267639B1 (en:Method)
GB (1) GB1457866A (en:Method)
IT (1) IT1033222B (en:Method)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5571091A (en) * 1978-11-24 1980-05-28 Hitachi Ltd Multilayer circuit board

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4045594A (en) * 1975-12-31 1977-08-30 Ibm Corporation Planar insulation of conductive patterns by chemical vapor deposition and sputtering
US4129904A (en) * 1977-11-14 1978-12-19 Pansini Andrew L Swimming pool cleaner
DE2755480A1 (de) * 1977-12-13 1979-06-21 Siemens Ag Verfahren zur herstellung einer integrierten halbleiterschaltung
JPS60134440A (ja) * 1983-12-23 1985-07-17 Hitachi Ltd 半導体集積回路装置
EP0154431B1 (en) * 1984-02-17 1989-08-16 AT&T Corp. Integrated circuit chip assembly
US4680617A (en) * 1984-05-23 1987-07-14 Ross Milton I Encapsulated electronic circuit device, and method and apparatus for making same
US4872825A (en) * 1984-05-23 1989-10-10 Ross Milton I Method and apparatus for making encapsulated electronic circuit devices
GB2253308B (en) * 1986-09-26 1993-01-20 Gen Electric Co Plc Semiconductor circuit arrangements
US5041943A (en) * 1989-11-06 1991-08-20 Allied-Signal Inc. Hermetically sealed printed circuit board
FR2666173A1 (fr) * 1990-08-21 1992-02-28 Thomson Csf Structure hybride d'interconnexion de circuits integres et procede de fabrication.
US5455202A (en) * 1993-01-19 1995-10-03 Hughes Aircraft Company Method of making a microelectric device using an alternate substrate
US6143396A (en) * 1997-05-01 2000-11-07 Texas Instruments Incorporated System and method for reinforcing a bond pad
US6085413A (en) * 1998-02-02 2000-07-11 Ford Motor Company Multilayer electrical interconnection device and method of making same
US6531945B1 (en) * 2000-03-10 2003-03-11 Micron Technology, Inc. Integrated circuit inductor with a magnetic core
US7214566B1 (en) 2000-06-16 2007-05-08 Micron Technology, Inc. Semiconductor device package and method
JP5173160B2 (ja) * 2006-07-14 2013-03-27 新光電気工業株式会社 多層配線基板及びその製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE631489A (en:Method) * 1962-04-27
US3264402A (en) * 1962-09-24 1966-08-02 North American Aviation Inc Multilayer printed-wiring boards
US3424629A (en) * 1965-12-13 1969-01-28 Ibm High capacity epitaxial apparatus and method
US3741880A (en) * 1969-10-25 1973-06-26 Nippon Electric Co Method of forming electrical connections in a semiconductor integrated circuit
US3726002A (en) * 1971-08-27 1973-04-10 Ibm Process for forming a multi-layer glass-metal module adaptable for integral mounting to a dissimilar refractory substrate
US3813773A (en) * 1972-09-05 1974-06-04 Bunker Ramo Method employing precision stamping for fabricating the wafers of a multiwafer electrical circuit structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5571091A (en) * 1978-11-24 1980-05-28 Hitachi Ltd Multilayer circuit board

Also Published As

Publication number Publication date
DE2510757C2 (de) 1983-08-25
GB1457866A (en) 1976-12-08
FR2267639A1 (en:Method) 1975-11-07
US3918148A (en) 1975-11-11
IT1033222B (it) 1979-07-10
JPS56945B2 (en:Method) 1981-01-10
CA1026469A (en) 1978-02-14
FR2267639B1 (en:Method) 1977-04-15
DE2510757A1 (de) 1975-10-23

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