JPS50137484A - - Google Patents

Info

Publication number
JPS50137484A
JPS50137484A JP50026134A JP2613475A JPS50137484A JP S50137484 A JPS50137484 A JP S50137484A JP 50026134 A JP50026134 A JP 50026134A JP 2613475 A JP2613475 A JP 2613475A JP S50137484 A JPS50137484 A JP S50137484A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP50026134A
Other languages
Japanese (ja)
Other versions
JPS56945B2 (US20030220297A1-20031127-C00009.png
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS50137484A publication Critical patent/JPS50137484A/ja
Publication of JPS56945B2 publication Critical patent/JPS56945B2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147Semiconductor insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894Materials of the insulating layers or coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2613475A 1974-04-15 1975-03-05 Expired JPS56945B2 (US20030220297A1-20031127-C00009.png)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US461078A US3918148A (en) 1974-04-15 1974-04-15 Integrated circuit chip carrier and method for forming the same

Publications (2)

Publication Number Publication Date
JPS50137484A true JPS50137484A (US20030220297A1-20031127-C00009.png) 1975-10-31
JPS56945B2 JPS56945B2 (US20030220297A1-20031127-C00009.png) 1981-01-10

Family

ID=23831131

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2613475A Expired JPS56945B2 (US20030220297A1-20031127-C00009.png) 1974-04-15 1975-03-05

Country Status (7)

Country Link
US (1) US3918148A (US20030220297A1-20031127-C00009.png)
JP (1) JPS56945B2 (US20030220297A1-20031127-C00009.png)
CA (1) CA1026469A (US20030220297A1-20031127-C00009.png)
DE (1) DE2510757C2 (US20030220297A1-20031127-C00009.png)
FR (1) FR2267639B1 (US20030220297A1-20031127-C00009.png)
GB (1) GB1457866A (US20030220297A1-20031127-C00009.png)
IT (1) IT1033222B (US20030220297A1-20031127-C00009.png)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5571091A (en) * 1978-11-24 1980-05-28 Hitachi Ltd Multilayer circuit board

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4045594A (en) * 1975-12-31 1977-08-30 Ibm Corporation Planar insulation of conductive patterns by chemical vapor deposition and sputtering
US4129904A (en) * 1977-11-14 1978-12-19 Pansini Andrew L Swimming pool cleaner
DE2755480A1 (de) * 1977-12-13 1979-06-21 Siemens Ag Verfahren zur herstellung einer integrierten halbleiterschaltung
JPS60134440A (ja) * 1983-12-23 1985-07-17 Hitachi Ltd 半導体集積回路装置
EP0172889A1 (en) * 1984-02-17 1986-03-05 AT&T Corp. Integrated circuit chip assembly
US4872825A (en) * 1984-05-23 1989-10-10 Ross Milton I Method and apparatus for making encapsulated electronic circuit devices
US4680617A (en) * 1984-05-23 1987-07-14 Ross Milton I Encapsulated electronic circuit device, and method and apparatus for making same
JPH0418893Y2 (US20030220297A1-20031127-C00009.png) * 1984-11-22 1992-04-28
JPH0341627Y2 (US20030220297A1-20031127-C00009.png) * 1985-09-09 1991-09-02
GB2253308B (en) * 1986-09-26 1993-01-20 Gen Electric Co Plc Semiconductor circuit arrangements
US5041943A (en) * 1989-11-06 1991-08-20 Allied-Signal Inc. Hermetically sealed printed circuit board
FR2666173A1 (fr) * 1990-08-21 1992-02-28 Thomson Csf Structure hybride d'interconnexion de circuits integres et procede de fabrication.
US5455202A (en) * 1993-01-19 1995-10-03 Hughes Aircraft Company Method of making a microelectric device using an alternate substrate
US6143396A (en) * 1997-05-01 2000-11-07 Texas Instruments Incorporated System and method for reinforcing a bond pad
US6085413A (en) * 1998-02-02 2000-07-11 Ford Motor Company Multilayer electrical interconnection device and method of making same
US6531945B1 (en) * 2000-03-10 2003-03-11 Micron Technology, Inc. Integrated circuit inductor with a magnetic core
US7214566B1 (en) 2000-06-16 2007-05-08 Micron Technology, Inc. Semiconductor device package and method
JP5173160B2 (ja) * 2006-07-14 2013-03-27 新光電気工業株式会社 多層配線基板及びその製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE631489A (US20030220297A1-20031127-C00009.png) * 1962-04-27
US3264402A (en) * 1962-09-24 1966-08-02 North American Aviation Inc Multilayer printed-wiring boards
US3424629A (en) * 1965-12-13 1969-01-28 Ibm High capacity epitaxial apparatus and method
US3741880A (en) * 1969-10-25 1973-06-26 Nippon Electric Co Method of forming electrical connections in a semiconductor integrated circuit
US3726002A (en) * 1971-08-27 1973-04-10 Ibm Process for forming a multi-layer glass-metal module adaptable for integral mounting to a dissimilar refractory substrate
US3813773A (en) * 1972-09-05 1974-06-04 Bunker Ramo Method employing precision stamping for fabricating the wafers of a multiwafer electrical circuit structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5571091A (en) * 1978-11-24 1980-05-28 Hitachi Ltd Multilayer circuit board

Also Published As

Publication number Publication date
DE2510757A1 (de) 1975-10-23
FR2267639B1 (US20030220297A1-20031127-C00009.png) 1977-04-15
IT1033222B (it) 1979-07-10
FR2267639A1 (US20030220297A1-20031127-C00009.png) 1975-11-07
GB1457866A (en) 1976-12-08
US3918148A (en) 1975-11-11
DE2510757C2 (de) 1983-08-25
CA1026469A (en) 1978-02-14
JPS56945B2 (US20030220297A1-20031127-C00009.png) 1981-01-10

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