EP0172889A1 - Integrated circuit chip assembly - Google Patents

Integrated circuit chip assembly

Info

Publication number
EP0172889A1
EP0172889A1 EP85901243A EP85901243A EP0172889A1 EP 0172889 A1 EP0172889 A1 EP 0172889A1 EP 85901243 A EP85901243 A EP 85901243A EP 85901243 A EP85901243 A EP 85901243A EP 0172889 A1 EP0172889 A1 EP 0172889A1
Authority
EP
European Patent Office
Prior art keywords
chip
wafer
substrate
conductive
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP85901243A
Other languages
German (de)
French (fr)
Inventor
Kwok Kwok Ng
Simon Min Sze
King Lien Tai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US06/581,336 external-priority patent/USH208H/en
Priority claimed from US06/581,259 external-priority patent/US4613891A/en
Priority claimed from US06/582,079 external-priority patent/US4670770A/en
Application filed by American Telephone and Telegraph Co Inc, AT&T Corp filed Critical American Telephone and Telegraph Co Inc
Publication of EP0172889A1 publication Critical patent/EP0172889A1/en
Pending legal-status Critical Current

Links

Classifications

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Definitions

  • the invention is concerned with integrated circuit technology.
  • Integrated circuit chips are assembled on a single-crystal carrier substrate and are electrically interconnected. Silicon is a preferred substrate material.
  • the positioning of a least one chip on the carrier substrate involves bringing at least one beveled sidewall of said at least one chip in juxtaposition with a sloping wall of a surface depression such as, e.g., a well, groove or opening in the carrier substrate.
  • Substrate and chip materials are crystallographically compatible, essentially single-crystal materials, and they are preferably essentially the same.
  • Sloping walls are made by crystallographically anisotropic etching which acts at differing rates in different crystallographic directions; angles other than 90 degrees are thus produced between etched surfaces and surfaces which are not exposed to an etchant.
  • alignment of chips involves match-up between two or four pairs of sloping faces, e.g., when chips are aligned in grooves or in four-sided wells.
  • Electrical connection can be effected by contacts on sloping walls; alternatively, connections can be made by one or several conductive paths analyzing the chip and the substrate.
  • an assembly is made to comprise at least one integrated circuit chip, active surface up, to the top side of a wafer.
  • Conductive pads are located in a central portion of the top surface of the mounted chip.
  • the top side of the wafer and all but peripheral portions of the attached chip(s) are then coated with an etch-resistance layer.
  • each chip is etched to form sloped edges between the active area of the device and the top side of the wafer.
  • conductive patterns are defined and formed on the top side of the wafer and on at least one of the sloped edges to connect the chip pads to pads on other chips or to conductive terminals disposed along the periphery of the wafer or to both.
  • the wafer-size assembly thus made is further processed (for example, encapsulated) in conventional ways and is then available as a monolithic component exhibiting advantageous performance and cost characteristics.
  • at least one chip of the type described is mounted on each side of a wafer. Additionally, connections may be established between chips mounted on the two sides of the wafer. In these ways, a particularly compact and dense wafer-size assembly is realized.
  • an assembly is made to comprise at least one chip which is mounted on the bottom side of a wafer. Conductive pads are located in a central portion of the top surface of the mounted chip. The wafer is then patterned to form a sloped-wall through-aperture in registry with the central portion, and thus with the conductive pads, of each mounted chip. Subsequently, by utilizing standard integrated-circuit fabrication techniques, a conductive pattern is formed overlying the top side of the wafer and on the sloped walls to connect the conductive pads of each chip to other chips or to conductive terminals on the top side of the wafer near the periphery thereof or to both.
  • the wafer-size assembly thus made is further processed (for example, encapsulated) in conventional ways and is then available as a monolithic component for inclusion in an electronic system.
  • FIG. 1 is a schematic, cross-sectional view of a portion of a circuit chip
  • FIG. 2 is a schematic, cross-sectional view of a portion of a wafer
  • FIG. 3 is a reduced-scale, schematic plan view of an integrated circuit assembly illustrating a ground metallization layer and a power metallization layer deposited side by side;
  • FIGS. 4, 5 and 6 are schematic cross-sectional views of an integrated circuit assembly at different stages of manufacture;
  • FIGS. 7 through 14 are schematic representations, not drawn to scale, of portions of a specific illustrative assembly;
  • FIGS. 15 through 24 are schematic representations, not drawn to scale, of portions of a specific illustrative assembly.
  • a substrate is a material body which has a surface which can serve as a support for material objects which may be insufficiently rigid in the absence of support or whose spatial arrangement depends on the presence of a support.
  • a substrate typically is relatively thin as compared with a planar extent.
  • a carrier substrate and a chip are mutually defined as substrates of relatively larger and smaller size, respectively, so that a plurality of chips can be attached to a carrier substrate.
  • An integrated circuit is a miniaturized electrical circuit which is supported by a substrate.
  • Preferential etching or crystallographically anisotropic etching is a chemical process which results in removal of surface matter at rates which differ depending on crystallographic direction in an essentially single- crystal material.
  • preferential etching is applicable to at least a portion of substrate material and at least a portion of chip material.
  • Such portions are here designated as body portions, and it is understood that substrate and chip may comprise portions other than such body portions such as, e.g., devices, circuits, and passive components.
  • FIG. 1 shows chip 1 , integrated circuit 2 with contact pads 3, insulating layer 4, metallic contact 15 which is preferably solder-wettable as, e.g., when consisting essentially of a Ti-Pd-Au or Cr-Cu-Au alloy, and soldei. metal 6. Beveled portions of chip 1 preferably have
  • FIG. 2 shows carrier substrate 7 which serves as electrical ground electrode and which is heavily doped at the surface, insulating oxide layer 8, power supply metallic conductor 9, x-signal metallic conductor 10, y- signal metallic conductor 11, metallic contact, stripe 12, polymeric insulating layers 13, cap layer 14 made, e.g., of silicon nitride, and solder metal layer 15.
  • the material of conductors 9, 10, and 11 is typically aluminum, and the material of metallic contact 12 is preferably solder wettable as, e.g., when consisting essentially of a Ti-Pd- Au or Cr-Cu-Au alloy.
  • Metallization 9, oxide layer 8, and substrate 7 form a metal-oxide-semiconductor decoupling capacitor. Electrical contact stripe 12 is shown connected to x-conductor 10; other contact stripes (not shown) may be connected to power supply 9 or y-conductor 13.
  • FIG. 3 shows wafer 7 serving as carrier substrate for chips 1, ground metallization layer 16, and power metallization layer 17.
  • Ground metallization layer 16 is electrically connected to heavily doped silicon substrate 7, and power layer 17 is deposited on a thin insulating layer, e.g., layer 8 as shown in FIG. 2.
  • the material of chip 1 and of carrier substrate 7 in FIGS. 2 and 3 is preferably the same, essentially single-crystal material which is amenable to preferential etching. Silicon is a primary example of such a material, potassium hydroxide being a convenient etchant in this case. (Etching of silicon for mask alignment is disclosed in U. S. patent No. 4,470,875.)
  • III-V semiconductor compounds such as, e.g.. gallium arsenide and gallium arsenide indium phosphide.
  • unpackaged silicon chips are mounted onto a silicon wafer which serves as carrier substrate.
  • Inter-chip connections are provided by two levels of signal nets with 5-15 ym wide conductive paths, power plane and a ground plane.
  • a photodefinable polymer such as, -e.g., a photosensitive polyimide
  • Methods to interconnect the chips and the wafer include techniques such as, e.g., wire bonding, tape- automatic bonding or "flip-chip" solder balls on solder pads.
  • self- aligned micro-stripes of solder metal on the chip can be used to connect to similar stripes on the wafer.
  • chips with precisely oriented beveled sides ((111) faces) by anisotropic wet etching of wafers having (100) surface planes, with the resulting beveled faces at an angle of 54-55 degrees. These can be inserted into matching beveled wells in silicon wafers, with an angle of 126-125 degrees between the bevel and the wafer plane.
  • Micro-solder stripes over the beveled oxides of the chips and wells can be defined in a CVD deposited, evaporated or sputtered resist, such as, e.g.,
  • Passive components such as resistors, capacitors and crystal oscillators can be incorporated into the silicon wafer by mounting on similarly beveled silicon plugs which are fitted into wells in the wafer.
  • optical fibers may terminate on a chip which may carry, e.g., an optical detector or a laser.
  • Beveled silicon planes can also be used for interconnection changes or customizations. Some wells may traverse the entire wafer thickness to allow interconnection, changes, or repairs on a circuit.
  • one wafer can replace a printed wiring board to form a subsystem or a system. This is advantageous because the high chip packing density allows short average interconnection lengths, short delay times, and lower capacitance and power consumption. Simultaneous switching noise induced by the inductance of the bonding wires is eliminated.
  • the self-aligned micro-solder stripes technique can provide an input/output of 400-800 I/O channels per chip without penalty in chip packing density.
  • the all- silicon system proposed alleviates the present reliability problems due to thermal mismatch between silicon, ceramics and printed circuit board materials, and the high thermal conductivity of silicon minimizes the danger of overheating of the components.
  • An example of an application is a "memory pack" consisting of a set of wafers stacked together, each wafer having an array of high density memory chips. Such a pack offers the speed of a random access memory and the mass storage capacity of a disc.
  • the entire system can be designed by existing computer aided design processes and computer aided testing can be implemented.
  • the drastic increase in I/O capability and chip packing density should provide new opportunities in system architecture. Since the penalty of "going off" the chip is removed, there is a lesser need to increase the number of circuits per chip. Thus, yield would be increased as the chip sizes are reduced. Furthermore, faster circuits with submicron design rules become manufacturable as the chip size shrinks.
  • FIGS. 4, 5, and 6 shown substrate 18, chip 19, insulating filler 20, and integrated circuit 21 with contact pads 22.
  • FIGS. 5 and 6 further show planarized insulating layer 23, electrical conductor 24, and contact pads 25.
  • FIG. 6 further shows planarized insulating layer 26 and electrical conductors 27.
  • Substrate 18 and chip i9 in FIG. 4-6 are preferably made of the same, essentially single-crystal material which is amenable to preferential etching, silicon being a primary example of such material.
  • Circuits are produced on chip-size portions of a substrate in customary fashion by deposition of layers and photolithographic patterning.
  • a layer of silicon nitride is deposited on front and back sides of the silicon wafer, a layer of a photoresist material is deposited on the silicon nitride on the back side, and a pattern corresponding to desired chips or openings is optically projected onto the photoresist layer.
  • the exposed photoresist is developed, and the developed pattern is copied into the silicon nitride layer, e.g., by reactive ion etching.
  • etching of the exposed portions of the silicon wafer is conveniently effected by the use of, e.g., potassium hydroxide as an etchant using a silicon nitride mask; etching may be partly into the wafer or through its entire thickness. Etch rate-is typically such
  • Etched chips are inserted into correspondingly etched grooves, wells, or openings in wafers; attachment by means of an insulating adhesive is convenient.
  • the surface of an inserted chip is preferably essentially co-planar with the' wafer surface.
  • a layer of a planarizing material such as, e.g., a polyimide or other photo-definable polymer, is deposited over the assembly, and holes corresponding to underlying circuit contact pads are etched by photolithographic patterning followed by reactive ion etching.
  • a metallization such as, e.g., an aluminum metallization is applied and patterned by reactive ion etching.
  • III-V semiconductor compounds such as, e.g., gallium arsenide and gallium arsenide indium phosphide.
  • advantages of the new insulating circuit assembly are the following:
  • FIG. 7 shows a wafer 28 that constitutes an integral part of an assembly made in accordance with the principles of the present invention.
  • the wafer 28 comprises a disc about 75-to-150 millimeters in diameter, with a thickness _t of approximately
  • the wafer 28 comprises a monocrystalline silicon wafer.
  • FIG. 8 shows in enlarged form a portion of the afore-described wafer 28. Additionally, FIG. 8 depicts a microminiature device, for example a silicon-integrated- circuit chip 29, adhered to the top of the wafer 28 by means of a bonding layer 31.
  • the layer 31 comprises an adhesive material such as a conventional polyimide material or a silicon dioxide layer.
  • the layer 31 is spun on the bottom surface of the chip 29 to a thickness of about 0..1-to- 10 micrometers before the chip 29 is placed in contact with the wafer 28.
  • one or more microminiature devices such as the chip 29 are adhered to the top side of the wafer 28 depicted in FIG. 17.
  • the chip 59 is, for example, about 0.25-to-0.75 millimeters thick and includes a -square top surface about six millimeters on a side. In some applications of applicant's invention, as many as 100 or even more devices of various designs and types are mounted on the top side of the wafer 28.
  • the devices mounted on the wafer 28 constitute chips cut from a wafer of monocrystalline silicon whose top and bottom surfaces were parallel (100) crystalline planes of the silicon structure. Accordingly, the top and bottom surfaces of each chip mounted on the wafer 28 also lie in (100) planes. The reason for selecting this particular orientation will be evident later below when a preferential etching step included in the fabrication sequence for the assembly is described.
  • multiple devices of various designs and types can be mounted on the bottom, as well as on the top, of the wafer 28. This is indicated in FIG. 8 wherein a device 30 is shown mounted on the bottom side of the wafer 28 by means of adhesive layer 32.
  • The- top of the chip 29 and the bottom .of the chip 30 shown in FIG. 8, respectively, constitute the so- called active sides thereof. Included on the active side of each chip are standard elements such as transistors (not shown), alignment marks (not shown), etc. Also included thereon are multiple relatively small-area conductive pads. Three such pads 33, 35, and 37 on chip 29, and three such pads 34, 36 and 38 on the chip 30, are schematically depicted in FIG. 8. Each pad has, for example, a square surface area only about 2.5-to-10 micrometers on a side.
  • the small-area pads included on the chips 29 and 30 can be located anywhere within the central region of the top surface thereof.
  • the pads are not limited to being located along the periphery of the central region.
  • some of the pads can be located in or towards the middle of the central region. This is advantageous because it reduces the total lead length required on a chip. As a result, the losses and delays experienced by signals that are propagated from the chip to associated circuitry are reduced.
  • the combination of reduced lead length and small-area pads leaves more of the active area available for other elements. Consequently, denser integrated designs are thereby made feasible.
  • FIGS. 9 through 13 emphasis hereinafter in connection with the description of FIGS. 9 through 13 will be directed to a portion of an assembly in which a single device (the chip 29) is mounted on the top side of the wafer 28. It is to be understood, however, that what is said about the processing of the chip 29 is also applicable to the processing of one or more additional devices mounted on the top side of the wafer 28 and to the processing of at least one additional device (such as the chip 30 of FIG. 8) mounted on the bottom side of the wafer 28.
  • sloped edges are formed on each of the devices mounted on the wafer 28. These sloped edges extend from the perimeter of the central region of each device toward the wafer side on which the device is mounted.
  • edges are formed in a particular well-defined etching step in which each chip mounted on the wafer 28 is inherently preferentially etched to reveal (111) planes that constitute the desired sloped edges.
  • FIG. 9 which shows a portion of the assembly taken along lines 43 in FIG. 10
  • each edge to be formed on the chip 29 will be inclined at an angle of 54-55 degrees with respect to the top surface of the chip 29.
  • a peripheral band of th'e top surface of the chip 29 will be removed by etching.
  • this band need not be continuous or closed.
  • one sloped edge per chip may be sufficient to satisfy the purposes of the invention.
  • the width w (FIG. 9) of this band is about 300-to-1000 micrometers.
  • the sloped-edge chip 29 whose outline is represented in FIG. 9 is formed by selectively masking the top surface of the chip 29 and then exposing the chip to a wet etchant such as a solution of potassium hydroxide.
  • a suitable etch-resistant mask for such an etchant is made, for example, of silicon nitride.
  • a layer 41 of silicon nitride patterned by conventional lithographic techniques is shown in FIG. 9.
  • an etch-resistant layer is also formed on the top surface of the wafer prior to defining the afore-specified sloped edges on the mounted chip(s).
  • Such an etch-resistant layer 42 made of silicon nitride is indicated in FIG. 9.
  • the layers 41 and 42 are each approximately 200 nm thick.
  • An advantageous etchant for forming the afore- described sloped edges on the chip 29 comprises approximately 250 grams of potassium hydroxide dissolved in 0.8 liters of water and 0.2 liters of propanol. Etching for about 3-to-10 hours with such a solution is effective to form the desired sloped edges. Subsequently, the silicon nitride masking layers 41 and 42 can be removed by, for example, etching the structure in hot phosphoric acid, as is well known in the art. At that point in the fabrication sequence, an assembly made in accordance with applicant's invention appears as depicted in the perspective view of FIG. 10.
  • the afore-specified slope of the edges of the chip 29 is not critical.
  • the sloped edges merely serve to facilitate the formation of conductive runners thereon.
  • the next step in applicant's inventive fabrication sequence is to form an insulating layer 44 over the entire top surface of the depicted assembly.
  • the layer 44 comprises a deposited layer of silicon dioxide about one micrometer thick.
  • Etching of the layer 44 is then carried out in a standard fashion utilizing conventional integrated-circuit patterning techniques to provide an opening in the layer 44 in registry with the conductive pad 35. In that way, the top surface of the conductive pad 35 is exposed, as indicated in FIG. 12.
  • a conductive*layer approximately one micrometer thick made, for example, of aluminum is deposited over the entire top surface of the assembly shown in FIG. 12.
  • the conductive layer is then patterned by conformal lithographic techniques (utilizing, for example, a germanium selenide resist) to form fine-line runners that extend from the chip pads, down one or more of the oxide-coated sloped edges of each chip and onto the main top surface of the assembly. In turn, these runners extend to conductive pads included on other mounted chips and/or to relatively large-area pads disposed around the periphery of the chip-wafer assembly.
  • a single conductive runner 45 is represented in FIG. 13.
  • the runner 45 contacts the pad 35 on the chip 29 and extends down one sloped edge of the chip 29 to overlie the silicon dioxide layer 44 that constitutes the main top surface of the depicted assembly.
  • additional alternating insulating and conductive layers may be deposited on top of the assembly represented in FIG. 13.
  • multi-level conductive patterns may be formed in the assembly.
  • planar conductors may be utilized, for example, as low- resistance low-inductance ground and/or power plane.
  • FIG. 14 is a top schematic view of a portion of an assembly made in accordance with the principles of the present invention.
  • a suitable standard encapsulant for the assembly may be advantageous but is not shown in FIG. 14.
  • four chips are indicated as being included in the depicted assembly.
  • Three chips 46, 47 and 48 are shown mounted overlying the top of the wafer 28 and one chip 49 is represented as being mounted on the bottom of the wafer 28.
  • one chip 49 is represented as being mounted on the bottom of the wafer 28.
  • each such chip typically has multiple (for example, 100 or more) leads extending therefrom. So as not to unduly clutter FIG.
  • each top-mounted chip is shown in this simplified depiction as including at least three but not more than five leads.
  • mounted chip 47 in FIG. -14 is represented as having five leads connected thereto.
  • Lead 50 of the chip 47 extends to adjacent chip 46.
  • Leads 51 and 52 interconnect the chips 47 and 48.
  • leads 53 and 54 respectively, extend between the chip 47 and peripheral conductive pads 55 and 56.
  • each of the interconnecting leads shown in FIG. 14 has a width d_ of approximately 1-to-10 micrometers.
  • each of the peripheral pads shown therein is about 1.25-by-1.25 millimeters.
  • the wafer 28 may be made of a material other than silicon. In selecting an alternative material, factors such as matching the thermal properties of the wafer to those of the associated chips are to be considered.
  • FIG. 15 shows a wafer 57 that constitutes an integral part of an assembly made in accordance with the. principles of the present invention.
  • the wafer 57 is made of monocrystalline silicon and is cut in the form of a disc about 75-to-150 millimeters in diameter, with a thickness t: of approximately 0.5 millimeters.
  • the top and bottom surfaces of the wafer 57 are parallel and lie in (100) crystalline planes of the silicon structure. The reason for selecting this particular orientation will be evident later below when a preferential etching step included in the fabrication sequence for the assembly is described.
  • an etch-resistant layer 58 shown in FIG. 16 is deposited on the entire bottom surface of the wafer 57.
  • the layer 58 comprises silicon nitride deposited to a thickness of approximately 100 nm.
  • FIG. 17 shows in enlarged form a portion of the afore-described wafer 10 and layer 58. Additionally, FIG. 17 depicts a microminiature device, for example, a silicon-integrated-circuit chip 59, adhered to the bottom of the layer 58 by means of a bonding layer 60.
  • the layer 60 comprises an adhesive material such as a conventional layer of silicon dioxide or a standard polyimide material.
  • the layer 60 is spun on the top surface of the chip 59 to a thickness of about 0.1-to-10 micrometers before the chip 59 is placed in contact with the layer 58.
  • one or more microminiature devices such as the chip 59 are adhered to the underside of the wafer 57 depicted in FIG. 3.
  • the chip 29 is, for example, about 0.25-to-0.75 millimeters thick and includes a square top surface about six millimeters on a side.
  • as many as 100 or even more devices of various designs and types are mounted on the underside of the wafer 59.
  • the top of the chip 59 shown in FIG. 17 constitutes the so-called active side thereof. Included on the active side of the chip are standard elements such as transistors (not shown), alignment marks (not shown), etc. Also included thereon are multiple relatively small-area conductive pads.
  • each pad has, for example, a square top surface area only about 2.5-to- 10 micrometers on a side.
  • the small-area pads included on the chip 59 can be located anywhere within the central region of the top surface. In other words, the pads are not limited to being located along the periphery of the central region. Thus, as indicated in FIG. 17, some of the pads can be located in or towards the middle of the central region. This is advantageous because it reduces the total lead length required on the chip. As a result, the losses and delays experienced by signals that are propagated from the chip to associated circuitry are reduced. Moreover, the combination of reduced lead length and small-area pads leaves more of the active, area available for other elements. Consequently, denser integrated circuit designs are thereby made feasible.
  • a well-defined through-aperture with four sloped walls is formed in the wafer in registry with the central region of each mounted device such as the chip 59.
  • the apertures are formed in a particular wet etching step in which the wafer 57 is inherently preferentially etched to reveal (111) planes that constitute the desired sloped walls.
  • each wall to be formed in the wafer 57 will be inclined at an angle of 35-36 degrees with respect to vertical walls through the wafer.
  • each sloped-wall through-aperture in the wafer 57 is designed -to overlie only the central region of an associated chip. In that way, a peripheral band of the chip that does not include conductive pads remains adhered to the underside of the wafer.
  • the width w (FIG. 18) of this band is, for example, about 10-to-250 micrometers. Of course, this band need not be continuous or closed or uniform in width.
  • the through-aperture whose outline is represented' in FIG. 18 is formed by selectively masking the top surface of the wafer 57 and then exposing the wafer to a wet etchant such as a solution of potassium hydroxide.
  • a wet etchant such as a solution of potassium hydroxide.
  • a suitable etch-resistant mask for such an etchant is made, for example, of silicon nitride.
  • a layer 66 of silicon nitride patterned by conventional lithographic techniques is shown in FIG. 18.
  • the layer 66 is approximately 200 n thick.
  • An advantageous etchant for forming the afore- described through-aperture in the wafer 57 comprises approximately 250 grams of potassium hydroxide dissolved in 0.8 liters of water and 0.2 liters of propanol. Etching for about 3-to-10 hours with such a solution is effective to form the desired sloped-wall aperture(s) in the herein- specified wafer 57. Subsequently, the top silicon nitride masking layer 66 and that portion of the bottom silicon nitride layer 58 directly underlying the smaller opening of the aperture can be removed by, for example, etching the structure in hot phosphoric acid, as is well known in the art .
  • FIGS. 19 and 20 an assembly made in accordance with applicant's invention appears as depicted in FIGS. 19 and 20.
  • the adhesive layer 60 is partially broken away to show some of the small-area conductive pads included on the chip 59. These include the previously specified pads 61 , -62 and 63.
  • the entire exposed portion of the adhesive layer 60 shown in FIG. 20 may be removed by utilizing a standard etchant therefor. Alternatively, it may be advantageous to leave the layer 60 substantially intact and to subsequently etch only small-area openings therethrough in registry with associated underlying conductive pads on the chip 59. In the further fabrication steps described below, this latter alternative approach will be specified.
  • the next step in applicant's inventive fabrication sequence is to form an insulating layer 67 over the entire top surface of the depicted assembly.
  • the layer 67 comprises a deposited layer of silicon dioxide about one micrometer thick.
  • Etching of the layer 67 is then carried out in a standard fashion utilizing conventional integrated-circuit patterning techniques to provide an opening in the layer 67 in registry with the conductive pad 62. Either in the same step in which the layer 67 is etched or in a subsequent etching step, a corresponding opening is also formed in the adhesive layer 60. In that way, the top surface of the conductive pad 62 is exposed, as indicated in FIG. 22. Next, a conductive layer approximately one micrometer thick made, for example, of aluminum is deposited over the entire top surface of the assembly shown in FIG. 22.
  • the conductive layer is then patterned by conformal lithographic techniques (utilizing, for example, a germanium selenide resist) to form fine-line runners that extend from the chip pads, up one or more of the sloping walls of the aperture associated with each chip and onto the main top surface of the assembly. In turn, these runners extend to other mounted chips and/or to relatively large-area pads disposed around the periphery of the chip- wafer assembly.
  • conformal lithographic techniques utilizing, for example, a germanium selenide resist
  • a single conductive runner 68 is represented in FIG. 23.
  • the runner 68 contacts the pad 62 on the chip 59 and extends up one sloped wall of the depicted aperture to overlie the silicon dioxide layer 67 that constitutes the main top surface of the depicted assembly.
  • additional alternating insulating and conductive layers may be deposited on top of the assembly represented in FIG. 23.
  • multi-level conductive patterns may be formed in the assembly.
  • planar conductors may be utilized, for example, as low- resistance low-inductance ground and/or power planes.
  • FIG. 24 is a top schematic view of a portion of an assembly made in accordance with the principles of the present invention. (A suitable standard encapsulant for the assembly may be advantageous but is not shown in
  • FIG. 24 For representative purposes only, twenty-four chips are indicated as being included in the depicted assembly. (In a 150-millimeter wafer, it is feasible to include as many as 500 mounted chips.) In practice, each such chip typically has multiple (for example, 100 or more) leads extending therefrom. So as not to unduly clutter FIG. 24, however, each mounted chip is shown in this simplified depiction as including at least one but not more than seven leads.
  • mounted chip 81 in FIG. 24 is represented as having seven leads connected thereto, Leads 82 and 83 of the chip 81 , respectively, extend to adjacent chips 69 and 70. Additionally, leads 71 through 75, respectively, extend between the chip 81 and peripheral conductive pads 76 through 80.
  • each of the interconnecting leads shown in FIG. 24 has a width d_ of approximately 1-to- 10 micrometers.
  • each of the peripheral pads shown therein is about 1.25-by-1.25 millimeters.

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Abstract

Assemblage de puce de circuit intégré dans lequel au moins une puce de circuit intégré (p.ex. 46-48, 49) est fixée sur un substrat (p.ex. 26) d'un matériau monocristallin, cette puce étant connectée électriquement à un réseau de circuit connecté de manière lithographique (p.ex. 50-54) sur le substrat. Les puces peuvent être placées sur la partie supérieure ou la partie inférieure du substrat ou les deux, et peuvent être placées dans des puits ou rainures dans le substrat, ou alors elles peuvent être placées au-dessus ou sous les puits ou rainures par fixation périphérique des puces. Les parois des puits ou rainures permettent l'alignement par correspondance des bords biseautés de certaines puces. Un réseau de circuit peut également être appliqué sur les parois de certains puits pour permettre des connexions aux puces fixées sous le substrat.Integrated circuit chip assembly in which at least one integrated circuit chip (eg 46-48, 49) is attached to a substrate (eg 26) of monocrystalline material, this chip being electrically connected to a network of circuits connected lithographically (eg 50-54) on the substrate. The chips can be placed on the top or bottom of the substrate or both, and can be placed in wells or grooves in the substrate, or they can be placed above or under the wells or grooves by peripheral fixing lice or fleas. The walls of the wells or grooves allow alignment by correspondence of the beveled edges of certain chips. A network of circuits can also be applied to the walls of certain wells to allow connections to the chips fixed under the substrate.

Description

INTEGRATED CIRCUIT CHIP ASSEMBLY
Technical Field
The invention is concerned with integrated circuit technology.
Background of the Invention
To satisfy an ever-increasing demand for computing and data processing power both with respect to processing speed and storage capacity, computer design has been evolving toward increasingly compact arrangements of components and assemblies. Attention has been directed to the number of so-called package levels (a package being defined as a group of structurally similar components or assemblies) as, e.g., by R. F. Bouner et al, "Advanced Printed-Circuit Board Design for High-Performance Computer Applications," IBM Journal of Research and Development, Vol. 26, No. 3, May 1982, pp. 297-305.
Attention has also been given to the way components and assemblies are interconnected; e.g., C. . Ho et al, "The Thin-Film Module as a High-Performance Semiconductor Package," IBM Journal of Research and Development, Vol. 26, No. 3, May 1982, pp. 287-296, discuss a multi-chip module of silicon chips attached to thin-film transmission lines. Among early proposals for the achievement of high device density in silicon technology is one by P. Kraynak et al, "Wafer-Chip Assembly for Large- Scale Integration," IEEE Transactions on Electron Devices, Vol. ED-15, No. 9, September 1968, pp. 660-663, where silicon chips are bonded "face down" on a silicon wafer. Summary of the Invention
Integrated circuit chips are assembled on a single-crystal carrier substrate and are electrically interconnected. Silicon is a preferred substrate material. In accordance with one aspect of the invention, the positioning of a least one chip on the carrier substrate involves bringing at least one beveled sidewall of said at least one chip in juxtaposition with a sloping wall of a surface depression such as, e.g., a well, groove or opening in the carrier substrate. Substrate and chip materials are crystallographically compatible, essentially single-crystal materials, and they are preferably essentially the same. Sloping walls are made by crystallographically anisotropic etching which acts at differing rates in different crystallographic directions; angles other than 90 degrees are thus produced between etched surfaces and surfaces which are not exposed to an etchant. Typically, alignment of chips involves match-up between two or four pairs of sloping faces, e.g., when chips are aligned in grooves or in four-sided wells.
Electrical connection can be effected by contacts on sloping walls; alternatively, connections can be made by one or several conductive paths analyzing the chip and the substrate.
In accordance with another aspect of the invention, an assembly is made to comprise at least one integrated circuit chip, active surface up, to the top side of a wafer. Conductive pads are located in a central portion of the top surface of the mounted chip. The top side of the wafer and all but peripheral portions of the attached chip(s) are then coated with an etch-resistance layer. Subsequently, each chip is etched to form sloped edges between the active area of the device and the top side of the wafer. By utilizing standard conformal integrated-circuit fabrication techniques, conductive patterns are defined and formed on the top side of the wafer and on at least one of the sloped edges to connect the chip pads to pads on other chips or to conductive terminals disposed along the periphery of the wafer or to both. The wafer-size assembly thus made is further processed (for example, encapsulated) in conventional ways and is then available as a monolithic component exhibiting advantageous performance and cost characteristics. In other embodiments of the invention, at least one chip of the type described is mounted on each side of a wafer. Additionally, connections may be established between chips mounted on the two sides of the wafer. In these ways, a particularly compact and dense wafer-size assembly is realized.
In accordance with still another aspect of the invention, an assembly is made to comprise at least one chip which is mounted on the bottom side of a wafer. Conductive pads are located in a central portion of the top surface of the mounted chip. The wafer is then patterned to form a sloped-wall through-aperture in registry with the central portion, and thus with the conductive pads, of each mounted chip. Subsequently, by utilizing standard integrated-circuit fabrication techniques, a conductive pattern is formed overlying the top side of the wafer and on the sloped walls to connect the conductive pads of each chip to other chips or to conductive terminals on the top side of the wafer near the periphery thereof or to both. The wafer-size assembly thus made is further processed (for example, encapsulated) in conventional ways and is then available as a monolithic component for inclusion in an electronic system. Brief Description of the Drawing
FIG. 1 is a schematic, cross-sectional view of a portion of a circuit chip;
FIG. 2 is a schematic, cross-sectional view of a portion of a wafer;
FIG. 3 is a reduced-scale, schematic plan view of an integrated circuit assembly illustrating a ground metallization layer and a power metallization layer deposited side by side;
FIGS. 4, 5 and 6 are schematic cross-sectional views of an integrated circuit assembly at different stages of manufacture; FIGS. 7 through 14 are schematic representations, not drawn to scale, of portions of a specific illustrative assembly; FIGS. 15 through 24 are schematic representations, not drawn to scale, of portions of a specific illustrative assembly. Detailed Description The following terms are prominently used in the description of the invention, and their meaning is as follows:
A substrate is a material body which has a surface which can serve as a support for material objects which may be insufficiently rigid in the absence of support or whose spatial arrangement depends on the presence of a support. A substrate typically is relatively thin as compared with a planar extent.
A carrier substrate and a chip are mutually defined as substrates of relatively larger and smaller size, respectively, so that a plurality of chips can be attached to a carrier substrate.
An integrated circuit is a miniaturized electrical circuit which is supported by a substrate. Preferential etching or crystallographically anisotropic etching is a chemical process which results in removal of surface matter at rates which differ depending on crystallographic direction in an essentially single- crystal material. In the interest of positioning a chip on a carrier substrate so as to facilitate electrical- interconnection of circuitry on the chip and on the substrate, preferential etching is applicable to at least a portion of substrate material and at least a portion of chip material. Such portions are here designated as body portions, and it is understood that substrate and chip may comprise portions other than such body portions such as, e.g., devices, circuits, and passive components.
FIG. 1 shows chip 1 , integrated circuit 2 with contact pads 3, insulating layer 4, metallic contact 15 which is preferably solder-wettable as, e.g., when consisting essentially of a Ti-Pd-Au or Cr-Cu-Au alloy, and soldei. metal 6. Beveled portions of chip 1 preferably have
-3 a depth which is at least 5.1 x 10 cm (2 mils).
FIG. 2 shows carrier substrate 7 which serves as electrical ground electrode and which is heavily doped at the surface, insulating oxide layer 8, power supply metallic conductor 9, x-signal metallic conductor 10, y- signal metallic conductor 11, metallic contact, stripe 12, polymeric insulating layers 13, cap layer 14 made, e.g., of silicon nitride, and solder metal layer 15. The material of conductors 9, 10, and 11 is typically aluminum, and the material of metallic contact 12 is preferably solder wettable as, e.g., when consisting essentially of a Ti-Pd- Au or Cr-Cu-Au alloy. Metallization 9, oxide layer 8, and substrate 7 form a metal-oxide-semiconductor decoupling capacitor. Electrical contact stripe 12 is shown connected to x-conductor 10; other contact stripes (not shown) may be connected to power supply 9 or y-conductor 13.
FIG. 3 shows wafer 7 serving as carrier substrate for chips 1, ground metallization layer 16, and power metallization layer 17. There is easy access to each chip from ground and power metallizations; more elaborate metallization patterns may be used as needed; e.g., narrow stripes of ground and power metallizations may extend at least partly around a chip to facilitate access to ground or power from any side of a chip.
Ground metallization layer 16 is electrically connected to heavily doped silicon substrate 7, and power layer 17 is deposited on a thin insulating layer, e.g., layer 8 as shown in FIG. 2. The material of chip 1 and of carrier substrate 7 in FIGS. 2 and 3 is preferably the same, essentially single-crystal material which is amenable to preferential etching. Silicon is a primary example of such a material, potassium hydroxide being a convenient etchant in this case. (Etching of silicon for mask alignment is disclosed in U. S. patent No. 4,470,875.) Among other suitable materials are III-V semiconductor compounds such as, e.g.. gallium arsenide and gallium arsenide indium phosphide. In a preferred embodiment, unpackaged silicon chips are mounted onto a silicon wafer which serves as carrier substrate. Inter-chip connections are provided by two levels of signal nets with 5-15 ym wide conductive paths, power plane and a ground plane. To insulate the planes, a photodefinable polymer (such as, -e.g., a photosensitive polyimide) having a low dielectric constant is used. Methods to interconnect the chips and the wafer include techniques such as, e.g., wire bonding, tape- automatic bonding or "flip-chip" solder balls on solder pads. Moreover, as illustrated by FIGS. 1 and 2, self- aligned micro-stripes of solder metal on the chip can be used to connect to similar stripes on the wafer.
In accordance with a preferred embodiment of the invention, in the case of silicon wafers and chips, it is possible to fabricate chips with precisely oriented beveled sides ((111) faces) by anisotropic wet etching of wafers having (100) surface planes, with the resulting beveled faces at an angle of 54-55 degrees. These can be inserted into matching beveled wells in silicon wafers, with an angle of 126-125 degrees between the bevel and the wafer plane. Micro-solder stripes over the beveled oxides of the chips and wells can be defined in a CVD deposited, evaporated or sputtered resist, such as, e.g.,
A92.0Se Ge0.15Se0.85 Which allowS nonplanar lithography. After the beveled chips have been dropped into the corresponding wells in the wafer, the micro-solder stripes on the chips and on the walls of the wells can be fused by reflowing the solder.
Passive components such as resistors, capacitors and crystal oscillators can be incorporated into the silicon wafer by mounting on similarly beveled silicon plugs which are fitted into wells in the wafer.
Furthermore, optical fibers may terminate on a chip which may carry, e.g., an optical detector or a laser.
Beveled silicon planes can also be used for interconnection changes or customizations. Some wells may traverse the entire wafer thickness to allow interconnection, changes, or repairs on a circuit.
When 10.2 cm. or 12.7 cm (4" or 5") silicon wafers are used, one wafer can replace a printed wiring board to form a subsystem or a system. This is advantageous because the high chip packing density allows short average interconnection lengths, short delay times, and lower capacitance and power consumption. Simultaneous switching noise induced by the inductance of the bonding wires is eliminated.
The self-aligned micro-solder stripes technique can provide an input/output of 400-800 I/O channels per chip without penalty in chip packing density. The all- silicon system proposed alleviates the present reliability problems due to thermal mismatch between silicon, ceramics and printed circuit board materials, and the high thermal conductivity of silicon minimizes the danger of overheating of the components.
An example of an application is a "memory pack" consisting of a set of wafers stacked together, each wafer having an array of high density memory chips. Such a pack offers the speed of a random access memory and the mass storage capacity of a disc.
The entire system can be designed by existing computer aided design processes and computer aided testing can be implemented. The drastic increase in I/O capability and chip packing density should provide new opportunities in system architecture. Since the penalty of "going off" the chip is removed, there is a lesser need to increase the number of circuits per chip. Thus, yield would be increased as the chip sizes are reduced. Furthermore, faster circuits with submicron design rules become manufacturable as the chip size shrinks.
FIGS. 4, 5, and 6 shown substrate 18, chip 19, insulating filler 20, and integrated circuit 21 with contact pads 22.
FIGS. 5 and 6 further show planarized insulating layer 23, electrical conductor 24, and contact pads 25. FIG. 6 further shows planarized insulating layer 26 and electrical conductors 27.
Substrate 18 and chip i9 in FIG. 4-6 are preferably made of the same, essentially single-crystal material which is amenable to preferential etching, silicon being a primary example of such material.
In particular, in the case of silicon, it is possible to fabricate chips with precisely oriented beveled sides (i.e., (111) faces) by anisotropic wet etching of (100) planes, with the resulting beveled faces at an angle of 54-55 degrees. Matching beveled wells in Si wafers can be made with an angle of 126-125 degrees between the bevel and a wafer plane. In the Figures the angle of 54-55 degrees is between the top surface of chip 19 and the beveled face of the chip, and the angle of 126-125 degrees is between the top surface of wafer 18 and the beveled face of the wafer) .
The following sequence of steps can be used to make an assembly in accordance with the invention: Circuits are produced on chip-size portions of a substrate in customary fashion by deposition of layers and photolithographic patterning. A layer of silicon nitride is deposited on front and back sides of the silicon wafer, a layer of a photoresist material is deposited on the silicon nitride on the back side, and a pattern corresponding to desired chips or openings is optically projected onto the photoresist layer. The exposed photoresist is developed, and the developed pattern is copied into the silicon nitride layer, e.g., by reactive ion etching. Preferential etching of the exposed portions of the silicon wafer is conveniently effected by the use of, e.g., potassium hydroxide as an etchant using a silicon nitride mask; etching may be partly into the wafer or through its entire thickness. Etch rate-is typically such
-3 that a 51 x 10 cm (20-mil) wafer is etched through in a time of from 7 to 8 hours.
Etched chips are inserted into correspondingly etched grooves, wells, or openings in wafers; attachment by means of an insulating adhesive is convenient. The surface of an inserted chip is preferably essentially co-planar with the' wafer surface.
A layer of a planarizing material such as, e.g., a polyimide or other photo-definable polymer, is deposited over the assembly, and holes corresponding to underlying circuit contact pads are etched by photolithographic patterning followed by reactive ion etching. A metallization such as, e.g., an aluminum metallization is applied and patterned by reactive ion etching.
Among suitable chip and wa'fer materials other than silicon are III-V semiconductor compounds such as, e.g., gallium arsenide and gallium arsenide indium phosphide. Among advantages of the new insulating circuit assembly are the following:
1. The new approach eliminates wire bonding operation.
2. The new approach eliminates a level of individual packaging namely, e.g. so-called DIP or chip carriers. 3. All chips of an electronic system or subsystem are packaged in one operation. 4. Circuit design is facilitated by contacts for metallization which can be located at any place inside the chip. 5. Multilevel metallization can be made by repeated deposition of insulating layers, metallization, and patterning. 6. The length of interconnections between chips can be minimized by suitable arrangement of chips on a substrate; this will reduce parasitic inductance and resistance. Parasitic capacitance decreases with increasing thickness of an insulating layer. FIG. 7 shows a wafer 28 that constitutes an integral part of an assembly made in accordance with the principles of the present invention. Advantageously, the wafer 28 comprises a disc about 75-to-150 millimeters in diameter, with a thickness _t of approximately
0.5 millimeters. Illustratively, the wafer 28 comprises a monocrystalline silicon wafer.
FIG. 8 shows in enlarged form a portion of the afore-described wafer 28. Additionally, FIG. 8 depicts a microminiature device, for example a silicon-integrated- circuit chip 29, adhered to the top of the wafer 28 by means of a bonding layer 31. By way of example, the layer 31 comprises an adhesive material such as a conventional polyimide material or a silicon dioxide layer. Illustratively, the layer 31 is spun on the bottom surface of the chip 29 to a thickness of about 0..1-to- 10 micrometers before the chip 29 is placed in contact with the wafer 28.
In accordance with the principles of the present invention, one or more microminiature devices such as the chip 29 are adhered to the top side of the wafer 28 depicted in FIG. 17. The chip 59 is, for example, about 0.25-to-0.75 millimeters thick and includes a -square top surface about six millimeters on a side. In some applications of applicant's invention, as many as 100 or even more devices of various designs and types are mounted on the top side of the wafer 28.
Advantageously, the devices mounted on the wafer 28 constitute chips cut from a wafer of monocrystalline silicon whose top and bottom surfaces were parallel (100) crystalline planes of the silicon structure. Accordingly, the top and bottom surfaces of each chip mounted on the wafer 28 also lie in (100) planes. The reason for selecting this particular orientation will be evident later below when a preferential etching step included in the fabrication sequence for the assembly is described. In accordance with the principles of applicant's invention, multiple devices of various designs and types can be mounted on the bottom, as well as on the top, of the wafer 28. This is indicated in FIG. 8 wherein a device 30 is shown mounted on the bottom side of the wafer 28 by means of adhesive layer 32.
The- top of the chip 29 and the bottom .of the chip 30 shown in FIG. 8, respectively, constitute the so- called active sides thereof. Included on the active side of each chip are standard elements such as transistors (not shown), alignment marks (not shown), etc. Also included thereon are multiple relatively small-area conductive pads. Three such pads 33, 35, and 37 on chip 29, and three such pads 34, 36 and 38 on the chip 30, are schematically depicted in FIG. 8. Each pad has, for example, a square surface area only about 2.5-to-10 micrometers on a side.
Importantly, the small-area pads included on the chips 29 and 30 (FIG. 8) can be located anywhere within the central region of the top surface thereof. In other words, the pads are not limited to being located along the periphery of the central region. Thus, as indicated in FIG. 8, some of the pads can be located in or towards the middle of the central region. This is advantageous because it reduces the total lead length required on a chip. As a result, the losses and delays experienced by signals that are propagated from the chip to associated circuitry are reduced. Moreover, the combination of reduced lead length and small-area pads leaves more of the active area available for other elements. Consequently, denser integrated designs are thereby made feasible.
So as not to unduly clutter the drawing, emphasis hereinafter in connection with the description of FIGS. 9 through 13 will be directed to a portion of an assembly in which a single device (the chip 29) is mounted on the top side of the wafer 28. It is to be understood, however, that what is said about the processing of the chip 29 is also applicable to the processing of one or more additional devices mounted on the top side of the wafer 28 and to the processing of at least one additional device (such as the chip 30 of FIG. 8) mounted on the bottom side of the wafer 28.
In accordance with a feature of applicant's invention, sloped edges are formed on each of the devices mounted on the wafer 28. These sloped edges extend from the perimeter of the central region of each device toward the wafer side on which the device is mounted.
Advantageously, these edges are formed in a particular well-defined etching step in which each chip mounted on the wafer 28 is inherently preferentially etched to reveal (111) planes that constitute the desired sloped edges. Thus, as indicated in FIG. 9 (which shows a portion of the assembly taken along lines 43 in FIG. 10) by reference lines 39 and 40, each edge to be formed on the chip 29 will be inclined at an angle of 54-55 degrees with respect to the top surface of the chip 29. In that way, a peripheral band of th'e top surface of the chip 29 will be removed by etching. (Of course, this band need not be continuous or closed. In fact, in some cases one sloped edge per chip may be sufficient to satisfy the purposes of the invention.) In one specific illustrative embodiment, the width w (FIG. 9) of this band is about 300-to-1000 micrometers.
Advantageously, the sloped-edge chip 29 whose outline is represented in FIG. 9 is formed by selectively masking the top surface of the chip 29 and then exposing the chip to a wet etchant such as a solution of potassium hydroxide. A suitable etch-resistant mask for such an etchant is made, for example, of silicon nitride. A layer 41 of silicon nitride patterned by conventional lithographic techniques is shown in FIG. 9. Additionally, if the wafer 28 of FIG. 9 is made of silicon, or of another material that is etched by a potassium hydroxide solution, an etch-resistant layer is also formed on the top surface of the wafer prior to defining the afore-specified sloped edges on the mounted chip(s). Such an etch-resistant layer 42 made of silicon nitride is indicated in FIG. 9. Illustratively, the layers 41 and 42 are each approximately 200 nm thick.
An advantageous etchant for forming the afore- described sloped edges on the chip 29 (FIG. 2) comprises approximately 250 grams of potassium hydroxide dissolved in 0.8 liters of water and 0.2 liters of propanol. Etching for about 3-to-10 hours with such a solution is effective to form the desired sloped edges. Subsequently, the silicon nitride masking layers 41 and 42 can be removed by, for example, etching the structure in hot phosphoric acid, as is well known in the art. At that point in the fabrication sequence, an assembly made in accordance with applicant's invention appears as depicted in the perspective view of FIG. 10.
The afore-specified slope of the edges of the chip 29 is not critical. The sloped edges merely serve to facilitate the formation of conductive runners thereon.
Preferential etching, as described above, is one convenient and advantageous way of achieving such sloped edges. But other techniques may be employed to form sloped edges on the chips. As indicated in FIG. 11, the next step in applicant's inventive fabrication sequence is to form an insulating layer 44 over the entire top surface of the depicted assembly. Illustratively, the layer 44 comprises a deposited layer of silicon dioxide about one micrometer thick.
So as to not unduly clutter the drawing, only one conductive pad 35 on the chip 29 is explicitly shown in FIG. 11. It should be understood, however, that in applicant's invention as many as 1000, or even more, small- area pads may be actually included on a typical chip.
Etching of the layer 44 is then carried out in a standard fashion utilizing conventional integrated-circuit patterning techniques to provide an opening in the layer 44 in registry with the conductive pad 35. In that way, the top surface of the conductive pad 35 is exposed, as indicated in FIG. 12. Next, a conductive*layer approximately one micrometer thick made, for example, of aluminum is deposited over the entire top surface of the assembly shown in FIG. 12. The conductive layer is then patterned by conformal lithographic techniques (utilizing, for example, a germanium selenide resist) to form fine-line runners that extend from the chip pads, down one or more of the oxide-coated sloped edges of each chip and onto the main top surface of the assembly. In turn, these runners extend to conductive pads included on other mounted chips and/or to relatively large-area pads disposed around the periphery of the chip-wafer assembly.
A single conductive runner 45 is represented in FIG. 13. The runner 45 contacts the pad 35 on the chip 29 and extends down one sloped edge of the chip 29 to overlie the silicon dioxide layer 44 that constitutes the main top surface of the depicted assembly.
In accordance with applicant's invention, additional alternating insulating and conductive layers (not shown) may be deposited on top of the assembly represented in FIG. 13. In that way, multi-level conductive patterns may be formed in the assembly. In some embodiments, it is advantageous to form one or more of the conductive levels as large-area planar conductors. Such planar conductors may be utilized, for example, as low- resistance low-inductance ground and/or power plane.
FIG. 14 is a top schematic view of a portion of an assembly made in accordance with the principles of the present invention. (A suitable standard encapsulant for the assembly may be advantageous but is not shown in FIG. 14.) For representative purposes only, four chips are indicated as being included in the depicted assembly. Three chips 46, 47 and 48 are shown mounted overlying the top of the wafer 28 and one chip 49 is represented as being mounted on the bottom of the wafer 28. (In a 150- millimeter wafer, it is feasible to include as many as 1000 mounted chips on the top and bottom of the wafer.) In practice, each such chip typically has multiple (for example, 100 or more) leads extending therefrom. So as not to unduly clutter FIG. 14, however, each top-mounted chip is shown in this simplified depiction as including at least three but not more than five leads. Thus, for example, mounted chip 47 in FIG. -14 is represented as having five leads connected thereto. Lead 50 of the chip 47 extends to adjacent chip 46. Leads 51 and 52 interconnect the chips 47 and 48. Additionally, leads 53 and 54, respectively, extend between the chip 47 and peripheral conductive pads 55 and 56. In one specific illustrative embodiment of applicant's invention, each of the interconnecting leads shown in FIG. 14 has a width d_ of approximately 1-to-10 micrometers. By way of example, each of the peripheral pads shown therein is about 1.25-by-1.25 millimeters. By a variety of conventional techniques, it is a relatively easy matter to establish electrical connections between such large-area peripheral pads and similar assemblies and/or other components included in an overall electronic system. It is to be understood that the above-described structures and processing techniques are only illustrative of the principles of the present invention. In accordance with these principles, numerous modifications and alternatives may be devised by those skilled in the art without departing from the spirit and scope of the invention. For example, in accordance with applicant's inventive principles, it is feasible to selectively interconnect device pads and/or peripheral pads on the top and bottom of the wafer by forming conductors that extend through via holes in the wafer. Moreover, it is feasible to fabricate composite chip-wafer assemblies that embody the concepts described herein. In such a composite assembly, sloped-wall chips and straight-wall chips would be mounted on both sides of a wafer that contains sloped- wall through apertures.
Also, it is to be understood that the wafer 28 may be made of a material other than silicon. In selecting an alternative material, factors such as matching the thermal properties of the wafer to those of the associated chips are to be considered.
FIG. 15 shows a wafer 57 that constitutes an integral part of an assembly made in accordance with the. principles of the present invention. Advantageously, the wafer 57 is made of monocrystalline silicon and is cut in the form of a disc about 75-to-150 millimeters in diameter, with a thickness t: of approximately 0.5 millimeters. In accordance with an advantageous feature of this invention, the top and bottom surfaces of the wafer 57 are parallel and lie in (100) crystalline planes of the silicon structure. The reason for selecting this particular orientation will be evident later below when a preferential etching step included in the fabrication sequence for the assembly is described.
Illustratively, an etch-resistant layer 58 shown in FIG. 16 is deposited on the entire bottom surface of the wafer 57. By way bf example, the layer 58 comprises silicon nitride deposited to a thickness of approximately 100 nm.
FIG. 17 shows in enlarged form a portion of the afore-described wafer 10 and layer 58. Additionally, FIG. 17 depicts a microminiature device, for example, a silicon-integrated-circuit chip 59, adhered to the bottom of the layer 58 by means of a bonding layer 60. By way of example, the layer 60 comprises an adhesive material such as a conventional layer of silicon dioxide or a standard polyimide material. Illustratively, the layer 60 is spun on the top surface of the chip 59 to a thickness of about 0.1-to-10 micrometers before the chip 59 is placed in contact with the layer 58. In accordance with the principles of the present invention, one or more microminiature devices such as the chip 59 are adhered to the underside of the wafer 57 depicted in FIG. 3. The chip 29 is, for example, about 0.25-to-0.75 millimeters thick and includes a square top surface about six millimeters on a side. In some applications of applicant's invention, as many as 100 or even more devices of various designs and types are mounted on the underside of the wafer 59. The top of the chip 59 shown in FIG. 17 constitutes the so-called active side thereof. Included on the active side of the chip are standard elements such as transistors (not shown), alignment marks (not shown), etc. Also included thereon are multiple relatively small-area conductive pads. Three such pads 61, 62 and 63 located in a central region of the active side of the chip are schematically depicted in FIG. 17. Each pad has, for example, a square top surface area only about 2.5-to- 10 micrometers on a side. Importantly, the small-area pads included on the chip 59 can be located anywhere within the central region of the top surface. In other words, the pads are not limited to being located along the periphery of the central region. Thus, as indicated in FIG. 17, some of the pads can be located in or towards the middle of the central region. This is advantageous because it reduces the total lead length required on the chip. As a result, the losses and delays experienced by signals that are propagated from the chip to associated circuitry are reduced. Moreover, the combination of reduced lead length and small-area pads leaves more of the active, area available for other elements. Consequently, denser integrated circuit designs are thereby made feasible.
In accordance with a feature of applicant's invention, a well-defined through-aperture with four sloped walls is formed in the wafer in registry with the central region of each mounted device such as the chip 59. Advantageously, the apertures are formed in a particular wet etching step in which the wafer 57 is inherently preferentially etched to reveal (111) planes that constitute the desired sloped walls. Thus, as indicated in FIG. 18 by reference lines 64 and 65, each wall to be formed in the wafer 57 will be inclined at an angle of 35-36 degrees with respect to vertical walls through the wafer.
The bottom or smaller opening of each sloped-wall through-aperture in the wafer 57 is designed -to overlie only the central region of an associated chip. In that way, a peripheral band of the chip that does not include conductive pads remains adhered to the underside of the wafer. In specific embodiments, the width w (FIG. 18) of this band is, for example, about 10-to-250 micrometers. Of course, this band need not be continuous or closed or uniform in width.
Advantageously, the through-aperture whose outline is represented' in FIG. 18 is formed by selectively masking the top surface of the wafer 57 and then exposing the wafer to a wet etchant such as a solution of potassium hydroxide. A suitable etch-resistant mask for such an etchant is made, for example, of silicon nitride. A layer 66 of silicon nitride patterned by conventional lithographic techniques is shown in FIG. 18.
Illustratively, the layer 66 is approximately 200 n thick.
An advantageous etchant for forming the afore- described through-aperture in the wafer 57 comprises approximately 250 grams of potassium hydroxide dissolved in 0.8 liters of water and 0.2 liters of propanol. Etching for about 3-to-10 hours with such a solution is effective to form the desired sloped-wall aperture(s) in the herein- specified wafer 57. Subsequently, the top silicon nitride masking layer 66 and that portion of the bottom silicon nitride layer 58 directly underlying the smaller opening of the aperture can be removed by, for example, etching the structure in hot phosphoric acid, as is well known in the art .
At that point in the fabrication sequence, an assembly made in accordance with applicant's invention appears as depicted in FIGS. 19 and 20. In the perspective ' view of FIG. 20, the adhesive layer 60 is partially broken away to show some of the small-area conductive pads included on the chip 59. These include the previously specified pads 61 , -62 and 63.
The entire exposed portion of the adhesive layer 60 shown in FIG. 20 may be removed by utilizing a standard etchant therefor. Alternatively, it may be advantageous to leave the layer 60 substantially intact and to subsequently etch only small-area openings therethrough in registry with associated underlying conductive pads on the chip 59. In the further fabrication steps described below, this latter alternative approach will be specified.
As indicated in FIG. 21 , the next step in applicant's inventive fabrication sequence is to form an insulating layer 67 over the entire top surface of the depicted assembly. Illustratively, the layer 67 comprises a deposited layer of silicon dioxide about one micrometer thick.
So as to not unduly clutter the drawing, only one conductive pad 62 on the chip 59 is explicitly shown in FIG. 21. it should be understood, however, that in accordance with applicant's invention as many as 1000, or even more, small-area pads may be actually included on some chips.
Etching of the layer 67 is then carried out in a standard fashion utilizing conventional integrated-circuit patterning techniques to provide an opening in the layer 67 in registry with the conductive pad 62. Either in the same step in which the layer 67 is etched or in a subsequent etching step, a corresponding opening is also formed in the adhesive layer 60. In that way, the top surface of the conductive pad 62 is exposed, as indicated in FIG. 22. Next, a conductive layer approximately one micrometer thick made, for example, of aluminum is deposited over the entire top surface of the assembly shown in FIG. 22. The conductive layer is then patterned by conformal lithographic techniques (utilizing, for example, a germanium selenide resist) to form fine-line runners that extend from the chip pads, up one or more of the sloping walls of the aperture associated with each chip and onto the main top surface of the assembly. In turn, these runners extend to other mounted chips and/or to relatively large-area pads disposed around the periphery of the chip- wafer assembly.
A single conductive runner 68 is represented in FIG. 23. The runner 68 contacts the pad 62 on the chip 59 and extends up one sloped wall of the depicted aperture to overlie the silicon dioxide layer 67 that constitutes the main top surface of the depicted assembly.
In accordance with applicant's invention, additional alternating insulating and conductive layers (not shown) may be deposited on top of the assembly represented in FIG. 23. In that way, multi-level conductive patterns may be formed in the assembly. In some embodiments, it is advantageous to form one or more of the conductive levels as large-area planar conductors. Such planar conductors may be utilized, for example, as low- resistance low-inductance ground and/or power planes.
FIG. 24 is a top schematic view of a portion of an assembly made in accordance with the principles of the present invention. (A suitable standard encapsulant for the assembly may be advantageous but is not shown in
FIG. 24.) For representative purposes only, twenty-four chips are indicated as being included in the depicted assembly. (In a 150-millimeter wafer, it is feasible to include as many as 500 mounted chips.) In practice, each such chip typically has multiple (for example, 100 or more) leads extending therefrom. So as not to unduly clutter FIG. 24, however, each mounted chip is shown in this simplified depiction as including at least one but not more than seven leads.
Thus, for example, mounted chip 81 in FIG. 24 is represented as having seven leads connected thereto, Leads 82 and 83 of the chip 81 , respectively, extend to adjacent chips 69 and 70. Additionally, leads 71 through 75, respectively, extend between the chip 81 and peripheral conductive pads 76 through 80.
In one specific illustrative embodiment of applicant's invention, each of the interconnecting leads shown in FIG. 24 has a width d_ of approximately 1-to- 10 micrometers. By way of example, each of the peripheral pads shown therein is about 1.25-by-1.25 millimeters. By a variety of conventional techniques, it is a relatively easy matter to establish electrical connections between such large-area peripheral pads and similar assemblies and/or other components included in an overall electronic system. It is to be understood that the above-described structures and processing techniques are only illustrative of the principles of the present invention. In accordance with these principles, numerous modifications and alternatives may be devised by those skilled in the art without departing from the spirit and scope of the invention. For example, it is feasible to fabricate composite chip-wafer assemblies that embody the concepts described herein. In such a composite assembly, sloped- wall chips and straight-wall chips would be mounted on both sides of a wafer that contains sloped-wall through apertures. Also, it is to be understood that the wafer 57 may in some cases of practical importance be made of a material other than silicon. In selecting an alternative material, factors such as matching the thermal properties of the wafer to those of the associated chips and the amenability of the wafer to being preferentially etched are to be considered. But, of course, it is to be realized that techniques other than etching may be employed to form the afore-specified 'through-apertures. The slope of the walls of these apertures is not critical. The sloped walls merely serve to facilitate the formation of runners thereon. Preferential etching, as described above, is one convenient and advantageous way of achieving such sloped- wall apertures.

Claims

Claims
1. Device comprising a substrate and at least one integrated circuit chip attached to said substrate,
CHARACTERIZED IN THAT said substrate consists essentially of a single- crystal material, and said at least one circuit chip being electricall connected to lithographically defined electrical circuitry on said substrate.
2. .Device according to claim 1,
CHARACTERIZED IN THAT the material of at least a body portion of said substrate and the material of at least a body portion of said at least one chip have the same crystallographic structure.
3. Device according to claim 2, CHARACTERIZED IN THAT the material of said body portion of said substrate is essentially the same as the material of said body portion of said at least one chip.
4. Device according to claim 1 or 2 or 3, CHARACTERIZED IN THAT said material is a semiconductor material.
5. Device according to claim 1 or 2 or 3 or 4, CHARACTERIZED IN THAT said material is essentially silicon.
6. Device according to any one of preceding claims 1-5,
CHARACTERIZED IN THAT said single-crystal material of the substrate is silicon.
7. Device according to any one of preceding claims 1-6,
CHARACTERIZED IN THAT said electrical circuitry comprises a ground conductor and a power conductor and a decoupling capacitor is between said ground conductor and said power conductor.
8. Device according to claim 7, CHARACTERIZED IN THAT said decoupling capacitor is a metal-oxide- semiconductor capacitor.
9. Device according to claim 8,
CHARACTERIZED IN THAT said capacitor consists of said substrate, an oxide layer on said substrate, and a metallic layer on said oxide layer.
10. Device according to any one of preceding claims 1-9,
CHARACTERIZED IN THAT said substrate has at least one surface depression (hereinafter referred to as "well") which has at least one sloping wall resulting from crystallographically anisotropic etching, said at least one chip has at least one beveled edge resulting from crystallographically anisotropic etching, and said at least one beveled edge and said at least one slope are in juxtaposition, whereby said at least one chip is positioned on said substrate.
11. Device according to claim 10, CHARACTERIZED IN THAT said at least one chip has a circuit-carrying side which faces into said at least one well in said wafer.
12. Device according to claim 11, CHARACTERIZED IN THAT contact is made to said circuit by at least one stripe conductor on a sidewall of said well.
13. Device according to any one of preceding claims 10-12,
CHARACTERIZED BY comprising a plurality of chips, said chips being electrically interconnected by electrical conductors on said wafer.
14. Device according to claim 13, CHARACTERIZED IN THAT said electrical conductors are separated by a photodefinable polymer material.
15. Device according to any one of preceding claims 10-14,
CHARACTERIZED BY comprising at least one passive component which i mounted on said at least on chip.
16. Device according to any one of preceding claims 10-15,
CHARACTERIZED IN THAT at least one optical fiber terminates on said at least one chip.
17. Device according to any one of preceding claims 1-9,
CHARACTERIZED BY comprising a wafer and at least one circuit- carrying chip, the material of said wafer being essentially in single-crystal form, the material of said at least one chip being in essentially the same single-crystal form as the material of said wafer, said at least one -chip having a first surface and at least one first sidewall forming a first angle with said first surface, said angle being less than 90 degrees as resulting from etching of the material of said at least one chip, said wafer having a second surface and at least one second sidewall forming a second angle with said second surface, said second angle being essentially supplementary to -said first angle as resulting from etching of the material of said wafer, said at least one chip being in alignment with respect to said wafer as a result of matching between said at least one first sidewall and said at least one second sidewall, said at least one chip carrying an integrated circuit and a planarizing layer overlying said circuit and at least a portion of said wafer, and electrical connection to said circuit being made by metallization which overlies said planarizing layer.
18. Device according to claim 17, CHARACTERIZED IN THAT the material of said planarizing layer is a photo-definable material.
19. Device according to claim 17, CHARACTERIZED BY comprising two or more planarizing layers and metallizations.
20. Device according to any one of pre'ceding claims 1-9,
CHARACTERIZED IN THAT said substrate is a wafer having top and bottom surfaces, said wafer having conductive terminal portions along the periphery thereof overlying said top surface, at least one chip mounted at least on the top surface of said wafer includes conductive elements in a central portion of its top surface, each mounted chip having at least one sloped edge extending from said central portion toward the top surface of said wafer, and a conductive pattern connects the elements of a mounted device to said terminal portions or to elements included on another mounted chip or to both, said pattern being disposed on the sloped edσe(s) of each mounted chip and overlying the top surface of said wafer.
21. Device according to claim 20, CHARACTERIZED IN THAT said wafer includes additional conductive terminal portions along the periphery thereof overlying said bottom surface. at least one chip mounted on the bottom surface of said wafer, said at least one chip including conductive elements in a central portion of its unmounted surface, each bottom-surface-mounted chip having at least one slope edge extending from its central portion toward the bottom surface of said wafer, and a conductive pattern connecting the conductive elements of a bottom-surface-mounted chip to said additional terminal portions or to elements included on another bottom-surface-mounted chip or to both, said pattern being disposed on the sloped edge(s) of each bottom-surface-mounted chip and overlying the planar botto surface of said wafer.
22. Device according to claim 20 or 21, CHARACTERIZED IT THAT said at least one chip comprises a monocrystalline silicon chip the top and bottom surfaces o which lie in (100) crystalline planes.
23. Device according to claim 22, CHARACTERIZED IN THAT said at least one sloped edge lies in a (111) crystalline plane of said silicon chip.
24. Device according to any one of preceding claims 20-23, CHARACTERIZED IN THAT the instrumentality mounting each chip on said wafer comprises an adhesive layer interposed between each device and said wafer.
25. Device according to any one preceding claims 1-9,
CHARACTERIZED BY substrate having a relatively large surface and provided with terminal pads, a plurality of semiconductor chips each having front and back surfaces with its back surface contacting the surface of said substrate and its front surface including a plurality of conductive pads which provide external connections to circuit elements within the chip, each chip having at least one sloping edge extending from its front surface to said substrate, and conductive paths extending from the conductor pads along the sloping edges of the chips and the surface of the substrate for interconnecting chips to one another and to the terminal pads on the substrate.
26. Device according to claim 25,
CHARACTERIZED IN THAT said substrate is a wafer, said at least one chip includes conductive pads in a central region of one surface of said chip mounted on said wafer, and at least one sloped wall extends from the central region of said at least one mounted chip to one surface of said wafer, a conductive pattern, including peripherally disposed elements, on the one surface of said wafer and on said at least one sloped wall connects said pads to other device pads or to said elements or to both.
27. Device according to any one of preceding claims 1-9,
CHARACTERIZED BY a wafer having planar top and bottom surfaces, said wafer having conductive terminal portions along the periphery thereof overlying said top surface, at least one chip mounted on the bottom surface of said wafer, said chip including in a central portion of its top surface conductive pads facing said wafer, a sloped-wall aperture formed through said wafer in registry with the central portion of each mounted chip, and a conductive pattern connecting the pads of a mounted chip to said terminal portions, said pattern being disposed on at least one of the sloped walls associated with a mounted chip and overlying the planar top surface of said wafer.
28. Device according to claim 27, CHARACTERIZED IN THAT the instrumentality mounting each chip on the bottom surface of said wafer comprises an adhesive layer disposed around at least a peripheral portion of the top surface of each chip.
29. Device according to any one of preceding claims 1-9, .
CHARACTERIZED BY a plurality of semiconductive chips, each having a plurality of conductive pads on a top surface for providing electrical connections to circuit elements in th chip, a cap member to one surface of which is bonded separately at least a portion of the top surface of each of the plurality of chips, the cap member including sloped- wall apertures to permit access to the conductive pads, and conductive paths overlying an opposite surface of the cap member and extending along the sloped side walls of the apertures for contacting the conductive pads and interconnecting the chips.
EP85901243A 1984-02-17 1985-02-15 Integrated circuit chip assembly Pending EP0172889A1 (en)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US58126084A 1984-02-17 1984-02-17
US06/581,336 USH208H (en) 1984-02-17 1984-02-17 Packaging microminiature devices
US06/581,259 US4613891A (en) 1984-02-17 1984-02-17 Packaging microminiature devices
US581260 1984-02-17
US581336 1984-02-17
US581259 1984-02-17
US06/582,079 US4670770A (en) 1984-02-21 1984-02-21 Integrated circuit chip-and-substrate assembly
US582079 1984-02-21

Publications (1)

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EP0172889A1 true EP0172889A1 (en) 1986-03-05

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EP85301014A Expired EP0154431B1 (en) 1984-02-17 1985-02-15 Integrated circuit chip assembly
EP85901243A Pending EP0172889A1 (en) 1984-02-17 1985-02-15 Integrated circuit chip assembly

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EP (2) EP0154431B1 (en)
DE (1) DE3572421D1 (en)
ES (1) ES8700500A1 (en)
WO (1) WO1985003806A1 (en)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6281745A (en) * 1985-10-05 1987-04-15 Fujitsu Ltd Lsi semiconductor device in wafer scale and manufacture thereof
DE3718684A1 (en) * 1987-06-04 1988-12-22 Licentia Gmbh SEMICONDUCTOR BODY
FR2618255A1 (en) * 1987-07-14 1989-01-20 Gen Electric PACKAGING BLOCK FOR MOUNTING AND INTERCONNECTING SEMICONDUCTOR CHIPS.
FR2634322A1 (en) * 1988-07-13 1990-01-19 Thomson Csf Hybrid active semiconductor module obtained by physical reconfiguration of insets interconnected by thin films, and corresponding method of manufacture
WO1990001215A1 (en) * 1988-07-22 1990-02-08 Nippondenso Co., Ltd. Semiconductor device
US5008213A (en) * 1988-12-09 1991-04-16 The United States Of America As Represented By The Secretary Of The Air Force Hybrid wafer scale microcircuit integration
US4989063A (en) * 1988-12-09 1991-01-29 The United States Of America As Represented By The Secretary Of The Air Force Hybrid wafer scale microcircuit integration
EP0393220B1 (en) * 1989-04-20 1994-07-13 International Business Machines Corporation Integrated circuit package
US5032896A (en) * 1989-08-31 1991-07-16 Hughes Aircraft Company 3-D integrated circuit assembly employing discrete chips
EP0419767B1 (en) * 1989-09-29 1993-11-24 Siemens Aktiengesellschaft Method for manufacturing a Silicon body
US6864570B2 (en) 1993-12-17 2005-03-08 The Regents Of The University Of California Method and apparatus for fabricating self-assembling microstructures
JP3701542B2 (en) * 2000-05-10 2005-09-28 シャープ株式会社 Semiconductor device and manufacturing method thereof
FR2917234B1 (en) * 2007-06-07 2009-11-06 Commissariat Energie Atomique MULTI-COMPONENT DEVICE INTEGRATED IN A SEMICONDUCTOR MATRIX
FR2934082B1 (en) 2008-07-21 2011-05-27 Commissariat Energie Atomique MULTI-COMPONENT DEVICE INTEGRATED IN A MATRIX
FR2947948B1 (en) 2009-07-09 2012-03-09 Commissariat Energie Atomique HANDLE PLATE HAVING VISUALIZATION WINDOWS

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3918148A (en) * 1974-04-15 1975-11-11 Ibm Integrated circuit chip carrier and method for forming the same
GB2047466B (en) * 1979-02-24 1983-03-30 Int Computers Ltd Multi-level connection networks

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8503806A1 *

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WO1985003806A1 (en) 1985-08-29
ES540478A0 (en) 1986-11-16
DE3572421D1 (en) 1989-09-21
EP0154431B1 (en) 1989-08-16
EP0154431A1 (en) 1985-09-11
ES8700500A1 (en) 1986-11-16

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