JPS50137449A - - Google Patents

Info

Publication number
JPS50137449A
JPS50137449A JP50006008A JP600875A JPS50137449A JP S50137449 A JPS50137449 A JP S50137449A JP 50006008 A JP50006008 A JP 50006008A JP 600875 A JP600875 A JP 600875A JP S50137449 A JPS50137449 A JP S50137449A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP50006008A
Other languages
Japanese (ja)
Other versions
JPS5516334B2 (en:Method
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS50137449A publication Critical patent/JPS50137449A/ja
Publication of JPS5516334B2 publication Critical patent/JPS5516334B2/ja
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646Configuration or reconfiguration
    • G06F12/0669Configuration or reconfiguration with decentralised address assignment
    • G06F12/0676Configuration or reconfiguration with decentralised address assignment the address being position dependent

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
  • Executing Machine-Instructions (AREA)
  • Feedback Control In General (AREA)
JP600875A 1974-04-17 1975-01-14 Expired JPS5516334B2 (en:Method)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US461576A US3872452A (en) 1974-04-17 1974-04-17 Floating addressing system and method

Publications (2)

Publication Number Publication Date
JPS50137449A true JPS50137449A (en:Method) 1975-10-31
JPS5516334B2 JPS5516334B2 (en:Method) 1980-05-01

Family

ID=23833136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP600875A Expired JPS5516334B2 (en:Method) 1974-04-17 1975-01-14

Country Status (12)

Country Link
US (1) US3872452A (en:Method)
JP (1) JPS5516334B2 (en:Method)
AR (1) AR214387A1 (en:Method)
BR (1) BR7502331A (en:Method)
CA (1) CA1019456A (en:Method)
CH (1) CH578765A5 (en:Method)
ES (1) ES433528A1 (en:Method)
FR (1) FR2268305B1 (en:Method)
GB (1) GB1459889A (en:Method)
IT (1) IT1027866B (en:Method)
NL (1) NL7503807A (en:Method)
SE (1) SE408501B (en:Method)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5441139U (en:Method) * 1977-08-26 1979-03-19

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4055802A (en) * 1976-08-12 1977-10-25 Bell Telephone Laboratories, Incorporated Electrical identification of multiply configurable circuit array
US4315321A (en) * 1978-06-16 1982-02-09 The Kardios Systems Corporation Method and apparatus for enhancing the capabilities of a computing system
US4296467A (en) * 1978-07-03 1981-10-20 Honeywell Information Systems Inc. Rotating chip selection technique and apparatus
JPS55110355A (en) * 1979-02-16 1980-08-25 Toshiba Corp Memory board and selection system for it
US4451903A (en) * 1981-09-14 1984-05-29 Seeq Technology, Inc. Method and device for encoding product and programming information in semiconductors
US4419747A (en) * 1981-09-14 1983-12-06 Seeq Technology, Inc. Method and device for providing process and test information in semiconductors
FR2520896B1 (fr) * 1982-02-01 1987-06-05 Merlin Gerin Dispositif d'adressage des cartes d'un automate programmable pour la securite des echanges sur le bus
GB2153567A (en) * 1984-01-12 1985-08-21 Sinclair Res Ltd Arrangements for enabling the connection of one or more additional devices to a computer
US4980856A (en) * 1986-10-20 1990-12-25 Brother Kogyo Kabushiki Kaisha IC memory cartridge and a method for providing external IC memory cartridges to an electronic device extending end-to-end
US4980850A (en) * 1987-05-14 1990-12-25 Digital Equipment Corporation Automatic sizing memory system with multiplexed configuration signals at memory modules
US4951248A (en) * 1988-03-04 1990-08-21 Sun Microsystems, Inc. Self configuring memory system
GB2226667B (en) * 1988-12-30 1993-03-24 Intel Corp Self-identification of memory
US4984213A (en) * 1989-02-21 1991-01-08 Compaq Computer Corporation Memory block address determination circuit
JPH02245840A (ja) * 1989-03-20 1990-10-01 Fujitsu Ltd 記憶装置
US5261073A (en) 1989-05-05 1993-11-09 Wang Laboratories, Inc. Method and apparatus for providing memory system status signals
US5012408A (en) * 1990-03-15 1991-04-30 Digital Equipment Corporation Memory array addressing system for computer systems with multiple memory arrays
US5295255A (en) * 1991-02-22 1994-03-15 Electronic Professional Services, Inc. Method and apparatus for programming a solid state processor with overleaved array memory modules
US5860028A (en) * 1996-02-01 1999-01-12 Paragon Electric Company, Inc. I/O bus expansion system wherein processor checks plurality of possible address until a response from the peripheral selected by address decoder using user input
US6438625B1 (en) * 1999-10-21 2002-08-20 Centigram Communications Corporation System and method for automatically identifying slots in a backplane
CN103123528A (zh) * 2011-11-18 2013-05-29 环旭电子股份有限公司 即插式模块、电子系统以及相应的判断方法与查询方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3736574A (en) * 1971-12-30 1973-05-29 Ibm Pseudo-hierarchy memory system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5441139U (en:Method) * 1977-08-26 1979-03-19

Also Published As

Publication number Publication date
AR214387A1 (es) 1979-06-15
DE2460781A1 (de) 1975-10-23
JPS5516334B2 (en:Method) 1980-05-01
FR2268305B1 (en:Method) 1977-07-08
DE2460781B2 (de) 1976-09-16
GB1459889A (en) 1976-12-31
IT1027866B (it) 1978-12-20
NL7503807A (nl) 1975-10-21
AU7657474A (en) 1976-06-24
FR2268305A1 (en:Method) 1975-11-14
SE408501B (sv) 1979-06-11
SE7503268L (sv) 1975-10-20
CH578765A5 (en:Method) 1976-08-13
BR7502331A (pt) 1976-02-17
ES433528A1 (es) 1976-12-01
CA1019456A (en) 1977-10-18
US3872452A (en) 1975-03-18

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