CH578765A5 - - Google Patents

Info

Publication number
CH578765A5
CH578765A5 CH1630274A CH1630274A CH578765A5 CH 578765 A5 CH578765 A5 CH 578765A5 CH 1630274 A CH1630274 A CH 1630274A CH 1630274 A CH1630274 A CH 1630274A CH 578765 A5 CH578765 A5 CH 578765A5
Authority
CH
Switzerland
Application number
CH1630274A
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of CH578765A5 publication Critical patent/CH578765A5/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0669—Configuration or reconfiguration with decentralised address assignment
    • G06F12/0676—Configuration or reconfiguration with decentralised address assignment the address being position dependent
CH1630274A 1974-04-17 1974-12-09 CH578765A5 (xx)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US461576A US3872452A (en) 1974-04-17 1974-04-17 Floating addressing system and method

Publications (1)

Publication Number Publication Date
CH578765A5 true CH578765A5 (xx) 1976-08-13

Family

ID=23833136

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1630274A CH578765A5 (xx) 1974-04-17 1974-12-09

Country Status (12)

Country Link
US (1) US3872452A (xx)
JP (1) JPS5516334B2 (xx)
AR (1) AR214387A1 (xx)
BR (1) BR7502331A (xx)
CA (1) CA1019456A (xx)
CH (1) CH578765A5 (xx)
ES (1) ES433528A1 (xx)
FR (1) FR2268305B1 (xx)
GB (1) GB1459889A (xx)
IT (1) IT1027866B (xx)
NL (1) NL7503807A (xx)
SE (1) SE408501B (xx)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4055802A (en) * 1976-08-12 1977-10-25 Bell Telephone Laboratories, Incorporated Electrical identification of multiply configurable circuit array
JPS5810240Y2 (ja) * 1977-08-26 1983-02-24 株式会社日立製作所 Ｉｃメモリユニツト
US4315321A (en) * 1978-06-16 1982-02-09 The Kardios Systems Corporation Method and apparatus for enhancing the capabilities of a computing system
US4296467A (en) * 1978-07-03 1981-10-20 Honeywell Information Systems Inc. Rotating chip selection technique and apparatus
JPS55110355A (en) * 1979-02-16 1980-08-25 Toshiba Corp Memory board and selection system for it
US4419747A (en) * 1981-09-14 1983-12-06 Seeq Technology, Inc. Method and device for providing process and test information in semiconductors
US4451903A (en) * 1981-09-14 1984-05-29 Seeq Technology, Inc. Method and device for encoding product and programming information in semiconductors
FR2520896B1 (fr) * 1982-02-01 1987-06-05 Merlin Gerin Dispositif d'adressage des cartes d'un automate programmable pour la securite des echanges sur le bus
GB2153567A (en) * 1984-01-12 1985-08-21 Sinclair Res Ltd Arrangements for enabling the connection of one or more additional devices to a computer
US4980856A (en) * 1986-10-20 1990-12-25 Brother Kogyo Kabushiki Kaisha IC memory cartridge and a method for providing external IC memory cartridges to an electronic device extending end-to-end
US4980850A (en) * 1987-05-14 1990-12-25 Digital Equipment Corporation Automatic sizing memory system with multiplexed configuration signals at memory modules
US4951248A (en) * 1988-03-04 1990-08-21 Sun Microsystems, Inc. Self configuring memory system
GB2226667B (en) * 1988-12-30 1993-03-24 Intel Corp Self-identification of memory
US4984213A (en) * 1989-02-21 1991-01-08 Compaq Computer Corporation Memory block address determination circuit
JPH02245840A (ja) * 1989-03-20 1990-10-01 Fujitsu Ltd 記憶装置
US5261073A (en) 1989-05-05 1993-11-09 Wang Laboratories, Inc. Method and apparatus for providing memory system status signals
US5012408A (en) * 1990-03-15 1991-04-30 Digital Equipment Corporation Memory array addressing system for computer systems with multiple memory arrays
US5295255A (en) * 1991-02-22 1994-03-15 Electronic Professional Services, Inc. Method and apparatus for programming a solid state processor with overleaved array memory modules
US5860028A (en) * 1996-02-01 1999-01-12 Paragon Electric Company, Inc. I/O bus expansion system wherein processor checks plurality of possible address until a response from the peripheral selected by address decoder using user input
US6438625B1 (en) * 1999-10-21 2002-08-20 Centigram Communications Corporation System and method for automatically identifying slots in a backplane
CN103123528A (zh) * 2011-11-18 2013-05-29 环旭电子股份有限公司 即插式模块、电子系统以及相应的判断方法与查询方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3736574A (en) * 1971-12-30 1973-05-29 Ibm Pseudo-hierarchy memory system

Also Published As

Publication number Publication date
ES433528A1 (es) 1976-12-01
CA1019456A (en) 1977-10-18
DE2460781B2 (de) 1976-09-16
AR214387A1 (es) 1979-06-15
JPS50137449A (xx) 1975-10-31
GB1459889A (en) 1976-12-31
FR2268305B1 (xx) 1977-07-08
US3872452A (en) 1975-03-18
NL7503807A (nl) 1975-10-21
SE408501B (sv) 1979-06-11
SE7503268L (sv) 1975-10-20
IT1027866B (it) 1978-12-20
DE2460781A1 (de) 1975-10-23
JPS5516334B2 (xx) 1980-05-01
AU7657474A (en) 1976-06-24
FR2268305A1 (xx) 1975-11-14
BR7502331A (pt) 1976-02-17

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Legal Events

Date Code Title Description
PL Patent ceased