GB2153567A - Arrangements for enabling the connection of one or more additional devices to a computer - Google Patents

Arrangements for enabling the connection of one or more additional devices to a computer Download PDF

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Publication number
GB2153567A
GB2153567A GB08400782A GB8400782A GB2153567A GB 2153567 A GB2153567 A GB 2153567A GB 08400782 A GB08400782 A GB 08400782A GB 8400782 A GB8400782 A GB 8400782A GB 2153567 A GB2153567 A GB 2153567A
Authority
GB
United Kingdom
Prior art keywords
computer
additional
connection means
arrangement according
reference voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB08400782A
Other versions
GB8400782D0 (en
Inventor
David Karlin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sinclair Research Ltd
Original Assignee
Sinclair Research Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sinclair Research Ltd filed Critical Sinclair Research Ltd
Priority to GB08400782A priority Critical patent/GB2153567A/en
Publication of GB8400782D0 publication Critical patent/GB8400782D0/en
Publication of GB2153567A publication Critical patent/GB2153567A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4063Device-to-bus coupling
    • G06F13/4068Electrical coupling
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646Configuration or reconfiguration
    • G06F12/0669Configuration or reconfiguration with decentralised address assignment
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits

Abstract

Additional devices, such as extra memory boards, peripheral interfaces and network interfaces, are connectible to a computer 11 by means of multi-pin plug and socket connections. The sockets 3-7 are connected in parallel to circuits of the computer and each has a plurality of additional contacts selectively connected to a reference voltage or a signal source in the computer, the combinations of connections of the additional contacts being different for the different sockets. Each additional device includes comparison logic for comparing input address data with signals or voltages derived from the additional contacts, so that additional devices plugged into the different sockets can be addressed separately by reference to the socket into which they are plugged. A CARD SELECT signal from the computer is used to inhibit spurious responses from the additional devices to an address signal combination which might accidentally be the same as that of an additional device. <IMAGE>

Description

SPECIFICATION Arrangements for enabling the connection of one or more additional devices to a computer This invention relates to arrangements for enabling the connection of one or more additional devices to a computer including a plurality of similar multicontact connection means connected in parallel to circuits of the computer.
It has been proposed to provide a plurality of similar sockets wired in parallel to the data and address busses of a computer so that devices such as additional memory capacity and interfaces for ad ditional output devices such as printers or to communications networks can be added to the computer in accordance with the user's particular requirements. A convenient way of transferring data between the additional devices and the computer itself is for the devices to be memory mapped, that is to say to have unique addresses so that when the computer wishes to communciate with them it has only to generate the appropriate address to open the communication path when data transfer can be effected.When several similar such devices are to be connected to the same computer, for example the addition of several cards bearing extra memory capacity, it is necessary for some means to be provided for distinguishing one card from another, otherwise the computer will treat them all as being identical. In order to achieve this it has been proposed to provide manually pre-settable switches 2 on the cards so that each has a unique address. A difficulty with this procedure is that if for some reason the switches are not correctly set or are not set at all, then the selection of the devices by the computer cannot be achieved as required.
It is an object of the present invention to overcome the above difficulty by providing an automanic allocation of addresses to additional devices when added to a computer so that the manual presetting of switches is no longer required.
According to the present invention there is pro vided an arrangement for enabling the connection of one or more additional devices to a computer including a plurality of similar multicontact connection means connected in parallel to circuits of the computer, each additional device having a connector able to be connected to any one of the connection means, wherein the connection means include a plurality of additional contacts selectively connected in different combinations to a reference voltage or a signal source in the computer, and each additional device includes logic means con nectible to respond to the combination of connections to the voltage or signal and to address data from the computer, thereby to enable devices connected to different connection means to be addressed selectively by the computer.
The connection means may be a socket and the connector may be a plug such as an edge connection on a printed circuit board which can be inserted into the socket.
The reference voltage may be a +5 volt supply used to establish a logic 1 level on the contacts to which it is connected. The logic means may in clude a plurality of exclusive OR gates respectively connectible to the additional contacts and having as their other inputs part or all of the address information from the computer. The outputs of the exclusive OR gates may be connected as inputs to a NOR gate having as a further input a CARD SE LECT signal from the computer.
The plurality of connection means may be mounted on a printed circuit back plane which is connectible to an input/output connection means of the computer itself. In order that any of the additional devices may be connected directly to the computer without the use of the back plane, the connection means on the computer may also be provided with the plurality of additional contacts, using a combination of connections corresponding to an initial combination used on the back plane.
Alternatively, a different combination from any of those provided on the back plane may be used.
In order that the invention may be fully understood and readily carried into effect it will now be described with reference to the accompanying drawings, of which: Figure I is a diagram of one embodiment of the invention; and Figure 2 shows a possiible logic means for use on a device connectible to any of the connection means shown in Figure 1.
Referring now to Figure 1, the arrangement includes a printed circuit expansion back plane 1 bearing a plurality of parallel conductors 2 which are connected to separate connection means 3, 4, 5, 6 and 7 which may conveniently be multicontact sockets for edge connections on printed circuit boards. The conductors 2 on the plane 1, which include a 5 volt conductor and a 0 volt conductor, are connected through a cable 8 to a plug 9 which fits into a socket 10 connected to a computer 11.
The details of the connection of the socket 10 to the computer 11 are not shown since these are not relevant to the present invention and would be well understood by those skilled in the art.
The lowermost four contacts of the socket 10 which is of the same construction as the sockets 3 to 7 are connected to the 0 volt conductor. The lowermost four contacts of the sockets 3 to 7 are selectively connected in different combinations to the 5 volt and 0 volt conductors so as to produce a unique logical combination at each socket.
As shown in Figure 1, the combinations are in accordance with ascending binary numbers starting from 0001 for the socket 3 to 1111 for the socket 7. Thus the arrangement shown in Figure 1 can provide for fifteen different combinations, and therefore the board 1 may carry 15 sockets. It will be noticed that the socket 10 corresponds to the binary number 0000 because all of the four lowest contacts 2 are connected to 0 volts. A further socket corresponding to 0000 may be provided on the back plane unless it is necessary to distinguish between a device plugged directly into the computer and one plugged into the back plane.
Each of the additional devices which is connecti ble to the computer can be plugged into any of the sockets 3 to 7. They may also be plugged into the socket 10 provided that the back plane 1 is not plugged into it. Each additional device will include an address selection circuit enabling the computer to communicate with it and with it alone. One example of such an address selection circuit is shown in Figure 2, which shows the peripheral select signals obtained from the lowermost four contacts of each of the sockets being connected to inputs of respective exclusive OR gates 12, 13, 14 and 15. The other inputs of these gates are connected respectively to contacts 16, 17, 18 and 19 connectible to others of the contacts of the sockets through which part of the address information from the computer is applied to the device.The outputs of the exclusive OR gates 12 to 15 are applied to respective inputs of a NOR-gate 20 together with a further CARD SELECT input from the computer via a contact 21. If the particular device is selected, then the output of the NOR gate 20 on conductor 22 will go high and may be used in the device to activate the response required by the computer from it. Other address lines 23 may be provided between contacts of the sockets and address selection circuits in the device to enable the computer to address part only of that device; this would be necessary if the device were some form of memory expansion.
Although the invention has been described with reference to a specific example, it will be appreciated that many modifications may be made to the example without departing from the invention. For example, the number of contacts connected in coded combinations to the 5 volt and 0 volt supplies on the back plane may be larger or smaller than the four shown. In addition, not all of the possible combinations of the conductors provided need be used. The connection means which are described as sockets and the connectors co-operating with them which are described as plugs are only examples of the kind of components which may be used, and any type of connection means and connector which is appropriate to the particular application of the arrangement will be suitable.
In an alternative it would be possible for the reference voltages to be applied through two or more of the lowermost four contacts of the socket 10 and the same combination may be used or not used as required on the back plane 1. In yet another alternative, instead of 5 volts (or any other steady voltage), there may be used a pulsed signal from the computer to which the exclusive OR gates 12 to 15 would respond.
The CARD SELECT signal shown in Figure 2 as applied to the gate 20 from the input 21 is necessary because during the operation of the computer various combinations of signals will appear on the address bus and will be applied to inputs of the gates 12 to 15, and it is possible that such a combination might correspond to the combination of peripheral select signals applied to the gates when communication with a particular device is not required.

Claims (8)

1. An arrangement for enabling the connection of one or more additional devices to a computer including a plurality of similar multicontact connection means connected in parallel to circuits of the computer, each additional device having a connector able to be connected to any one of the connection means, wherein the connection means include a plurality of additional contacts selectively connected in different combinations to a reference voltage or a signal source in the computer, and each additional device includes logic means connectible to respond to the combination of connections to the voltage or signal and to address data from the computer, thereby to enable devices connected to different connection means to be addressed selectively by the computer.
2. An arrangement according to claim 1 in which each connection means is a multi-pin socket and each connector is a multi-pin plug.
3. An arrangement according to claim 1 or 2 wherein the reference voltage corresponds to a logic 1 level and those of the additional contacts not connected to the reference voltage are connected to a voltage corresponding to a logic 0 level.
4. An arrangement according to claim 3 wherein the reference voltage is +5 volts and the other voltage is 0 volts.
5. An arrangement according to any preceding claim wherein the logic means includes a plurality of exclusive OR gates having inputs respectively connectible to the additional contacts and being connectible to receive on their other inputs part or all of the address information from the computer, and a NOR gate to which the outputs of the exclusive OR gates are connected, the output of the NOR gate indicating when the part or all of the address information from the computer corresponds to the particular combination of connections of the additional contacts to the reference voltage or signal source at the connection means to which the additional device in question is connected.
6. An arrangement according to claim 5 wherein the NOR gate has a further input for receiving a CARD SELECT signal from the computer.
7. An arrangement according to any preceding claim in which the connection means are mounted on a circuit board detachably connected to the computer via a similar multicontact connection means mounted on the computer, whereby a single additional device may be connected directly to the computer without using the circuit board.
8. An arrangement for connecting one or more additional devices to a computer substantially as described herein with reference to the accompanying drawings.
GB08400782A 1984-01-12 1984-01-12 Arrangements for enabling the connection of one or more additional devices to a computer Withdrawn GB2153567A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB08400782A GB2153567A (en) 1984-01-12 1984-01-12 Arrangements for enabling the connection of one or more additional devices to a computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB08400782A GB2153567A (en) 1984-01-12 1984-01-12 Arrangements for enabling the connection of one or more additional devices to a computer

Publications (2)

Publication Number Publication Date
GB8400782D0 GB8400782D0 (en) 1984-02-15
GB2153567A true GB2153567A (en) 1985-08-21

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Family Applications (1)

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GB08400782A Withdrawn GB2153567A (en) 1984-01-12 1984-01-12 Arrangements for enabling the connection of one or more additional devices to a computer

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0289157A2 (en) * 1987-04-17 1988-11-02 Tandem Computers Incorporated Electrical keying for replaceable modules
FR2622711A1 (en) * 1987-11-04 1989-05-05 Trt Telecom Radio Electr Device intended to replace an integrated circuit including, on the same chip, a signal processor and a memory assembly containing fixed information
EP0429780A2 (en) * 1989-11-29 1991-06-05 Kabushiki Kaisha Toshiba Computer system capable of connecting expansion unit
WO1997016782A2 (en) * 1995-10-18 1997-05-09 Leslie Christopher Holborow Computer network security arrangements

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3872452A (en) * 1974-04-17 1975-03-18 Ibm Floating addressing system and method
US4007452A (en) * 1975-07-28 1977-02-08 Intel Corporation Wafer scale integration system
EP0086137A1 (en) * 1982-02-01 1983-08-17 Merlin Gerin A programmable machine card addressing device for the security of exchanges on the bus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3872452A (en) * 1974-04-17 1975-03-18 Ibm Floating addressing system and method
US4007452A (en) * 1975-07-28 1977-02-08 Intel Corporation Wafer scale integration system
EP0086137A1 (en) * 1982-02-01 1983-08-17 Merlin Gerin A programmable machine card addressing device for the security of exchanges on the bus

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0289157A2 (en) * 1987-04-17 1988-11-02 Tandem Computers Incorporated Electrical keying for replaceable modules
EP0289157A3 (en) * 1987-04-17 1989-10-18 Tandem Computers Incorporated Electrical keying for replaceable modules
FR2622711A1 (en) * 1987-11-04 1989-05-05 Trt Telecom Radio Electr Device intended to replace an integrated circuit including, on the same chip, a signal processor and a memory assembly containing fixed information
EP0429780A2 (en) * 1989-11-29 1991-06-05 Kabushiki Kaisha Toshiba Computer system capable of connecting expansion unit
EP0429780A3 (en) * 1989-11-29 1994-08-24 Toshiba Kk Computer system capable of connecting expansion unit
US5428798A (en) * 1989-11-29 1995-06-27 Kabushiki Kaisha Toshiba Computer system capable of connecting expansion unit
US5440748A (en) * 1989-11-29 1995-08-08 Kabushiki Kaisha Toshiba Computer system capable of connecting expansion unit
WO1997016782A2 (en) * 1995-10-18 1997-05-09 Leslie Christopher Holborow Computer network security arrangements
WO1997016782A3 (en) * 1995-10-18 1997-06-26 Leslie Christopher Holborow Computer network security arrangements

Also Published As

Publication number Publication date
GB8400782D0 (en) 1984-02-15

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WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)