JPS4950878A - - Google Patents
Info
- Publication number
- JPS4950878A JPS4950878A JP47093410A JP9341072A JPS4950878A JP S4950878 A JPS4950878 A JP S4950878A JP 47093410 A JP47093410 A JP 47093410A JP 9341072 A JP9341072 A JP 9341072A JP S4950878 A JPS4950878 A JP S4950878A
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP47093410A JPS525228B2 (en:Method) | 1972-09-18 | 1972-09-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP47093410A JPS525228B2 (en:Method) | 1972-09-18 | 1972-09-18 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS4950878A true JPS4950878A (en:Method) | 1974-05-17 |
| JPS525228B2 JPS525228B2 (en:Method) | 1977-02-10 |
Family
ID=14081513
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP47093410A Expired JPS525228B2 (en:Method) | 1972-09-18 | 1972-09-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS525228B2 (en:Method) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52157768U (en:Method) * | 1976-05-26 | 1977-11-30 | ||
| JPS538565A (en) * | 1976-07-12 | 1978-01-26 | Nec Corp | Semiconductor device |
| JPS5371584A (en) * | 1976-12-08 | 1978-06-26 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS5418168U (en:Method) * | 1977-06-06 | 1979-02-06 | ||
| JPS5596646A (en) * | 1979-01-17 | 1980-07-23 | Nec Corp | Semiconductor device |
| JPS5662352A (en) * | 1979-10-26 | 1981-05-28 | Hitachi Ltd | Semiconductor integrated circuit device for acoustic amplification circuit |
| JPS58194363A (ja) * | 1982-05-07 | 1983-11-12 | Hitachi Ltd | 半導体集積回路装置 |
| JPS60103631A (ja) * | 1983-11-11 | 1985-06-07 | Nec Corp | 半導体集積回路装置 |
| JPS622627A (ja) * | 1985-06-28 | 1987-01-08 | Toshiba Corp | 半導体集積回路 |
| JPS6225445A (ja) * | 1985-07-25 | 1987-02-03 | Toshiba Corp | 半導体集積回路装置 |
| US7414300B2 (en) | 2005-09-26 | 2008-08-19 | Mitsubishi Denki Kabushiki Kaisha | Molded semiconductor package |
-
1972
- 1972-09-18 JP JP47093410A patent/JPS525228B2/ja not_active Expired
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52157768U (en:Method) * | 1976-05-26 | 1977-11-30 | ||
| JPS538565A (en) * | 1976-07-12 | 1978-01-26 | Nec Corp | Semiconductor device |
| JPS5371584A (en) * | 1976-12-08 | 1978-06-26 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS5418168U (en:Method) * | 1977-06-06 | 1979-02-06 | ||
| JPS5596646A (en) * | 1979-01-17 | 1980-07-23 | Nec Corp | Semiconductor device |
| JPS5662352A (en) * | 1979-10-26 | 1981-05-28 | Hitachi Ltd | Semiconductor integrated circuit device for acoustic amplification circuit |
| JPS58194363A (ja) * | 1982-05-07 | 1983-11-12 | Hitachi Ltd | 半導体集積回路装置 |
| JPS60103631A (ja) * | 1983-11-11 | 1985-06-07 | Nec Corp | 半導体集積回路装置 |
| JPS622627A (ja) * | 1985-06-28 | 1987-01-08 | Toshiba Corp | 半導体集積回路 |
| JPS6225445A (ja) * | 1985-07-25 | 1987-02-03 | Toshiba Corp | 半導体集積回路装置 |
| US7414300B2 (en) | 2005-09-26 | 2008-08-19 | Mitsubishi Denki Kabushiki Kaisha | Molded semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS525228B2 (en:Method) | 1977-02-10 |