JPS4945650A - - Google Patents
Info
- Publication number
- JPS4945650A JPS4945650A JP6098673A JP6098673A JPS4945650A JP S4945650 A JPS4945650 A JP S4945650A JP 6098673 A JP6098673 A JP 6098673A JP 6098673 A JP6098673 A JP 6098673A JP S4945650 A JPS4945650 A JP S4945650A
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/83—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
- G11C29/832—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption with disconnection of faulty elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Static Random-Access Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US26782772A | 1972-06-30 | 1972-06-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS4945650A true JPS4945650A (en:Method) | 1974-05-01 |
| JPS5440183B2 JPS5440183B2 (en:Method) | 1979-12-01 |
Family
ID=23020290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6098673A Expired JPS5440183B2 (en:Method) | 1972-06-30 | 1973-06-01 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US3750116A (en:Method) |
| JP (1) | JPS5440183B2 (en:Method) |
| CA (1) | CA1019835A (en:Method) |
| DE (1) | DE2332555A1 (en:Method) |
| FR (1) | FR2191203B1 (en:Method) |
| GB (1) | GB1418552A (en:Method) |
| IT (1) | IT982699B (en:Method) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6356498B1 (en) | 1996-07-24 | 2002-03-12 | Micron Technology, Inc. | Selective power distribution circuit for an integrated circuit |
| JP2009093205A (ja) * | 2009-02-02 | 2009-04-30 | Hinomoto Gosei Jushi Seisakusho:Kk | 分子模型 |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3986179A (en) * | 1975-06-30 | 1976-10-12 | Honeywell Information Systems, Inc. | Fault-tolerant CCD memory chip |
| JPS5857838B2 (ja) * | 1980-12-29 | 1983-12-22 | 富士通株式会社 | デコ−ド回路 |
| US4963769A (en) * | 1989-05-08 | 1990-10-16 | Cypress Semiconductor | Circuit for selective power-down of unused circuitry |
| US20030074610A1 (en) * | 2001-10-16 | 2003-04-17 | Umax Data Systems Inc. | Method for improving utilization of a defective memory device in an image processing system |
| KR100481849B1 (ko) * | 2001-12-04 | 2005-04-11 | 삼성전자주식회사 | 용량 변경이 가능한 캐쉬 메모리 및 이를 구비한 프로세서칩 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3402398A (en) * | 1964-08-31 | 1968-09-17 | Bunker Ramo | Plural content addressed memories with a common sensing circuit |
| US3422402A (en) * | 1965-12-29 | 1969-01-14 | Ibm | Memory systems for using storage devices containing defective bits |
| US3588830A (en) * | 1968-01-17 | 1971-06-28 | Ibm | System for using a memory having irremediable bad bits |
| US3659275A (en) * | 1970-06-08 | 1972-04-25 | Cogar Corp | Memory correction redundancy system |
| US3688280A (en) * | 1970-09-22 | 1972-08-29 | Ibm | Monolithic memory system with bi-level powering for reduced power consumption |
-
1972
- 1972-06-30 US US00267827A patent/US3750116A/en not_active Expired - Lifetime
-
1973
- 1973-04-05 IT IT22598/73A patent/IT982699B/it active
- 1973-06-01 JP JP6098673A patent/JPS5440183B2/ja not_active Expired
- 1973-06-04 CA CA173,052A patent/CA1019835A/en not_active Expired
- 1973-06-06 FR FR7321782A patent/FR2191203B1/fr not_active Expired
- 1973-06-25 GB GB3004073A patent/GB1418552A/en not_active Expired
- 1973-06-27 DE DE2332555A patent/DE2332555A1/de active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6356498B1 (en) | 1996-07-24 | 2002-03-12 | Micron Technology, Inc. | Selective power distribution circuit for an integrated circuit |
| JP2009093205A (ja) * | 2009-02-02 | 2009-04-30 | Hinomoto Gosei Jushi Seisakusho:Kk | 分子模型 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5440183B2 (en:Method) | 1979-12-01 |
| CA1019835A (en) | 1977-10-25 |
| FR2191203A1 (en:Method) | 1974-02-01 |
| DE2332555A1 (de) | 1974-01-17 |
| FR2191203B1 (en:Method) | 1976-04-30 |
| IT982699B (it) | 1974-10-21 |
| US3750116A (en) | 1973-07-31 |
| GB1418552A (en) | 1975-12-24 |