JPS4940670A - - Google Patents
Info
- Publication number
- JPS4940670A JPS4940670A JP8472072A JP8472072A JPS4940670A JP S4940670 A JPS4940670 A JP S4940670A JP 8472072 A JP8472072 A JP 8472072A JP 8472072 A JP8472072 A JP 8472072A JP S4940670 A JPS4940670 A JP S4940670A
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Dicing (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8472072A JPS5719573B2 (US07754267-20100713-C00021.png) | 1972-08-23 | 1972-08-23 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8472072A JPS5719573B2 (US07754267-20100713-C00021.png) | 1972-08-23 | 1972-08-23 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS4940670A true JPS4940670A (US07754267-20100713-C00021.png) | 1974-04-16 |
JPS5719573B2 JPS5719573B2 (US07754267-20100713-C00021.png) | 1982-04-23 |
Family
ID=13838503
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8472072A Expired JPS5719573B2 (US07754267-20100713-C00021.png) | 1972-08-23 | 1972-08-23 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5719573B2 (US07754267-20100713-C00021.png) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60213662A (ja) * | 1984-03-27 | 1985-10-25 | エフ・エム・シ−・コ−ポレ−シヨン | 熱可塑性バツグ製造機械 |
JP2010182901A (ja) * | 2009-02-06 | 2010-08-19 | Disco Abrasive Syst Ltd | 半導体ウエーハの分割方法 |
-
1972
- 1972-08-23 JP JP8472072A patent/JPS5719573B2/ja not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60213662A (ja) * | 1984-03-27 | 1985-10-25 | エフ・エム・シ−・コ−ポレ−シヨン | 熱可塑性バツグ製造機械 |
JP2010182901A (ja) * | 2009-02-06 | 2010-08-19 | Disco Abrasive Syst Ltd | 半導体ウエーハの分割方法 |
Also Published As
Publication number | Publication date |
---|---|
JPS5719573B2 (US07754267-20100713-C00021.png) | 1982-04-23 |