JPS4919030B1 - - Google Patents

Info

Publication number
JPS4919030B1
JPS4919030B1 JP597569A JP597569A JPS4919030B1 JP S4919030 B1 JPS4919030 B1 JP S4919030B1 JP 597569 A JP597569 A JP 597569A JP 597569 A JP597569 A JP 597569A JP S4919030 B1 JPS4919030 B1 JP S4919030B1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP597569A
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP597569A priority Critical patent/JPS4919030B1/ja
Priority to GB387670A priority patent/GB1287221A/en
Priority to NL7001170A priority patent/NL142825B/xx
Priority to FR7003022A priority patent/FR2029636B1/fr
Priority to DE19702003952 priority patent/DE2003952C3/de
Publication of JPS4919030B1 publication Critical patent/JPS4919030B1/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76245—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using full isolation by porous oxide silicon, i.e. FIPOS techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Bipolar Transistors (AREA)
  • Weting (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Local Oxidation Of Silicon (AREA)
JP597569A 1969-01-29 1969-01-29 Pending JPS4919030B1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP597569A JPS4919030B1 (fr) 1969-01-29 1969-01-29
GB387670A GB1287221A (en) 1969-01-29 1970-01-27 Semiconductor device and method of producing the same
NL7001170A NL142825B (nl) 1969-01-29 1970-01-28 Werkwijze voor de vervaardiging van een siliciumhalfgeleiderinrichting, en halfgeleiderinrichting, verkregen volgens deze werkwijze.
FR7003022A FR2029636B1 (fr) 1969-01-29 1970-01-28
DE19702003952 DE2003952C3 (de) 1969-01-29 1970-01-29 Verfahren zur Herstellung einer Halbleitervorrichtung mit mindestens einem unter Anwendung eines anodischen Prozesses erzeugten isolierenden Bereich

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP597569A JPS4919030B1 (fr) 1969-01-29 1969-01-29

Publications (1)

Publication Number Publication Date
JPS4919030B1 true JPS4919030B1 (fr) 1974-05-14

Family

ID=11625834

Family Applications (1)

Application Number Title Priority Date Filing Date
JP597569A Pending JPS4919030B1 (fr) 1969-01-29 1969-01-29

Country Status (5)

Country Link
JP (1) JPS4919030B1 (fr)
DE (1) DE2003952C3 (fr)
FR (1) FR2029636B1 (fr)
GB (1) GB1287221A (fr)
NL (1) NL142825B (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3961353A (en) * 1974-10-21 1976-06-01 International Business Machines Corporation High power semiconductor device
US4016017A (en) * 1975-11-28 1977-04-05 International Business Machines Corporation Integrated circuit isolation structure and method for producing the isolation structure
US4111720A (en) * 1977-03-31 1978-09-05 International Business Machines Corporation Method for forming a non-epitaxial bipolar integrated circuit
GB2038548B (en) * 1978-10-27 1983-03-23 Nippon Telegraph & Telephone Isolating semiconductor device by porous silicon oxide

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE671953A (fr) * 1964-11-05

Also Published As

Publication number Publication date
NL142825B (nl) 1974-07-15
DE2003952A1 (de) 1972-02-03
NL7001170A (fr) 1970-07-31
DE2003952B2 (de) 1974-08-01
FR2029636A1 (fr) 1970-10-23
DE2003952C3 (de) 1975-03-20
FR2029636B1 (fr) 1973-10-19
GB1287221A (en) 1972-08-31

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