JPS49100970A - - Google Patents
Info
- Publication number
- JPS49100970A JPS49100970A JP860573A JP860573A JPS49100970A JP S49100970 A JPS49100970 A JP S49100970A JP 860573 A JP860573 A JP 860573A JP 860573 A JP860573 A JP 860573A JP S49100970 A JPS49100970 A JP S49100970A
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
- G11B5/127—Structure or manufacture of heads, e.g. inductive
- G11B5/31—Structure or manufacture of heads, e.g. inductive using thin films
- G11B5/3163—Fabrication methods or processes specially adapted for a particular head structure, e.g. using base layers for electroplating, using functional layers for masking, using energy or particle beams for shaping the structure or modifying the properties of the basic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/147—Semiconductor insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4685—Manufacturing of cross-over conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP860573A JPS49100970A (en) | 1973-01-22 | 1973-01-22 | |
DE2402720A DE2402720A1 (en) | 1973-01-22 | 1974-01-21 | Forming electric connections on electric circuits - by depositing a metal layer, anodically oxidising esp. its edges to cover any protrusions, and applying an outer insulating coating |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP860573A JPS49100970A (en) | 1973-01-22 | 1973-01-22 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS49100970A true JPS49100970A (en) | 1974-09-24 |
Family
ID=11697580
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP860573A Pending JPS49100970A (en) | 1973-01-22 | 1973-01-22 |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPS49100970A (en) |
DE (1) | DE2402720A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51126079A (en) * | 1975-04-25 | 1976-11-02 | Hitachi Ltd | Growth method of many layer wiring |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3407784A1 (en) * | 1984-03-02 | 1985-09-12 | Brown, Boveri & Cie Ag, 6800 Mannheim | THICK-LAYER HYBRID CIRCUIT |
DE10343279B4 (en) * | 2003-09-18 | 2007-02-15 | Thomas Passe | Electrical line system |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4933232A (en) * | 1972-07-28 | 1974-03-27 |
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1973
- 1973-01-22 JP JP860573A patent/JPS49100970A/ja active Pending
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1974
- 1974-01-21 DE DE2402720A patent/DE2402720A1/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4933232A (en) * | 1972-07-28 | 1974-03-27 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51126079A (en) * | 1975-04-25 | 1976-11-02 | Hitachi Ltd | Growth method of many layer wiring |
Also Published As
Publication number | Publication date |
---|---|
DE2402720A1 (en) | 1974-08-22 |