JPS4878470A - - Google Patents

Info

Publication number
JPS4878470A
JPS4878470A JP988172A JP988172A JPS4878470A JP S4878470 A JPS4878470 A JP S4878470A JP 988172 A JP988172 A JP 988172A JP 988172 A JP988172 A JP 988172A JP S4878470 A JPS4878470 A JP S4878470A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP988172A
Other versions
JPS5517518B2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP988172A priority Critical patent/JPS5517518B2/ja
Priority to DE19732303158 priority patent/DE2303158A1/de
Priority to FR7302576A priority patent/FR2169227A1/fr
Priority to NL7301256A priority patent/NL7301256A/xx
Publication of JPS4878470A publication Critical patent/JPS4878470A/ja
Publication of JPS5517518B2 publication Critical patent/JPS5517518B2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • H05K3/4667—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders characterized by using an inorganic intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/207—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a prefabricated paste pattern, ink pattern or powder pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0275—Fibers and reinforcement materials
    • H05K2201/0284—Paper, e.g. as reinforcement
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0376—Flush conductors, i.e. flush with the surface of the printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0156—Temporary polymeric carrier or foil, e.g. for processing or transferring

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
JP988172A 1972-01-28 1972-01-28 Expired JPS5517518B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP988172A JPS5517518B2 (ja) 1972-01-28 1972-01-28
DE19732303158 DE2303158A1 (de) 1972-01-28 1973-01-23 Verfahren zur herstellung von anschlussplatten
FR7302576A FR2169227A1 (ja) 1972-01-28 1973-01-25
NL7301256A NL7301256A (ja) 1972-01-28 1973-01-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP988172A JPS5517518B2 (ja) 1972-01-28 1972-01-28

Publications (2)

Publication Number Publication Date
JPS4878470A true JPS4878470A (ja) 1973-10-22
JPS5517518B2 JPS5517518B2 (ja) 1980-05-12

Family

ID=11732484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP988172A Expired JPS5517518B2 (ja) 1972-01-28 1972-01-28

Country Status (4)

Country Link
JP (1) JPS5517518B2 (ja)
DE (1) DE2303158A1 (ja)
FR (1) FR2169227A1 (ja)
NL (1) NL7301256A (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5210568A (en) * 1974-12-28 1977-01-26 Hideo Machida Method of manufacturing multilayered printed wiring substrate
JPS52154074A (en) * 1976-06-18 1977-12-21 Fujitsu Ltd Method of producing multilayer alumina substrate
JPS54111670A (en) * 1978-02-22 1979-09-01 Alps Electric Co Ltd Circuit board and method of forming same
JPS6419795A (en) * 1987-07-14 1989-01-23 Midori Mark Seisakusho Kk Flexible printed wiring board with multilayered pattern and manufacture thereof

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0074605B1 (en) * 1981-09-11 1990-08-29 Kabushiki Kaisha Toshiba Method for manufacturing multilayer circuit substrate
US4480288A (en) * 1982-12-27 1984-10-30 International Business Machines Corporation Multi-layer flexible film module
US4648179A (en) * 1983-06-30 1987-03-10 International Business Machines Corporation Process of making interconnection structure for semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
TECHNICAL DISCLOSURE BULLETIN#M5=1969 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5210568A (en) * 1974-12-28 1977-01-26 Hideo Machida Method of manufacturing multilayered printed wiring substrate
JPS52154074A (en) * 1976-06-18 1977-12-21 Fujitsu Ltd Method of producing multilayer alumina substrate
JPS5546077B2 (ja) * 1976-06-18 1980-11-21
JPS54111670A (en) * 1978-02-22 1979-09-01 Alps Electric Co Ltd Circuit board and method of forming same
JPS6419795A (en) * 1987-07-14 1989-01-23 Midori Mark Seisakusho Kk Flexible printed wiring board with multilayered pattern and manufacture thereof
JPH0252432B2 (ja) * 1987-07-14 1990-11-13 Midori Maaku Seisakusho Kk

Also Published As

Publication number Publication date
NL7301256A (ja) 1973-07-31
JPS5517518B2 (ja) 1980-05-12
DE2303158A1 (de) 1973-08-23
FR2169227A1 (ja) 1973-09-07

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