JPH1197562A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent dielectric breakdown of an insulating film at an edge of a floating gate electrode. SOLUTION: A semiconductor integrated circuit device has non-volatile memory cells of a MISFET type which utilizes a tunnel phenomenon to a first insulating film to erase information from a source region. The device includes (1) a floating gate electrode 7 provided on a semiconductor substrate via a second insulating film 8, (2) a control gate electrode 9 provided on the floating gate electrode 7 via a second insulating film 8, and (3) first and second n type semiconductor regions 11 and 14 acting as source and drain regions of the MISFET and provided at both ends of the floating and control gate electrodes on the semiconductor substrate. The floating gate electrode 7 is such a shape that eases electric field concentration at its corners.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a semiconductor integrated circuit device having a nonvolatile memory circuit.

[0002]

BACKGROUND ART nonvolatile storage circuit of the read electrical erasable private (E lectrically E rasable P rogrammable R ead
O nly M emory) 1 element type nonvolatile memory cell as a non-volatile memory have been proposed. This nonvolatile memory cell is constituted by a field effect transistor MISFET having a floating gate electrode (information storage gate electrode) and a control electrode (control gate electrode). The source region of this MISFET is connected to a source line, and the drain region is connected to a data line.

The nonvolatile memory cell is called a flash type nonvolatile memory cell, and is configured as a hot electron writing type and a tunnel erasing type. That is, the information writing operation of the nonvolatile memory cell is
Hot electrons are generated in a high electric field near the drain region, and the hot electrons are injected into the information storage gate electrode. On the other hand, in the information erasing operation of the nonvolatile memory cell, electrons stored in the information storage gate electrode are transferred to the source region by the Fower-Nordheim system.
This is done by releasing by pe tunneling.

The EEPROM composed of the flash type nonvolatile memory cells has a feature that the capacity can be increased because the cell area can be reduced by one element type as described above.

In the above-mentioned EEPROM, 1
988 IEEE International Solid-State Circuit
s Conference pp. 132, 133 and 330.

[0006]

SUMMARY OF THE INVENTION The present inventor has proposed the above-mentioned E
As a result of studying the EPROM, it has been found that the following problems occur.

That is, there is a large variation in erase characteristics between memory cells. There is a problem that reliability is inferior due to the relatively small number of times that rewriting is possible repeatedly.

[0008] The erasing characteristic largely depends on the shape of the floating gate electrode, especially at the end thereof. The electric field applied between the floating gate electrode and the source region at the time of erasing is as high as 108 V / m or more, but the intensity distribution is not uniform. Tend to concentrate. Therefore, a slight variation in the shape of the gate electrode causes a large variation in the erasing characteristics.

If the applied electric field at the time of erasing is concentrated in a specific location, the insulating film is likely to be destroyed or deteriorated at the concentrated location. Therefore, the number of times of application of the erase voltage, that is, the number of times of rewriting is reduced.

Further, since the source region is formed by a self-aligned ion implantation process with respect to the floating gate electrode and the control gate electrode, the overlapping region between the source region and the floating gate electrode cannot be made sufficiently large. For this reason, large variations in erasing characteristics occur due to process variations.

Further, the above-described arsenic ion implantation for forming the source region is performed through an insulating film, for example, a thermal oxide film provided on the surface of the semiconductor substrate. At that time, a dangling bond is generated in the oxide film at the end of the floating gate electrode. Due to this dangling bond, a leak current flows between the floating gate electrode and the source region, the breakdown voltage between the floating gate electrode and the source region is reduced, and the number of rewriting repetitions is reduced. Further, the erasing characteristics between the memory cells vary due to the leak current described above.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique for reducing the variation in erasing characteristics between storage elements and increasing the number of times of rewriting repeatedly to enable a highly reliable nonvolatile storage element. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

Means for Solving the Problems A summary of typical inventions among the inventions disclosed in the present application is as follows.

That is, there is provided an electric field impact means for reducing an electric field generated between the source region and the end of the floating gate electrode when an erase voltage is applied.

Further, a first conductive layer for forming a floating gate electrode and a second conductive layer for forming a control gate electrode are formed, and at least one of a source region and a drain region is connected to a control gate. After being formed by self-alignment using the electrode as a mask, a side wall spacer extending laterally of the control gate electrode is formed, and the floating gate electrode is formed by self-alignment using the side wall spacer and the control gate electrode as a mask. It forms.

Furthermore, after performing arsenic ion implantation for forming a source region in a self-aligned manner on the floating gate electrode and the control gate electrode, a thermal oxidation treatment is performed.

[0018]

According to the above-mentioned means, the applied electric field at the time of erasing is prevented from being concentrated at the end of the floating gate electrode, and electron tunnel emission is performed in a flat portion remote from the end of the gate electrode. Become like

This achieves the object of reducing the variation in the erasing characteristics between the memory cells and increasing the number of times that rewriting can be performed repeatedly to enable a highly reliable nonvolatile memory cell.

Further, according to the above-described means, the overlapping area between the source region or the drain region and the floating gate can be reduced while utilizing the fine processing technique based on the self-alignment without forcibly performing the stretching and diffusion processing more than necessary. Can be large.

[0021] With this process, a process which is excellent in reproducibility and controllability and enables microfabrication by self-alignment can reduce variations in erasing characteristics, increase the number of times of rewriting, and increase the reliability of nonvolatile memory. The goal of enabling flexible memory cells is achieved.

Further, according to the above-mentioned means, it is possible to reduce dangling bonds in the insulating film between the end of the floating gate electrode and the source region.

As a result, a reduction in the breakdown voltage between the floating gate electrode and the source region can be prevented, the number of times of rewriting can be increased, and the erasure characteristics between memory cells can be prevented from being varied.

[0024]

FIG. 1 is an equivalent circuit diagram of a part of a memory cell array and peripheral circuits of a FEPROM to which the present invention is applied, and FIG. 2 is a plan view of a part of the memory cell array.

An outline of the EEPROM will be described with reference to FIG.

The memory cell Qm is composed of a MISFET having a floating gate electrode and a control gate electrode. The control gate electrode of MISFET Qm is connected to word line WL. The drain region of MISFET Qm is connected to data line DL, and the source region of MISFET Qm is connected to ground potential line GL. Data line D
L and the ground line GL are parallel to each other and formed in a direction crossing the word line WL. That is, the memory cell array includes the memory cells Qm, the word lines WL, the data lines DL, and the ground lines GL.

One end of the word line WL is connected to an X decoder X-DEC which is a word line selection circuit. Data line D
One end of L is connected to the drive circuit DR of the data line DL,
The other ends are input / output circuits DOB and DIB through an n-channel MISFET Qc constituting a column switch circuit
Connected to. The output of the Y decoder and Y-DEC which is a data line selection circuit is supplied to the gate electrode of the MISFET Qc. The ground line GL has a p-channel MISFET
CM including QS1 and n-channel MISFET QS2
The output of the OS inverter circuit IV is supplied. Input terminals of inverter circuit IV, that is, MISFETs QS1 and QS
The erase signal φ￣E is supplied to the second gate electrode. The output circuit DOB including the sense amplifier circuit amplifies the signal applied to the selected data line DL and outputs the amplified signal to the external input / output terminal I / O in the read operation. Input circuit D
The IB supplies a signal supplied to an external terminal to the data line DL in a write operation. Circuits other than the memory cell array, that is, peripheral circuits are formed of CMOS circuits like the inverter circuit IV, and perform a static operation.

Writing, reading, and erasing of this EEPROM are performed as follows.

The inverter circuit IV applies the ground potential VSS of the circuit, for example, 0 V to the ground line GL at the time of writing and reading information through the MISFET QS2 which is turned on by the high level of the signal φ￣E, and the low level of the signal φ￣E. Then, an erase potential VPP, for example, 12 V is applied at the time of erasing information through the MISFET QS1 which is turned on. When erasing information, for example, 12 V is applied to VPP of the inverter circuit IV, and all the word lines WL and all data lines DL are connected to the circuit X-DEC receiving the signal φ 信号 E in a state where the ground line GL is set to 12 V. It is set to low level by Y-DEC. That is, in this embodiment, the contents of all the memory cells Qm are erased at once.

In the write operation, the power supply potential VCC (for example, 5 V) is supplied from the write circuit DIB to one data line DL selected by the Y-DEC. Prior to this, all the data lines DL are precharged to the circuit ground potential VSS (for example, 0 V) by the drive circuit DR in advance. In the read operation, all data lines DL
It is precharged to the power supply potential VCC in advance by the drive circuit DR. Thereafter, the potential according to the storage of the selected one memory cell Qm appears on the data line DL.

In a write operation, the power supply voltage VCC is supplied from the decoder X-DEC to one selected word line WL.
The above high voltage VPP (for example, 12 V) is supplied. In the read operation, the selected one word line WL is
A high level signal of the power supply voltage VCC (or lower) is applied from the decoder X-DEC. When the threshold value of the MISFET of the memory cell Qm is lower than the selection level of the word line WL, the potential of the data line DL is reduced from the potential VCC by turning on the MISFET Qm. MISFETQ
When the threshold value of m is higher than the selection level of the word line WL, the data line DL maintains the precharge level by turning off the MISFET Qm.

The writing operation, that is, the injection of hot carriers, is performed only in one memory cell in which the potential VPP is applied to the word line WL and the potential VCC is applied to the data line DL. In other memory cells, hot carriers are not injected.

The high voltage VPP may be supplied from an external terminal during a write operation, or may be generated from the power supply voltage VCC by a built-in booster circuit.

FIG. 3 shows an EE according to a first embodiment of the present invention.
FIG. 3 is a cross-sectional view of P-channel and N-channel MISFETs constituting a memory cell and a peripheral circuit of the PROM, and a memory cell portion is a cross-sectional view along AA in FIG.

As shown in FIG. 3, the EEPROM includes a p-type semiconductor substrate 1 made of single crystal silicon. Flash nonvolatile memory cell Qm and N channel M
In the formation region of the ISFET Qn, a p-type well region 3 is provided on the main surface of the semiconductor substrate 1, and in the formation region of the P-channel MISFET Qp, an n-type well region 2 is provided.

An element isolation insulating film 4 is provided on the main surfaces of the n-type well region 2 and the p-type well region 3 between the element formation regions. On the main surface of the p-type well region 3, a p-type channel stopper region 5 is provided below the element isolation insulating film 4.

The flash type nonvolatile memory element Qm is
It is formed on the main surface of the p-type well region 3 in a region defined by the element isolation insulating film 4 and the channel stopper region 5. That is, the flash nonvolatile memory element Qm includes the p-type well region 3, the first gate insulating film 6, the floating gate electrode 7, the second gate insulating film 8, the control gate electrode 9, the source region and the drain region. I have. This flash type nonvolatile memory element Qm is configured by an n-channel field effect transistor, and is configured by one element type.

The p-type well region 3 is used as a channel forming region.

The first gate insulating film 6 is formed of a silicon oxide film formed by oxidizing the surface of the p-type well region 3.
The first gate insulating film 6 is formed with a thickness of, for example, about 100 to 150 [Å].

The floating gate electrode 7 is formed of, for example, a polycrystalline silicon film into which an n-type impurity has been introduced.

The second gate insulating film 8 is formed of, for example, a silicon oxide film obtained by oxidizing the surface of the floating gate electrode 7 (polycrystalline silicon film). The second gate insulating film 8 is formed to a thickness of, for example, about 200 to 250 [Å].

The control gate electrode 9 is formed of, for example, a polycrystalline silicon film into which an n-type impurity has been introduced. The control gate electrode 9 is made of W, Ta, Ti, M
It may be formed of a single layer of a high melting point metal film such as O or a high melting point metal silicide film, or a composite film in which these metal films are stacked on a polycrystalline silicon film, that is, a polycide. The control gate electrode 9 is integrally formed with the control gate electrode 9 of another flash type nonvolatile memory element Qm arranged adjacently in the gate width direction, and forms a word line (WL).

The source region is composed of an n + type semiconductor region 11 having a high impurity concentration and an n type semiconductor region 12 having a low impurity concentration. The n-type semiconductor region 12 is the n + type semiconductor region 1
1 is provided along the outer periphery. That is, the source region has a so-called double diffusion structure. The n + type semiconductor region 11 having a high impurity concentration is mainly configured to increase the impurity concentration and increase the junction depth. The n-type semiconductor region 12 having a low impurity concentration is mainly configured to increase the junction depth. That is, when a high voltage is applied between the source region and the control gate electrode 9 during the information erasing operation, the impurity concentration in the n + type semiconductor region 11 is increased so that the surface is not depleted. Further, the source region increases the amount of diffusion (diffusion distance) to the channel formation region side by the high impurity concentration n + type semiconductor region 11 or the low impurity concentration n-type semiconductor region 12 or both, so that the floating gate electrode 7 , The overlap area (overlap amount) is increased, and the tunnel area during the information erasing operation is increased. Each of the semiconductor regions 11 and 12 is formed in self-alignment with the gate electrodes 7 and 9.

The drain region comprises a high impurity concentration n + type semiconductor region 14. This n + type semiconductor region 14 is formed in self-alignment with the floating gate electrode 7 and the control gate electrode 9.

A high impurity concentration p-type semiconductor region 13 is provided on the main surface of the semiconductor substrate 1 along the outer periphery of the drain region. The p-type semiconductor region 13 is configured to increase the electric field strength near the drain region, particularly to promote the generation of hot electrons in the selected flash type nonvolatile memory element Qm during the information writing operation, and to improve the information writing efficiency. Have been.

The peripheral circuit is an N-channel MISFET Q
CM in which n and P channel MISFETQp are connected in series
It is composed of an OS circuit. N-channel MISFET
The Qn and P-channel MISFETs Qp have low impurity concentration regions 15 (n) and 16 (p) and high impurity concentration regions 18 (p), respectively.
(n +), it has a LDD (L ightly- D oped- D rain ) structure having a source-drain region consisting of 19 (p +). The low impurity concentration regions 15 (n) and 16 (p) are formed in self-alignment with the respective gate electrodes 9, and the high impurity concentration regions 18 (n +) and 19 (p +) correspond to the respective gate electrodes 9. And sidewalls 17 provided at both ends thereof in a self-aligned manner. Furthermore, these N
Channel MISFET Qn, P channel MISFE
The gate electrode 9 of TQp is formed in the same layer as the control gate electrode 9 of the flash nonvolatile memory cell Qm.

This flash type nonvolatile memory cell Qm
A wiring 23 made of an aluminum alloy film is connected to the n + type semiconductor region 14 which is a drain region of the semiconductor device, and the wiring 23 functions as a data line DL.

Further, the source and source of N-channel and P-channel MISFETs SQn and Qp constituting the peripheral circuit
The wiring 23 is also connected to the drain region as needed. The wiring 23 extends on the interlayer insulating films 20 and 21 and is connected to the p + type and n + type semiconductor regions through the connection holes 22 formed in the interlayer insulating films 20 and 21.

FIG. 4 is an enlarged view of the flash nonvolatile memory cell Qm shown in FIG. Although not clearly shown in FIG. 3, the lower corners 7E of both ends of the floating gate electrode 7 are rounded. As described above, by forming the corner portion 7E of the floating gate electrode 7 into a rounded structure, electric field concentration at the corner portion can be prevented, and dielectric breakdown of the insulating film at the edge portion of the floating gate electrode 7 can be prevented. , The number of times of erasing and writing of the EEPROM can be increased.

A method for rounding the corner 7E will be described later.

Next, a method of manufacturing the EEPROM will be briefly described with reference to FIGS. 5 to 19 (cross-sectional views schematically showing respective manufacturing steps).

First, a p− type semiconductor substrate 1 is prepared.

Next, in the formation region of the p-channel MISFET Qp, an n-type well region 2 is formed on the main surface of the semiconductor substrate 1. The n-type well region 2 is, for example, 1 × 10
Impurities of about 13 to 3 × 10 13 [atoms / cm 2], for example, p
+ Is formed by ion implantation at an energy of 100 to 150 KeV. Thereafter, in each of the formation regions of the flash nonvolatile memory element Qm and the n-channel MISFET Qn, a region other than the region for forming the n-type well region 2 on the main surface of the semiconductor substrate 1 is, for example, 5 × 10 12 to 1 × 1.
Impurities of about 013 [atoms / cm2], for example, BF2 +
The p-type well region 3 is formed by ion implantation at an energy of 0 to 70 KeV.

Next, on the main surfaces of the n-type well region 2 and the p-type well region 3, a device isolation insulating film 4 of about 6000 to 8000 ° is formed, and a p-type well region 3 is formed with a p-type well. A mold channel stopper region 5 is formed.

Next, as shown in FIG. 5, a first gate insulating film 6 of about 100 to 150 ° is formed on each of the main surfaces of the n-type well region 2 and the p-type well region 3 in the semiconductor element formation region. I do.

Next, a conductive film 7A is formed on the entire surface of the substrate including the first gate insulating film 6 to a thickness of about 2000 to 3000 °. The conductive film 7A is formed of, for example, a polycrystalline silicon film deposited by a CVD method. An n-type impurity such as P is introduced into the polycrystalline silicon film to reduce the resistance. Thereafter, as shown in FIG. 6, the conductive film 7A is patterned into a predetermined shape. The conductive film 7A remains only in the formation region of the flash nonvolatile memory cell Qm, and the size of the conductive film 7A in the channel width direction is defined.

Next, the flash type nonvolatile memory cell Q
In the formation region of m, the second gate insulating film 8 is formed on the surface of the conductive type 7A at a thickness of about 200 to 250 °. An n-channel MISFET is manufactured by substantially the same manufacturing process as this process.
P-type well region 3 for forming Qn, p-channel MI
A second gate insulating film 8 is formed on each main surface of the n-type well region 2 in the formation region of the SFET Qp. After this, FIG.
As shown in FIG. 7, a conductive film 9A is formed on the entire surface of the substrate including the second gate insulating film 8 by about 1000 to 1500 °. The conductive film 9A is formed of, for example, a polycrystalline silicon film deposited by a CVD method. An n-type impurity such as P is introduced into the polycrystalline silicon film to reduce the resistance.

Next, the flash type nonvolatile memory cell Q
In the formation region of m, each of the conductive films 9A and 7A is sequentially patterned to form the control gate electrode 9 and the floating gate electrode 7. This patterning is performed by a so-called overlap cutting technique using anisotropic etching such as RIE. Thereafter, patterning is performed on the conductive film 9A in the formation region of the peripheral circuit element to form the control gate electrode 9. Here, this control gate electrode 9
Are formed integrally with the word line WL, so that Ta, Ti,
It may be formed of a high melting point metal such as W or Mo, a single layer of these high melting point metal silicide films, or a polycide film in which a high melting point metal silicide film is laminated on a polycrystalline silicon film. Thereafter, an oxidation process is performed on the front surface of the substrate to form an insulating film 1 covering the respective surfaces of the gate electrodes 7 and 9 as shown in FIG.
0 is formed on a semiconductor substrate at about 70 to 80 °.

Next, the flash type nonvolatile memory cell Q
An impurity introduction mask 30 having an opening in a region where a source region of m is formed is formed. The impurity introduction mask 30 is formed of, for example, a photoresist film. Thereafter, as shown in FIG. 9, an n-type impurity 12n is introduced into the main surface of the p-type well region 3 serving as a source region formation region using the impurity introduction mask 30. The n-type impurity 12n is, for example, 1 × 1
P having an impurity concentration of about 014 to 1 × 10 15 [atoms / cm 2]
It is introduced by ion implantation using ions at an energy of about 50 [KeV]. This n-type impurity 12n is introduced into the floating gate electrode 7 and the control gate electrode 9 in a self-aligned manner.

Then, the impurity introduction mask 30 is removed.

Next, the flash type nonvolatile memory cell Q
An impurity introduction mask 31 having an opening in the region where the m drain region is formed is formed. The impurity introduction mask 31 is formed of, for example, a photoresist film. Thereafter, as shown in FIG. 10, a p-type impurity 13p is introduced into the main surface portion of the p-type well region 3 serving as a drain region using the impurity introduction mask 31. The p-type impurity 13p is, for example, BF2 ion having an impurity concentration of about 5 * 10 <13> to 1.5 * 10 <14> atoms / cm <2>, and is introduced by an ion implantation method with an energy of about 60 [KeV]. p-type impurity 13
p is introduced in a self-aligned manner with respect to the floating gate electrode 7 and the control gate electrode 9. And
The impurity introduction mask 31 is removed.

Next, in a nitrogen gas atmosphere, about 1000
[° C.] heat treatment, and the introduced n-type impurity 12
Each of the n and p type impurities 13p is stretched and diffused.
By the diffusion of the n-type impurity 12n, the n-type semiconductor region 1 is formed.
2 can be formed. The n-type semiconductor region 12 is formed with a deep junction depth of about 0.5 [μm].

By the diffusion of the p-type impurity 13p, the p-type semiconductor region 13 having a low impurity concentration can be formed. The p-type semiconductor region 13 is formed with a deep junction depth of about 0.3 to 0.5 [μm].

Next, the flash type nonvolatile memory element Q
An impurity introduction mask 32 having an opening in a region where m is formed is formed. The impurity introduction mask 32 is formed of, for example, a photoresist film. Thereafter, as shown in FIG. 11, using the impurity introduction mask 32 in which the formation region of the source region of the flash nonvolatile memory cell Qm is opened, the main surface of the p-type well 3 serving as the formation region of the source region is formed. An n + type impurity 11n + is introduced. The n + type impurity 11n + is introduced by ion implantation at an energy of about 60 KeV using, for example, As ions of 5 × 10 15 to 1 × 10 16 atoms / cm 2. The n + type impurity 11n + is introduced into the floating gate electrode 7 and the control gate electrode 9 in a self-aligned manner. Then, the impurity introduction mask 32
Is removed.

Next, as shown in FIG. 12, the p-type well 3 serving as a drain region forming region is formed using an impurity introduction mask 33 having an opening formed in the drain region forming region of the flash type nonvolatile memory cell Qm. N + type impurity 1 on the surface
4n + is introduced. The n + type impurity 14n + is, for example, 1
6 × 10 15 to 5 × 10 15 atoms / cm 2 of As ions
It is introduced by an ion implantation method at an energy of about 0 KeV. The n + type impurity 14n + is introduced into the floating gate electrode 7 and the control gate electrode 9 in a self-aligned manner.

Here, n + type impurities 11n +, 14n +
Has been described in a separate step, but when the n + type impurities 11n + and 14n + have the same impurity concentration, they may be introduced simultaneously.

Next, a heat treatment is performed at about 1000 ° C. in a nitrogen gas atmosphere to introduce the n + -type impurities 11n +,
Stretch and diffuse each of the 14n +. By this heat treatment, the n-type impurity regions 11 (n +) and 14 (n +) have a junction depth of about 0.3 μm.

Next, as shown in FIG.
Using an impurity introduction mask 34 having an opening in an ISFET Qn formation region, an n-type impurity 15n is
ETQn is introduced into the main surface of the p-type well 3 at both ends of the gate electrode 9 in a self-aligned manner with respect to the gate electrode 9. This n-type impurity 15n has, for example, 1 × 10 13 to 5 × 10 13 atoms.
p ions of / cm @ 2 are implanted at an energy of about 50 KeV and introduced.

Next, as shown in FIG.
Using the impurity introduction mask 35 having an opening in the ISFET Qp formation region, the p-type
TQp is introduced into the main surface of the N-type well 2 at both ends of the gate electrode 9 in a self-aligned manner with respect to the gate electrode 9. This p-type impurity 16p is, for example, 5 × 10 12 to 1 × 10 13 atoms / cm.
2 BF2 ions are implanted at an energy of about 60 KeV and introduced.

Next, as shown in FIG.
0 is removed by wet etching. This etching solution is, for example, a mixed solution of hydrofluoric acid and water, and the mixing ratio is 1:99. By this step, the insulating film on the surface of the source / drain region of the flash type nonvolatile memory cell Qm, on which the dangling bond is formed by ion implantation of As ions of n + type impurities 11n + 14n +, is removed.

Next, as shown in FIG. 16, a new insulating film 10 ', such as an oxide film, is oxidized in a furnace at a temperature of about 900.degree. A film of about 400-500 ° is formed on the surface of the source / drain region of cell Qm. At this time, an insulating film having substantially the same thickness is formed on the surfaces of the floating gate electrode 7 and the control electrode 9.

By this oxidation step, the corners at both ends of the floating gate electrode 7 of the flash nonvolatile memory cell Qm are rounded as shown in FIG.

Further, the MISFET Q
The n-type impurity 15n and the p-type impurity 16p of n and Qp are extended and diffused, and both have a junction depth of about 0.1 to 0.2 μm.

Next, as shown in FIG. 17, sidewall spacers 17 are formed on the respective side walls of each of the gate electrodes 7 and 9. The side wall spacers 17 can be formed by depositing a silicon oxide film on the entire surface of the substrate by a CVD method and performing anisotropic etching such as RIE on the entire surface of the substrate by an amount corresponding to the deposited film thickness.

Next, since the main surfaces of the n-type well region 2, the p-type well region 3 and the like are exposed by the anisotropic etching, an oxidation treatment is performed, and the surfaces are covered with a thin silicon oxide film.

Further, as shown in FIG. 18, an impurity introduction mask having an opening in the N-channel MISFET Qn is formed, and an n + -type impurity is introduced into the gate electrode 9 and the side wall 17 in a self-aligned manner. The n + -type impurity is, for example, As ions having a high impurity concentration of about 5 × 10 15 [atoms / cm 2], and is introduced by ion implantation at an energy of about 60 [KeV].

Next, an impurity introduction mask having an opening in the formation region of the p-channel MISFET Qp is formed. Then, a p-type impurity 19p + is introduced into the main surface of the p-type semiconductor region 16 using the impurity introduction mask. The p
For example, BF2 ions having a high impurity concentration of about 2.times.10@15 [atoms / cm @ 2] are introduced by ion implantation at an energy of about 60 KeV. The p +
Type semiconductor region 19 includes gate electrode 9 and sidewall 1
7 is formed in a self-aligned manner.

Further, thereafter, annealing at about 850 ° C. is performed to thereby obtain n + type impurities 18n as shown in FIG.
+, P-type impurities 19p + are stretched and diffused to 0.2 to 0.2.
N + type semiconductor region 18 having a junction depth of about 3 μm
(N +), p + type semiconductor region 19 (p +) is formed.

Next, interlayer insulating films 20 and 21 are formed on the entire surface of the substrate. The interlayer insulating film 20 is an oxide film having a thickness of about 1500 ° formed by thermal decomposition of organic silane.
1 is, for example, a thickness of 5000 to 600 formed by a CVD method.
0 ° BPSG film. And the interlayer insulating film 2
After forming connection holes 22 at 0 and 21 and applying a glass flow to the interlayer insulating film 21, wirings 23 are formed as shown in FIG. By performing these series of manufacturing processes,
The EEPROM of this embodiment is completed. Although not shown, a passivation film is provided on the wiring 23.

In this embodiment, as described with reference to FIGS. 15 and 16, the insulating film is removed and then oxidized to form an insulating film again. However, the insulating film does not necessarily need to be removed by etching. Just do it. It is considered that the reason is that oxygen is supplied to the dangling bonds generated by the ion implantation by the oxidation treatment, and the dangling bonds disappear or decrease.

Furthermore, even if oxidation is performed after removing part of the insulating film, the leakage current can be similarly prevented or suppressed.

FIG. 20 shows a schematic structure of a flash type nonvolatile memory cell according to the second embodiment of the present invention.

The difference from the first embodiment will be described. In the flash type nonvolatile memory cell according to the second embodiment shown in FIG. 11, the source region 11 under the end of the floating gate electrode 7 is formed. By selectively forming the low-concentration region 24 near the surface, an electric-field buffering means is formed to alleviate an electric field generated between the source region 11 and the end of the floating gate electrode 7 when an erase voltage is applied.

That is, the electric field is reduced by making the depletion layer easily extend on the surface of the source region 11 below the end of the floating gate electrode 7.

This low-concentration region 24 partially reduces the doping amount of the conductivity-imparting impurity in source region 11 or, as shown in FIG. It is formed by selective ion implantation at a depth of about 0.15 μm.

When the low concentration region 24 as described above is provided,
Due to the applied electric field at the time of erasing, a large depletion layer spreads partially in the low concentration region 24 below the end of the floating gate electrode 7. Due to the expansion of the depletion layer, the tendency of the electric field to concentrate near the end of the floating gate electrode 7 is corrected.

Thus, as in the case of the first embodiment described above, with a structure obtained by a relatively simple manufacturing process, it is possible to reduce the variation in the erasing characteristics between the storage elements and to enable repeated rewriting. The number of times can be increased.

FIG. 22 shows a third embodiment of the present invention.
The first embodiment is different from the first embodiment in that the flash type nonvolatile memory cell Q
The structure of m is different. The structure and manufacturing method of the peripheral circuit are the same.

Therefore, portions corresponding to the respective portions of the first embodiment are denoted by the same reference numerals.

The flash type non-volatile memory cell shown in the figure is a MISFET similar to the first embodiment, and has a floating gate electrode 7 provided on the semiconductor substrate 1 with a first gate insulating film 6 interposed therebetween. A control gate electrode 9 provided on the floating gate electrode 7 with a second gate insulating film 8 interposed therebetween, and separated from each other below the floating gate electrode 7 and partially overlapping the floating gate electrode 7. Are formed by the source regions 11 and 12 and the drain region 14 and the like.

Here, a side wall spacer 17 is provided on the side of the control gate electrode 9. The floating gate electrode 7 is formed with reference to the end of the sidewall spacer 17. Thus, the side portion of the control gate electrode 9 is formed to be recessed from the side portion of the floating gate electrode 7.

As described above, the side portion of the control gate electrode 9 is formed to be recessed inside the side portion of the floating gate electrode 7 and the source regions 11 and 12 are formed.
And the tip of the drain region 14 reach below the side of the control gate electrode 9, so that a relatively large overlapping portion between the source region 11, 12 and the drain region 14 and the floating gate electrode 7. It is formed with good reproducibility and good controllability.

In this case, the dimensions of the floating gate electrode 7 are smaller than the dimensions of the control gate electrode 9 by one side edge by the side wall spacers 17.
It is set to be as large as about 2 to 0.3 μm.

The flash type nonvolatile memory cell Q
The thickness of each layer m is the same as in the first embodiment.

In the nonvolatile memory element configured as described above, first, the overlapping area between the source region 61 and the drain region 62 and the floating gate electrode 3 is ensured. The stable tunnel current can be secured by avoiding the influence of the shape and the like of the side portion of No. 3. As a result, variations in the erasing characteristics can be reduced. At the same time, the concentration of the electric field at the end is reduced, so that the erasing voltage can be increased and the erasing speed can be increased.

Next, an embodiment of a method for manufacturing the above-mentioned nonvolatile memory element will be described.

A method of manufacturing the flash nonvolatile memory cell shown in FIG. 22 will be described with reference to FIGS.

A conductive film 9A of a polycrystalline silicon film is formed on a semiconductor substrate as in FIG. 7 of the first embodiment.

Next, as shown in FIG. 24, the conductive film 9 is formed in the formation region of the flash type nonvolatile memory cell Qm.
The conductive film 9A in the N-channel and P-channel MISFETs forming regions forming the A and peripheral circuits is patterned to form a control gate electrode and gate electrodes of the N-channel and P-channel MISFETs.

Next, the surface is oxidized to form an insulating film 10.

Next, the steps from FIG. 25 to FIG.
Since this embodiment corresponds to FIGS. 9 to 12 of the embodiment, the description is omitted. However, each ion implantation is performed through the polycrystalline silicon film for forming the floating gate electrode in a self-aligned manner with respect to the control gate electrode 9. Therefore, the energy of the ion implantation must be higher than that of the first embodiment.

For example, the n-type impurity 12n has p + of 150
About KeV, p-type impurity 13p is about 50 KeV for B +, and n + -type impurities 11n + and 14n + are about 250 for As +.
Energy of about KeV is formed by ion implantation.
Thereafter, n is set in the same manner as in FIGS. 15 and 16 of the first embodiment.
Type and p-type impurities 15n and 16p are ion-implanted.

Next, as shown in FIG. 29, similarly to FIG. 17 of the first embodiment, the control gate electrode 9 and the N-channel
A sidewall 17 is formed on the side of the gate electrode 9 of the channel MISFET.

Next, as shown in FIG. 30, the floating gate electrode 7 is processed in a self-aligned manner with respect to the control gate electrode 9 and the side wall 17 described above.

Thereafter, the EEPROM of the present embodiment is completed by a process similar to that of FIG. 17 and thereafter of the first embodiment.

FIG. 31 shows a modification of the third embodiment, in which the floating gate electrode 7 and the control gate electrode 9 are asymmetric on the source region 11, 12 side and the drain region 14 side. ing. In this case, the side of the floating gate electrode 7 closer to the source regions 11 and 12 is 0.2 to 0.3 than the control gate electrode 9 by the sidewall spacers 17 as in the above-described embodiment.
It is formed to protrude sideways by μm. However, on the drain region 14 side, the respective ends of the floating gate electrode 7 and the control gate electrode 9 are aligned at substantially the same position.

With such an asymmetric structure, the overlap between the source regions 11 and 12 and the floating gate electrode 7 can be increased to improve the erasing characteristics, while the overlap between the drain region 14 and the floating gate electrode 7 can be reduced. At the same time, it is possible to improve the write characteristics by reducing the size.

The embodiment in which the invention made by the present inventor is applied to a flash EEPROM has been described. However, the invention can also be applied to an EEPROM other than the flash EEPROM or a microcomputer having the built-in EEPROM.

For example, in FIG. 32, reference numeral 25 denotes a semiconductor substrate (chip) made of P-type single crystal silicon, and a plurality of bonding pads 26 are arranged around the semiconductor substrate (chip).
I / O circuit area I / O inside bonding pad 26
Is provided. Microcomputer chip 2 shown in FIG.
5, a μ (micro) ROM, CPU (central processing unit), SCI (serial communication interface), A / D (analog-digital conversion) circuit, dual-RAM (dual port random access memory)
ry), RAM, ROM, timer 1, timer 2, timer 3
Each has a built-in.

The present invention can be applied to the μROM, the ROM section, and the ROM section.

[0111]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) By rounding the lower corner of the end of the floating gate electrode, it is possible to prevent the electric field from concentrating at the corner, and it is possible to prevent the gate insulating film at the end of the floating gate electrode from being broken or damaged. Since deterioration can be prevented, the number of times of rewriting can be increased.

(2) By rounding the lower corner of the end of the floating gate electrode, the electric field concentration at the corner can be prevented, and the electric field at the time of erasing is almost uniformly applied to the gate insulating film. Variations in the erasing characteristics can be prevented. Further, even if the shape of the end of the floating gate electrode varies, the tunneling at the time of erasing occurs on the channel side rather than the end, so that it is possible to prevent the variation in erase characteristics between bits.

(3) The leakage current between the floating gate electrode and the source region is obtained by removing the oxide film on the surface after ion implantation of high-concentration As ions for forming the source region and then replacing the oxide film. Therefore, it is possible to prevent variations in the erasing characteristics. By performing the oxidation treatment after the above-described ion implantation, dangling bonds in the oxide film can be reduced, and the leak current can be prevented or reduced.

(4) Since the overlap between the source region and the floating gate electrode can be reliably obtained, variations in the erasing characteristics can be eliminated.

(5) Since the concentration of the conductivity-imparting substance in the source region under the floating gate electrode can be increased with good controllability, an inversion layer is formed on the surface of the semiconductor substrate or a depletion layer spreads during the erasing operation. The influence is reduced and the tunneling current is increased by applying the erasing electric field only through the gate insulating film, whereby the erasing characteristics, particularly the erasing speed, can be increased.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a part of a memory cell array portion and peripheral circuits of an EEPROM of the present invention.

FIG. 2 is a plan view of a main part of a memory cell array unit.

FIG. 3 is a sectional view of N-channel and P-channel MISFETs for a memory cell and a peripheral circuit.

FIG. 4 is an enlarged view of a gate portion of a memory cell.

FIG. 5 is a sectional view showing a manufacturing process of the EEPROM.

FIG. 6 is a sectional view showing a manufacturing process of the EEPROM.

FIG. 7 is a sectional view showing a manufacturing process of the EEPROM.

FIG. 8 is a sectional view showing a manufacturing process of the EEPROM.

FIG. 9 is a sectional view showing a manufacturing process of the EEPROM.

FIG. 10 is a sectional view showing a manufacturing process of the EEPROM.

FIG. 11 is a sectional view showing a manufacturing process of the EEPROM.

FIG. 12 is a sectional view showing a manufacturing process of the EEPROM.

FIG. 13 is a sectional view showing a manufacturing process of the EEPROM.

FIG. 14 is a cross-sectional view showing a manufacturing process of the EEPROM.

FIG. 15 is a sectional view showing a manufacturing process of the EEPROM.

FIG. 16 is a sectional view showing a manufacturing process of the EEPROM.

FIG. 17 is a sectional view showing a manufacturing process of the EEPROM.

FIG. 18 is a sectional view showing a manufacturing process of the EEPROM.

FIG. 19 is a sectional view showing a manufacturing process of the EEPROM.

FIG. 20 is a sectional view showing a second embodiment of the present invention.

FIG. 21 is a sectional view showing a second embodiment of the present invention.

FIG. 22 is a sectional view showing a third embodiment of the present invention.

FIG. 23 is a sectional view showing the manufacturing process of the EEPROM of the third embodiment.

FIG. 24 is a sectional view showing the manufacturing process of the EEPROM of the third embodiment.

FIG. 25 is a sectional view showing the manufacturing process of the EEPROM of the third embodiment.

FIG. 26 is a sectional view showing the manufacturing process of the EEPROM of the third embodiment.

FIG. 27 is a sectional view showing the manufacturing process of the EEPROM of the third embodiment.

FIG. 28 is a sectional view showing the manufacturing process of the EEPROM of the third embodiment;

FIG. 29 is a sectional view showing the manufacturing process of the EEPROM of the third embodiment.

FIG. 30 is a sectional view showing the manufacturing process of the EEPROM of the third embodiment;

FIG. 31 is a sectional view showing a modification of the third embodiment.

FIG. 32 is a layout diagram of a microcomputer chip to which the EEPROM of the present invention is applied.

[Description of Signs] Qm: memory cell, Qp, Qn: MISFE for peripheral circuit
T, 1 ... semiconductor substrate, 4 ... insulating insulating film, 6 ... first
Gate insulating film, 7 floating gate electrode, 8 second gate insulating film, 9 control gate electrode (memory cell portion), gate electrode (peripheral circuit portion), 11, 12 source region (memory cell), 14 Drain region (memory cell), 17 ... sidewall, 20, 21 ... interlayer insulating film, 23 ... wiring, 15, 18 ... source / drain region of N-channel MISFET for peripheral circuit, 16, 19 ... p-channel MISFET for peripheral circuit 24, low-concentration regions.

 ──────────────────────────────────────────────────続 き Continued on front page (72) Inventor Hitoshi Kume 5-20-1, Kamizuhoncho, Kodaira-shi, Tokyo Inside Musashi Plant of Hitachi, Ltd. (72) Inventor Hideaki Yamamoto 1-280 Higashi-Koigabo, Kokubunji-shi, Tokyo Address: Central Research Laboratory, Hitachi, Ltd.

Claims (2)

[Claims] 1. A semiconductor integrated circuit device having a MISFET type nonvolatile memory cell for erasing information from a source region by utilizing a tunnel phenomenon to a first insulating film. (1) a floating gate electrode provided via an insulating film; (2) a control gate electrode provided on the floating gate electrode via a second insulating film; The semiconductor device has first and second n-type semiconductor regions serving as source and drain regions of the MISFET provided at both ends of the gate electrode, and the floating gate electrode has a shape for alleviating electric field concentration at a corner. A semiconductor integrated circuit device. 2. A semiconductor integrated circuit device having a MISFET type nonvolatile memory cell for erasing information from a source region by utilizing a tunnel phenomenon to a first insulating film. (1) a floating gate electrode provided via an insulating film; (2) a control gate electrode provided on the floating gate electrode via a second insulating film; The semiconductor device includes first and second n-type semiconductor regions provided as source and drain regions of the MISFET provided at both ends of the gate electrode, and the floating gate electrode includes the MISFE.
In the channel direction of T, the first semiconductor region of the source region, which is larger than the control gate electrode,
A semiconductor integrated circuit device overlapping the control gate electrode in a channel direction of an FET.