JPH1197559A - Ferroelectric memory cell, method for driving the same and memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ferroelectric memory cell which can be suitably made in a high integration. SOLUTION: A gate laminated structure is formed on a region of a part of a substrate having a semiconductor surface layer. The gate laminated structure is made to a gate insulating film, a floating gage conductive film 5, a ferroelectric film 6 and a control gate electrode 7, and all the layers are laminated sequentially in the order described above from a side of the substrate. Two impurity diffusion regions are provided at both side of the gate laminated structure of the semiconductor surface layer of the substrate. A vertically projected image of the floating gate conductive film 5 toward the substrate surface is partly overlapped with one impurity diffusion region. Assuming that CFD is a capacitance between the floating gate conductive film 5 and one impurity diffusion region, Cf is a capacitance of the ferroelectric film. Then, a coupling ratio CFD/(CFD+Cf ) becomes 0.2 or more.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory cell and a memory device, and more particularly, to a metal-ferroelectric-metal.
The present invention relates to a ferroelectric memory cell having an insulator-semiconductor (MFMIS) structure and a memory device.

[0002]

2. Description of the Related Art The structure and operating principle of a conventional MFMIS structure ferroelectric memory cell will be described with reference to FIG.

FIG. 5A is a cross-sectional view of a conventional MFMIS structure ferroelectric memory cell. A channel region 101 is defined in a surface layer of a grounded p-type silicon substrate 101, and an n ⁺ -type source region 102S and a drain region 102D are formed on both sides thereof. A gate insulating film 103, a floating gate conductive film 104, a ferroelectric film 105, and a control gate electrode 106 are stacked on the channel region 101.

[0004] One bit of information can be stored by this one transistor. Hereinafter, the writing process will be described. The control gate electrode 106 has a ferroelectric film 10
5. Apply a positive voltage sufficient to reverse the polarization of 5 and then return to ground potential. At this time, downward residual polarization occurs in the ferroelectric film 105. Due to the remanent polarization, negative charges are induced on the surface of the silicon substrate 100, and an inversion layer is formed in the channel region 101. Thus, the transistor is turned on.

As shown in FIG. 5B, a negative voltage sufficient to invert the polarization of the ferroelectric film 105 is applied to the control gate electrode 106, and thereafter, is returned to the ground potential. At this time, upward remanent polarization occurs in the ferroelectric film 105, and the inversion layer formed in the channel region 101 disappears. Thus, the transistor is turned off.

As described above, while the ground potential is being applied to the control gate electrode 106, the transistor can be held in either the conductive state or the non-conductive state.
By associating the conductive state and the non-conductive state with 1 and 0, one-bit information can be stored. By applying a voltage between the source and the drain of the transistor and detecting the conduction state, stored information can be read.

FIG. 6 shows an example of an equivalent circuit diagram of a ferroelectric memory device in which transistors of the MFMIS structure are arranged in a matrix. One memory cell is formed by one transistor having the MFMIS structure. FIG.
This shows a case in which they are arranged in two rows and two columns.

The control gates of the transistors on the first and second rows are
The gate electrodes are respectively connected to the word lines WL ₁And WL_TwoConnect to
Have been. Sources of transistors in first and second rows
The region is the source line SL₁And SL_TwoConnected to
ing. Drain area of transistors in first and second columns
Area is bit line BL₁And BL_TwoConnected to
I have. The channel region of each transistor is
In area.

Each word line is connected to a word line control circuit 110, each bit line is connected to a bit line control circuit 111 and a detection circuit 112, and each source line is connected to a source line control circuit 113. . Word line control circuit 11
0, bit line control circuit 111, and source line control circuit 1
Reference numeral 13 can selectively apply a voltage to one word line, one bit line, and one source line, respectively. The detection circuit 112 can select one bit line and detect an electric signal appearing on the bit line.

At the time of writing, a sufficient voltage is applied between a word line and a bit line corresponding to a memory cell to be written, and the ferroelectric film of the memory cell is brought into a desired polarization state. At the time of reading, a conduction state between a source line and a bit line corresponding to a memory cell to be read is detected.

[0011]

In the ferroelectric memory device shown in FIG. 6, a voltage is applied to a channel region of a memory cell in a specific column by selecting a bit line. Therefore, it is necessary to electrically separate the channel regions of the memory cells from each other for each column. Since it is necessary to adopt this separation structure, it is difficult to highly integrate the memory device.

An object of the present invention is to provide a ferroelectric memory cell suitable for high integration.

Another object of the present invention is to provide a ferroelectric memory device suitable for high integration.

[0014]

According to one aspect of the present invention, a substrate having a semiconductor surface layer and a gate insulating film and a floating film formed on a part of the semiconductor surface layer of the substrate in this order from the substrate side A gate stacked structure in which a gate conductive film, a ferroelectric film, and a control gate electrode are stacked; and two impurity diffusion regions formed in regions on both sides of the gate stacked structure in the semiconductor surface layer of the substrate. A vertical projection image of the floating gate conductive film on the substrate surface and two impurity diffusion regions arranged so that one impurity diffusion region partially overlaps with each other; The capacitance between the one impurity diffusion region and _CFD , the capacitance of the ferroelectric film, that is, the control gate electrode and the floating gate conductive film When the capacitance between is C _f
The ferroelectric film, the gate insulating film, the floating gate conductive film, and the one impurity diffusion region are configured so that a coupling ratio C _FD / (C _FD + C _f ) becomes 0.2 or more. A ferroelectric memory cell is provided.

According to another aspect of the present invention, a substrate having a semiconductor surface layer and a gate insulating film, a floating gate conductive film, and a gate insulating film formed on a partial region of the semiconductor surface layer of the substrate in this order from the substrate side. A gate stack structure in which a dielectric film and a control gate electrode are stacked; and two impurity diffusion regions formed in both sides of the gate stack structure in a semiconductor surface layer of the substrate, wherein the floating gate The control gate electrode and the ferroelectric memory cell each having two impurity diffusion regions arranged so that a vertical projection image of the conductive film on the substrate surface and one impurity diffusion region partially overlap each other. A method of driving a ferroelectric memory cell in which a writing process is performed by applying a voltage between one of the impurity diffusion regions and generating remanent polarization in the ferroelectric film. It is provided.

Since the vertical projection image of the floating gate conductive film on the substrate surface and the one impurity diffusion region partially overlap each other, a voltage applied between the control gate electrode and the one impurity diffusion region is applied. Among them, the voltage applied to the ferroelectric film between the floating gate conductive film and the control gate electrode can be increased.
Therefore, a voltage higher than the coercive voltage can be applied to the ferroelectric film at a relatively low voltage.

By adopting a structure in which the coupling ratio C _FD / (C _FD + C _f ) becomes 0.2 or more, a voltage can be efficiently applied to the ferroelectric film.

According to another aspect of the present invention, a substrate having a semiconductor surface layer, and a gate insulating film, a floating gate conductive film, and a gate insulating film formed on a partial region of the semiconductor surface layer of the substrate in this order from the substrate side. A gate stack structure in which a dielectric film and a control gate electrode are stacked; and two impurity diffusion regions formed in both sides of the gate stack structure in a semiconductor surface layer of the substrate, wherein the floating gate A ferroelectric memory cell having two impurity diffusion regions arranged so that a vertical projection image of a conductive film on the substrate surface and one impurity diffusion region partially overlap each other is formed in a matrix on the substrate. And a word line connecting control gate electrodes of the memory cells arranged in each row, for each row of the memory cell matrix structure, For each column in the Moriseru matrix structure, a ferroelectric memory device having a bit line connected to the one of the impurity diffusion region between the memory cells arranged in each row are provided.

The voltage applied to the selected word line among the word lines is V _W1 , the voltage applied to the other word lines is V _W2 , and the voltage applied to the selected bit line among the bit lines is V _{W B1} , the voltage applied to the other bit lines is V
When the _B2, the absolute value of (V _W1 -V _B1) becomes the size capable of changing the spontaneous polarization direction of the ferroelectric film of the memory _{cell, (V W1 -V B2),} (V W2 -V _B1 ) and (V _W1 −
When a voltage is applied to the word line and the bit line so that the absolute value of V _B2 ) does not change the direction of the spontaneous polarization of the ferroelectric film of the memory cell, the voltage between the selected word line and the bit line is changed. The spontaneous polarization of the ferroelectric film can be changed only for the memory cell at the intersection.

[0020]

FIG. 1 is a block diagram of an embodiment of the present invention.
1 shows a cross-sectional view of an FMIS structure transistor. One transistor constitutes one memory cell. A gate laminated structure 10 is formed on a partial region of a silicon substrate 1 provided with p-type conductivity. Gate laminated structure 10
Has a structure in which a gate insulating film 4, a floating gate conductive film 5, a ferroelectric film 6, and a control gate electrode 7 are sequentially stacked from the lower layer.

The gate insulating film 4 is, for example, a SiO ₂ film having a thickness of 10 nm, and is formed by thermal oxidation.

The floating gate conductive film 5 is constituted by, for example, laminating a polysilicon film having a thickness of 450 nm, an iridium oxide (IrO ₂ ) film having a thickness of 50 nm, and an iridium (Ir) film having a thickness of 100 nm in this order. You.
The polysilicon film contains phosphorus (P) at a concentration of 1 × 10 ²⁰ cm.
^{-3 is} doped to provide n-type conductivity.

The polysilicon film is formed by, for example, using silicon as a target and performing sputtering in an Ar atmosphere. The IrO ₂ film is formed by, for example, reactively sputtering an Ir target in a mixed atmosphere of Ar and O ₂ . The Ir film is formed, for example, by sputtering an Ir target in an Ar atmosphere. The IrO ₂ film and the Ir film are inserted to form a ferroelectric film having a favorable perovskite structure thereon. Further, the IrO ₂ film also functions as a diffusion barrier layer.

The ferroelectric film 6 is, for example, a 200 nm thick SrBi ₂ Ta ₂ O ₉ (SBT) film. The SBT film can be formed by, for example, a sol-gel method. More specifically, a mixed alkoxide solution as a starting material is spin-coated on the substrate surface, and dried at a temperature of 250 ° C.
After repeating this four times, the temperature was increased to 650 in an O ₂ atmosphere.
Temporary baking is performed at 30 ° C. for 30 minutes. After that, a crystallization heat treatment is performed for 30 minutes at a temperature of 800 ° C. in an O ₂ atmosphere.

The control gate electrode 7 has a lower layer thickness of 50 nm.
It composed of two layers of IrO ₂ film and an upper thickness 200 nm Ir film.

The patterning of the laminated structure from the gate insulating film 4 to the control gate electrode 7 can be performed, for example, by reactive ion etching (RIE) using a mixed gas of CF ₄ and Ar.

In the surface layer of the silicon substrate 1, n ⁺ -type impurity diffusion regions 3S are provided on both sides of the gate laminated structure 10, respectively.
And 3D are formed. The structure is such that a vertical projection image of the floating gate conductive film 5 on the substrate surface and one impurity diffusion region partially overlap each other.
Here, the overlapped impurity diffusion region is referred to as a drain region 3D, and the other is referred to as a source region 3S.

Note that, similarly to the drain region 3D, the source region 3S may be configured to overlap the vertical projection image of the floating gate conductive film 5 on the substrate surface. At this time, the area where the vertical projection image of the floating gate conductive film 5 on the substrate surface overlaps with the drain region 3D is larger than the overlap area with the source region 3S.

The source region 3S is formed, for example, by using the gate lamination structure 10 as a mask and accelerating energy 3 from substantially vertical direction.
It is formed by implanting As ions under the conditions of 0 keV and a dose of 1 × 10 ¹⁵ cm ⁻² . Drain region 3D
For example, using the gate laminated structure 10 as a mask, the incident angle is 60 °, the acceleration energy is 60 keV, and the dose is 1 × 10 ¹⁵
It is formed by implanting As ions under the condition of cm ⁻² . After ion implantation, activation heat treatment is performed.

By ion implantation from an oblique direction,
The drain region 3D can be penetrated from the end of the gate stack structure 10 to below. In this way,
A structure is obtained in which an image obtained by vertically projecting the floating gate conductive film 5 on the substrate surface overlaps the drain region 3D. In order to obtain such a structure, the drain region 3D
It is preferable that the angle of incidence of ion implantation for formation be 45 to 70 °.

For example, the lateral length (direction of current flow) of the gate laminated structure 10 in the drawing is 0.6 μm, the gate width is 5 μm, and the lateral direction of the overlapping portion of the gate laminated structure 10 and the drain region 3D in the drawing. Is 0.3 μm.

Next, a method for writing to the memory cell shown in FIG. 1 will be described. By applying a voltage between the drain region 3D and the control gate electrode 7 to generate an electric field in the ferroelectric film 6, remnant polarization occurs in the ferroelectric film 6. The direction of the remanent polarization can be controlled by the polarity of the applied voltage.

Next, a preferred value of the length of the overlapping portion between the gate laminated structure 10 and the drain region 3D will be considered.
The capacitance between the floating gate conductive film 5 and the drain region 3D is C _FD , and the capacitance of the ferroelectric film 6, that is, the capacitance between the control gate electrode 7 and the floating gate conductive film 5 is C _f The voltage between the drain region 3D and the control gate electrode 10 is set to V _GD . At this time, the voltage _Vf applied to the ferroelectric film 6 is

[0034]

V _f = (C _FD / (C _FD + C _f )) × V _GD (1) Here, C _FD / (C _FD + C _f ) is called a coupling ratio. In the case of the dimensions described in the above embodiment, the coupling ratio is about 0.28. The relative permittivity of SBT was 100, and the relative permittivity of SiO ₂ was 3.9.

The coercive electric field of the SBT is about 50 kV / c as a standard value.
m, the coercive voltage in this case, ie, the ferroelectric film
The minimum voltage that can reverse the remanent polarization of
V. Therefore, the polarization of the ferroelectric film 6 is reversed.
V between the control gate electrode 7 and the drain region 3D_GD
Is V in equation (1)._f1V, C_FD/ (C_FD+
C _f) Is substituted for 0.28, resulting in about 3.6V. cup
Control to reverse the polarization as the ring ratio decreases
Voltage V between gate electrode 7 and drain region 3D_GDIs large
Become. For this reason, the coupling ratio should be 0.2 or more.
Is preferred. When the coupling ratio is 0.2, the polarization
Control gate electrode 7 for inversion and drain region 3D
Voltage V between_GDBecomes 5V.

When the thickness of the ferroelectric film 6 is 200 nm, the relative permittivity is 100, the thickness of the gate insulating film 4 is 10 nm, and the relative permittivity is 3.9, the coupling ratio is 0.2 or more. In order to achieve this, the area of the overlapping portion between the image of the floating gate conductive film 5 vertically projected on the substrate surface and the drain region 3D needs to be 0.32 or more of the total area of the image. The processing length of the floating gate conductive film 5 is 0.6
In the case of μm, the horizontal depth of the overlapping portion is 0.
It is 19 μm or more.

The preferred value of the lateral depth of the overlapping portion varies depending on the relative permittivity of the ferroelectric film and the thickness ratio between the ferroelectric film and the gate insulating film. When LiNbO ₃ having a relative permittivity of 30, YMnO ₃ having a relative permittivity of 20, or Sr ₂ Nb ₂ O ₇ having a relative permittivity of 43 to 75 is used as the ferroelectric film, the lateral depth of the overlapping portion is made smaller. can do.

FIG. 1 shows a case in which a transistor having an MFMIS structure is formed on a p-type silicon substrate. However, a p-type well is formed in a surface layer of the silicon substrate, and an
A transistor having an FMIS structure may be formed.

FIG. 2 is an equivalent circuit diagram of a ferroelectric memory device using the memory cell of FIG. The memory cells shown in FIG. 1 are arranged in a matrix. FIG. 2 shows a 2-row, 2-column portion as a representative. A ground potential is applied to the source region and the channel region of each memory cell. When the MFMIS structure transistor shown in FIG. 1 is formed in a p-type well, the p-type well is grounded.

The control gate electrodes of the memory cells arranged in each row of the matrix structure of the memory cells are connected to the word line W for each row.
L. Each word line is connected to a word line control circuit 20. The drain regions of the memory cells arranged in each column are connected to each other by a bit line BL for each column. Each bit line is connected to a bit line control circuit 21 and a signal detection circuit 22.

The word line control circuit 20 and the bit line control circuit 21 correspond to each word line WL and each bit line BL, respectively.
, A predetermined voltage can be applied selectively. The signal detection circuit 22 can selectively detect an electric signal generated on each bit line BL.

Next, the writing process to the ferroelectric memory device shown in FIG. 2 will be described with reference to FIG. FIG. 3 (A)
(B) schematically shows word lines and bit lines arranged in a lattice, and memory cells arranged at intersections thereof. In the following description, it is assumed that the coercive voltage between the control gate electrode and the drain region required to invert the polarization of the ferroelectric film is V _CC .

The n-th word line WL shown in FIG._n
And the m-th bit line BL_mAt the intersection with
Consider the case of writing to a molycell. nth word line W
L_nCoercive voltage V_CCAnd apply a coercive voltage to the other word lines.
V_CCIs applied. m-th bit line BL
_mAnd the coercive voltage V is applied to the other bit lines. _CC
Is applied.

Since a coercive voltage V _CC is applied between the control gate electrode and the drain region of the memory cell in the n-th row and the m-th column,
Even when the applied voltage is released, residual polarization in a predetermined direction remains in the ferroelectric film. In this case, upward residual polarization remains in the ferroelectric film 6 shown in FIG.

In other memory cells, only one-third of the coercive voltage V _CC is applied between the control gate electrode and the drain region. Therefore, the direction of the remanent polarization of the ferroelectric film does not change. That is, the polarization state before voltage application is maintained.

FIG. 3B shows a case where the direction of the remanent polarization of the ferroelectric film of the memory cell in the n-th row and the m-th column is directed downward. applying a ground potential to the n-th word line WL _n, applies a 2/3 voltage of the coercive voltage V _CC to the other word lines.
The coercive voltage V _CC is applied to the m-th bit line BL _m, applying a third voltage of the coercive voltage V _CC to the other bit line.

In this case, as in the case of FIG.
In n rows and m-th column of the memory cell only, the control gate electrode and between the drain region coercive voltage V _CC is applied to the other in the memory cell, only 1/3 of the voltage of the coercive voltage V _CC is not applied. Further, since the direction of the electrode applied to the memory cell in the n-th row and the m-th column is opposite to that in FIG. 3A, downward remanent polarization occurs in the ferroelectric film.

As described above, it is possible to select only one of the memory cells arranged in a matrix and control the polarization state of the ferroelectric film of the selected memory cell.

Note that a plurality of memory cells in the same row or a plurality of memory cells in the same column may be selected. In this case, the voltages applied to the selected word lines and bit lines and the unselected word lines and bit lines may be the same as those described above.

Note that the voltage applied to each word line and bit line is
Voltage is not necessarily the coercive voltage V_CC1/3 and 2/3 of
Need not be. To the selected memory cell of the word line
The voltage applied to the connected word line is V_W1,Other
The voltage applied to the word line is V_W2, Select out of bit lines
Voltage applied to the bit line connected to the memory cell
Pressure V_B1And the voltage applied to the other bit lines is V_B2When
When (V_W1-V _B1) Is the coercive voltage V_CCThan
Becomes larger, and (V_W1-V_B2), (V_W2-V_B1),as well as
(V_W1-V_B2) Is the coercive voltage V_CCSmaller than
You may make it.

Next, the reading process of the ferroelectric memory device shown in FIG. 2 will be described with reference to FIG.

FIG. 4A shows current-voltage characteristics of each memory cell. The curves a and b in the figure correspond to the case where downward and upward remanent polarization occurs in the ferroelectric film 6 shown in FIG. 1, respectively. The threshold voltage when the memory cell is in state of the curve a and b, respectively, and V _TL and V _TH.

FIG. 4B schematically shows word lines and bit lines arranged in a lattice, and memory cells arranged at the intersections. Consider a case where information of a memory cell in the n-th row and the m-th column is read. A voltage V _SEL intermediate between the threshold voltages V _TL and V _TH is applied to the n-th word line WL _n , and a voltage V _NSEL lower than V _TL is applied to the other word lines.

The memory cell connected to the n-th word line is conductive when in the state corresponding to curve a in FIG. 4A, and is non-conductive when in the state corresponding to curve b. The memory cells connected to the other word lines are non-conductive in any of the states of the curves a and b. FIG.
Bit line BL from the bit line control circuit 21 shown in FIG.
giving an electrical signal in _m, by detecting the electric signals appearing in signal detecting circuit 22 to the bit line BL _m, n rows and m
The information of the memory cell in the column can be read.

In this case, the n-th word line WL _n
It is also possible to simultaneously read out information of a plurality of memory cells connected to the memory cell.

According to the above embodiment, as shown in FIG.
A common potential is applied to the source region and the channel region of all the memory cells. Therefore, there is no need to electrically insulate the source region and the channel region of the plurality of memory cells. In addition, a specific memory cell can be selected in both writing and reading with only one group of word lines and one group of bit lines. Therefore, it is easy to achieve high integration.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0058]

As described above, according to the present invention,
Since the vertical projection image of the floating gate conductive film on the substrate surface and the one impurity diffusion region partially overlap each other, of the voltages applied between the control gate electrode and the one impurity diffusion region, The voltage applied to the ferroelectric film between the floating gate conductive film and the control gate electrode can be increased. Therefore, a voltage higher than the coercive voltage can be applied to the ferroelectric film at a relatively low voltage.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a transistor having an MFMIS structure according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of a ferroelectric memory device using one transistor of the MFMIS structure shown in FIG. 1 as one memory cell.

FIG. 3 is a schematic diagram of a word line, a bit line, and a memory cell for describing a writing process of the ferroelectric memory device shown in FIG. 2;

4 is a graph showing current-voltage characteristics of the transistor having the MFMIS structure shown in FIG. 1, and a schematic diagram of word lines, bit lines, and memory cells for explaining a reading process of the ferroelectric memory device shown in FIG. It is.

FIG. 5 is a cross-sectional view of a transistor having an MFMIS structure according to a conventional example.

6 is an equivalent circuit diagram of a ferroelectric memory device using one transistor having the MFMIS structure shown in FIG. 5 as one memory cell.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 100 Silicon substrate 2, 101 Channel region 3S, 102S Source region 3D, 102D Drain region 4, 103 Gate insulating film 5, 104 Floating gate conductive film 6, 105 Ferroelectric film 7, 106 Control gate electrode 10 Gate laminated structure 20, 110 Word line control circuit 21, 111 Bit line control circuit 22, 112 Signal detection circuit 113 Source line control circuit WL Word line BL Bit line SL Source line

Claims (7)

[Claims] 1. A substrate having a semiconductor surface layer, and a gate insulating film, a floating gate conductive film, a ferroelectric film, and a control gate formed on a partial region of the semiconductor surface layer of the substrate in order from the substrate side. A gate lamination structure in which electrodes are laminated, and two impurity diffusion regions respectively formed in regions on both sides of the gate lamination structure in the semiconductor surface layer of the substrate, wherein A vertical projection image and one of the impurity diffusion regions, the two impurity diffusion regions being disposed so as to partially overlap each other; and an electrostatic capacitance between the floating gate conductive film and the one impurity diffusion region. When the capacitance is C _FD and the capacitance of the ferroelectric film, that is, the capacitance between the control gate electrode and the floating gate conductive film is C _f , The ferroelectric film, the gate insulating film, the floating gate conductive film, and the one impurity diffusion region are configured so that a ring ratio C _FD / (C _FD + C _f ) becomes 0.2 or more. Ferroelectric memory cell. 2. The vertical projection image of the floating gate conductive film on the substrate surface and the other impurity diffusion region are arranged so as to overlap each other, and an area of an overlapping portion between the vertical projection image and the one diffusion region is provided. Is larger than the area of the overlapping portion between the vertical projection image and the other diffusion region.
3. The ferroelectric memory cell according to 1. 3. A substrate having a semiconductor surface layer, and a gate insulating film, a floating gate conductive film, a ferroelectric film, and a control gate formed on a partial region of the semiconductor surface layer of the substrate in order from the substrate side. A gate lamination structure in which electrodes are laminated, and two impurity diffusion regions respectively formed in regions on both sides of the gate lamination structure in the semiconductor surface layer of the substrate, wherein In a ferroelectric memory cell having a vertical projection image and two impurity diffusion regions arranged so that one impurity diffusion region partially overlaps with each other, the ferroelectric memory cell has a structure in which the control gate electrode and the one impurity diffusion region are A method of driving a ferroelectric memory cell in which a writing process is performed by applying a voltage therebetween to generate remanent polarization in the ferroelectric film. 4. A substrate having a semiconductor surface layer, and a gate insulating film, a floating gate conductive film, a ferroelectric film, and a control gate formed on a partial region of the semiconductor surface layer of the substrate in order from the substrate side. A gate lamination structure in which electrodes are laminated, and two impurity diffusion regions respectively formed in regions on both sides of the gate lamination structure in the semiconductor surface layer of the substrate, wherein A ferroelectric memory cell having a vertical projection image and two impurity diffusion regions arranged such that one of the impurity diffusion regions partially overlaps a memory cell matrix arranged in a matrix on the substrate A word line connecting the control gate electrodes of the memory cells arranged in each row to each of the rows of the memory cell matrix structure; The ferroelectric memory device having a bit line connected to the one of the impurity diffusion region between the memory cells arranged in each column. 5. The ferroelectric memory device according to claim 4, wherein a common potential is applied to a region of the semiconductor surface layer sandwiched between the two impurity diffusion regions of all the memory cells. 6. The word line and the bit line,
A control circuit for applying a controlled voltage, wherein a voltage applied to a selected word line among the word lines is V _W1 , a voltage applied to other word lines is V _W2 , When the voltage applied to the selected bit line is V _B1 and the voltage applied to the other bit lines is V _B2 , the absolute value of (V _W1 −V _B1 ) is equal to the ferroelectric film of the memory cell. (V _W1 −V _B2 ), (V _W2 −V _B1 ), and (V _W1 −V
6. The control circuit according to claim 4, further comprising a control circuit for applying a voltage to the word line and the bit line such that the absolute value of _B2 ) does not change the direction of spontaneous polarization of the ferroelectric film of the memory cell. The ferroelectric memory device according to claim 1. 7. The first voltage is a threshold voltage at which the memory cell becomes conductive when the ferroelectric film of the memory cell is polarized in a first direction. The threshold voltage at which the memory cell becomes conductive when polarized in the second direction opposite to the second direction is the second voltage, and the control circuit supplies the first word to the selected word line. Applying a voltage intermediate between the voltage and the second voltage, and applying a voltage to the other word lines to render the memory cell non-conductive regardless of the direction of polarization of the ferroelectric film of the memory cell; 7. The ferroelectric memory device according to claim 6, further comprising a signal detection circuit for detecting an electric signal appearing on the bit line.