JP3422442B2 - Nonvolatile semiconductor memory device and method of using and manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile memory cell in which a memory cell is formed by a MIS transistor in which a gate insulating film is composed of a ferroelectric film on the gate electrode side and a paraelectric film on the channel region side. Semiconductor memory device and its use and manufacturing method.

[0002]

2. Description of the Related Art FIG. 14 shows an example of hysteresis characteristics of a ferroelectric substance. In this hysteresis characteristic, V _F is the applied voltage, Q is the polarization charge, ± V _C is the coercive voltage, and ± Q _P is the residual polarization charge. ± 2V _C is generally adopted as a voltage for reversing the polarization direction, and it is considered from this hysteresis characteristic that the polarization state hardly changes even when a voltage of ± 2V _C / 3 is applied. .

From the hysteresis characteristic shown in FIG. 14, P
It is conceivable to manufacture a nonvolatile semiconductor memory device using a ferroelectric such as ZT, and roughly classified into two methods. FIG. 15 shows a first method having a configuration similar to that of the DRAM. That is, one MIS transistor 11 to which the word line W serves as the gate electrode and the bit line B is connected, and one capacitor 12 to which the plate electrode P is connected, and one memory cell M.
And a ferroelectric film is used as the dielectric film of the capacitor 12.

FIG. 16 shows the second method. In the second method, as shown in FIG. 16A, the word line W
Serves as a gate electrode, and one MIS transistor 13 connected to the bit line B and the source line S forms one memory cell M.

In the MIS transistor 13, as shown in FIG.
As shown in (b), the gate insulating film is formed only by the ferroelectric film 14, or as shown in FIG. 16C, the word line W, that is, the ferroelectric film 14 on the gate electrode side. The paraelectric film 15 on the channel region side, for example, a SiO ₂ film,
And form a gate insulating film. A metal film 16 is provided between the paraelectric film 15 and the ferroelectric film 14 to facilitate the growth of the polarizable ferroelectric film 14, but the metal film 16 is not always necessary. is not.

The polarization of the ferroelectric film 14 controls the threshold voltage as shown in FIG. For example, when the MIS transistor 13 is an n-channel and a negative charge is induced on the surface of the ferroelectric film 14 on the channel region side, the threshold voltage shifts to the positive side. In the gate voltage-drain current characteristics shown in FIG. 17, the threshold voltage V _{th0 in} the initial state and the read voltage V _R are 1.5 V, the threshold voltage V _thE in the erased state is 2.5 V, and the threshold voltage V _thW in the _written state is 0. It is set to 0.5V. The same symbols as those in the capacitor 12 in the MIS transistor 13 indicate the ferroelectric film 14.

In the first method shown in FIG. 15, since information is destroyed at the time of reading, rewriting of information is necessary for each reading, and reading cannot be performed at high speed. Moreover, since the number of effective erase / write operations increases and the ferroelectric film deteriorates frequently, the number of rewritable times is small and the life is short. Further, the memory cell area is as large as that of DRAM, and it is not easy to increase the capacity. On the other hand, in the second method shown in FIG. 16, information can be read without destroying the information, and since the memory cell M can be formed by one MIS transistor 13, the memory cell area is also increased. small.

FIG. 18 shows a memory cell array configured by the above-mentioned second method. In this memory cell array, a selected memory cell, for example, the memory cell M
To write information to ₁₁ , as shown in FIG.
It is necessary to apply a high voltage 2V _C (= V _FW ) capable of reversing the polarization direction to the ferroelectric film 14 of the memory cell M ₁₁ .
It is necessary to apply the write voltage V _W for that purpose to the gate electrode, that is, the word line W ₁ .

On the other hand, unselected memory cells M ₁₂ ...
In M ₂₂ , even if a voltage is applied to the ferroelectric film 14, it is necessary to apply only a low voltage 2 V _C / 3 or less which does not invert the polarization direction, as shown in FIG. Among the memory cells M ₁₂ ~M ₂₂ which are not selected, the memory cells M _21, M ₂₂ which are arranged in different rows as the memory cell M _11, which is selected, the selected memory cell M ₁₁ and the word line W _{Since 1} is not shared, the high write voltage V _W of the word line W ₁ is not applied to the ferroelectric film 14.

However, the memory cell M ₁₂ arranged in the same row but in a different column from the selected memory cell M _11.
, The word line W ₁ is shared with the selected memory cell M ₁₁ . Therefore, in the memory cell M ₁₂ , in order to ensure that only a low voltage of 2 V _C / 3 or less that does not invert the polarization direction is applied to the ferroelectric film 14,
_A channel is formed in the ₁₂ MIS transistors 13 and a predetermined voltage is applied to the bit line B ₂ to make the source line S ₂ in a floating state so that the potential of the channel is equal to the potential of the bit line B ₂ and the word line W 2 The voltage between ₁ and the channel is reduced to 1/3 or less of the write voltage V _W.

[0011]

However, the memory cell M
Since it is necessary to form a channel in the ₁₂ MIS transistors 13, between the word line W ₁ and the channel region,
It is necessary to apply a voltage equal to or higher than the threshold voltage V _{thE in the} erased state. Therefore, the write voltage V _W applied to the word line W ₁
It is necessary to make the voltage ⅓ of the threshold voltage _VthE or more, and eventually, the write voltage V _W needs to be three times or more the threshold voltage _VthE .

As shown in FIG. 17, the threshold voltage V in the erased state
_{When thE} is _set to 2.5 V, the write voltage V _W is set as described above.
Must be 7.5V at least, also the erase voltage V _E is required to be -7.5V. However, as the degree of integration of the semiconductor memory device is improved, the power supply voltage V _CC is 2.5 to
When the voltage drops to about 1.5 V, the write voltage V _W and the erase voltage V _E of ± 7.5 V become extremely high voltages. Therefore, even the second method shown in FIG. 16 has a problem that it cannot be operated at a low voltage.

Further, among the second methods, FIG.
As shown in FIG. 3, in the system in which the gate insulating film is formed only by the ferroelectric film 14, the ferroelectric film 14 and the semiconductor substrate 1 are
The interface characteristics with 7 are not good, and the interface state density is high.
Therefore, the polarization effect is canceled, there was also the threshold voltage V _thE and problems reliability is low in operation varies the threshold voltage V _THW in the written state of the erasing state.

[0014]

SUMMARY OF THE INVENTION The non-volatile semiconductor memory device according to claim 1, the gate insulating film between the paraelectric film 27 of the ferroelectric film 44 and the channel region side of the Gate electrode 46 side is configured The memory cells M _{11 to} M ₂₂ are formed by the MIS transistor 47, and the plurality of memory cells M _{11 to} M ₂₂ are formed.
_{11 to} M ₂₂ are arranged in a matrix, and the gate electrodes 4 of the MIS transistors 47 are arranged in the row direction.
In a nonvolatile semiconductor memory device in which 6 are connected to each other to form word lines W ₁ and W ₂ , intermediate electrodes 31 and 41 are provided between the ferroelectric film 44 and the paraelectric film 27. The switching transistors T _{P11 to} T _P22 are provided in each of the plurality of memory cells M _{11 to} M ₂₂ , and the intermediate electrodes 31 and 41 are connected to the control electrode P ₁ via the switching transistors T _{P11 to} T _P22. is characterized in that is connected to the P _2, the source / drain of the switching transistor T _P11 through T _P22 arranged in the column direction are connected in series with each other.

A non-volatile semiconductor memory device according to a second aspect is the non-volatile semiconductor memory device according to the first aspect , wherein the switching transistors T _{P11 to} T _P22 are the thin film transistors 4.
8, the active layer 31 of the thin film transistor 48 and the intermediate electrode 31 are formed of the semiconductor film 31 in the same layer.

The nonvolatile semiconductor memory device according to claim 3, in the nonvolatile semiconductor memory device according to claim 1, the channel and the word line W ₁ of the said for reading the information of the memory cell M ₁₁ MIS transistor 47 Of the read voltage V _R applied during this period, the voltage V _FR applied to the ferroelectric film 44 is smaller than the coercive voltage V _C of the ferroelectric film 44, so that the ferroelectric film 44 is reduced. And the relative dielectric constants ε _F and ε _OX and the film thicknesses t _F and t _{OX of the} paraelectric film 27 are set.

According to the method of using the nonvolatile semiconductor memory device of claim 4 , all the switching transistors T _P11 are used when the nonvolatile semiconductor memory device of claim 3 is used.
To T _P22 are turned on, and all the word lines W ₁ and W ₂ are _turned on.
By applying a voltage −2V _C higher than the coercive voltage V _C of the ferroelectric film 44 between the memory cell M ₁₁ and all the control electrodes P ₁ and P ₂ , The information in M ₂₂ is erased all at once, and all the switching transistors T
_P11 The through T _P22 is conductive, the greater than the coercive voltage V _C between the control electrode P ₁ of the first of the word lines W ₁ and the first intersecting each other at the memory cell M _11, which is selected In addition, a voltage of 2V _C having a polarity opposite to that at the time of batch erasing is applied, and a voltage of 4V _C / 3 between the _first word line W ₁ and the coercive voltage V _C, which is smaller than the coercive voltage V _C , is applied to the first control. applying a non-electrode P ₁ 2 for the control electrode P _2, a small voltage 2V _C / 3 also voltage than the coercive voltage V _C between the first and second control electrodes P _1, P ₂ Information is written in the selected memory cell M ₁₁ by applying to the _second word line W ₂ other than the _first word line W ₁ , and all the switching transistors T _{P11 to} T _P22 are turned off. And the read voltage V ₁ is applied to the word line W ₁ passing through the selected memory cell M _11. Information is read from the selected memory cell M ₁₁ by applying _R.

A method of using the non-volatile semiconductor memory device according to a fifth aspect is the method of using the non-volatile semiconductor memory device according to the fourth aspect , wherein the voltage between the _first control electrode P ₁ and the _first control electrode P ₁ at the time of the writing is the 2V less than coercive voltage V _C
Applies a _C / 3 to the first and second word lines W _1, W _2, between the control electrode P ₁ the first than the first and second word lines W _1, W ₂ Is applied to the _second control electrode P ₂ at a voltage 4 V _C / 3 which is higher than the coercive voltage V _{C and} whose voltage between the first and second word lines W ₁ and W ₂ is smaller than the coercive voltage V _C. , After the switching transistors T _{P11 to} T _P22 are turned on, the voltage between the _first control electrode P ₁ and the second word line W ₂ is larger than the coercive voltage V _C. It is characterized by applying a voltage smaller voltage 2V _C than said coercive voltage V _C to the word line W ₁ of the first between large and the second control electrode P ₂ than.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a non-volatile semiconductor memory device, wherein the switching transistors T _{P11 to} T _P22 are used when manufacturing the non-volatile semiconductor memory device of the second aspect.
Forming the gate electrodes 34 of the switching transistors T _{P11 to} T _{P22 in} the row direction, forming sidewalls of the first insulating film 36 on the gate electrodes 34 of the switching transistors T _{P11 to} T _P22 , and the first insulating film. Forming a conductive film 41 in contact with the active layer 31 between the films 36 and filling the recesses between the first insulating films 36; dividing the conductive film 41 into columns; The second recess is formed between the conductive films 41.
After being filled with the insulating film 43 of
And forming the ferroelectric film 44 and the word lines W ₁ and W ₂ on the insulating film 43.

[0020]

[Action] In the nonvolatile semiconductor memory device according to claim 1, braking source / drain of the switching transistor T _P11 through T _P22 connected to the control electrode P _1, P ₂ are connected in series to each other extending in the column direction The word lines W ₁ and W ₂ extend in the row direction. Therefore, it is possible to select the desired memory cell M ₁₁ ~M ₂₂ by selecting the word lines W _1, W ₂ and a control electrode P _1, P _2, the control electrodes P _1, P ₂
Can be performed on desired memory cells M _{11 to} M ₂₂ .

[0021] In the nonvolatile semiconductor memory device according to claim 2,
Since the active layer 31 and the intermediate electrode 31 of the switching transistor T _P11 through T _P22 it is formed in the semiconductor film 31 of the same layer, an active layer 31 and the intermediate electrode 31 of the switching transistor T _P11 through T _P22 same process Can be formed simultaneously.

[0022] In the nonvolatile semiconductor memory device according to claim 3,
Of the read voltage V _R, the voltage V _FR applied to the ferroelectric film 44 is smaller than the coercive voltage V _C of the ferroelectric film 44, so that information is not destroyed during reading and rewriting of information is unnecessary. Is.

[0023] In use of the nonvolatile semiconductor memory device according to claim 4, when information is written into the memory cell M _11, selected ferroelectric film 44 on only the coercive voltage V of the memory cell M ₁₁
A voltage larger than C is applied, and a voltage smaller than the coercive voltage V _C is applied to the ferroelectric film 44 of the unselected memory cells M _{12 to} M ₂₂ . Therefore, the information is written only to the selected memory cell M _11, and the information is not written to the unselected memory cells M _{12 to} M ₂₂ .
Further, the information of all the memory cells M _{11 to} M ₂₂ is erased in the batch erase, and any of the memory cells M _{11 to} M ₂₂ is read in the read.
Information is not destroyed.

In the method of using the non-volatile semiconductor memory device according to the fifth aspect , all the switching transistors T _{P11 to} T _P11.
Before making _P22 conductive, a voltage having a larger voltage between the _first and _second control electrodes P ₁ than the first and second word lines W ₁ and W ₂ is applied to the second control electrode P _2. ing. Therefore, even when the voltage is applied to the _second control electrode P ₂ earlier than the voltage is applied to the first and second word lines W ₁ and W ₂ , the memory cells M _{11 to} M ₂₂ are not affected. Intermediate electrode 3
Nos. 1 and 41 are in a floating state, and the information of the memory cells M ₁₂ and M ₂₂ connected to the _second control electrode P ₂ is not destroyed.

Further, after applying a voltage 4V _C / 3, which is lower than the coercive voltage V _C , between the first and second word lines W ₁ and W ₂ to the second control electrode P ₂ , voltage 2V _C voltage is smaller than the coercive voltage V _C between the large and the second control electrode P ₂ than voltage coercive voltage V _C between the first control electrode P ₁
Is applied to the first word line W ₁ . Therefore, the second
Even if the timing of applying the voltage to the control electrode P ₂ of the above is later than the timing of applying the voltage to the first and second word lines W ₁ and W ₂ , it is connected to the _second control electrode P ₂ . The information in the memory cells M ₁₂ and M ₂₂ is not destroyed.

In the method for manufacturing a non-volatile semiconductor memory device according to a sixth aspect , the recesses between the first insulating films 36 which are the sidewalls of the gate electrodes 34 of the switching transistors T _{P11 to} T _P22 are formed in the conductive film 41 and the second insulating film. Since the ferroelectric film 44 and the word lines W ₁ and W ₂ are formed on the conductive film 41 and the second insulating film 43 after the film 43 is flattened, the switching transistors T _{P11 to} T _P22 are formed. The gate electrode 34
Even if the space between them is narrow, the ferroelectric film 44 and the word lines W ₁ and W ₂ can be easily formed.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS.
Will be described with reference to. 1 to 3 show the present embodiment, first, the manufacturing method of the present embodiment will be described with reference to FIGS. In order to manufacture this embodiment, as shown in FIG. 4A, Si having a laminated structure is formed on the surface of a p-type Si substrate 21.
_{A 3} N ₄ / SiO ₂ film 22 is formed, and this Si ₃ N ₄ / SiO ₂ film is formed.
A photoresist 23 is processed on the film 22 into a stripe pattern of element active regions.

The extending direction of the element active region is the column direction of the memory cell array, and the direction perpendicular to the extending direction of the element active region is the row direction of the memory cell array. After that, using the photoresist 23 as a mask, Si ₃ N ₄ / Si
The O ₂ film 22 is etched, and As ⁺ 24 is ion-implanted into the Si substrate 21 using the photoresist 23 as a mask.

Next, as shown in FIG. 4B, after the photoresist 23 is removed, a LOCOS method using the Si ₃ N ₄ / SiO ₂ film 22 as an anti-oxidation film is performed to remove the element isolation region. The SiO ₂ film 25 is formed on the surface, and the ion-implanted As ⁺ 24 is used to form the n ⁺ diffusion layer 26a under the SiO ₂ film 25.
26b is formed.

Next, as shown in FIG. 4 (c), Si ₃ N ₄ /
After removing the SiO ₂ film 22, S as a gate oxide film is formed.
An iO ₂ film 27 is formed on the surface of the element active region. In addition,
The film thickness t _OX of this SiO ₂ film 27 is 5 nm and the relative dielectric constant ε _OX.
= 3.9. And polycrystalline Si containing no impurities
A film 31 is deposited on the entire surface, and B ⁺ 32 is ion-implanted on the entire surface of the polycrystalline Si film 31.

Next, as shown in FIG. 5A, the polycrystalline Si film 31 is processed into a pattern extending in the column direction on the SiO ₂ film 25 on the element active region and in the vicinity thereof, and this polycrystalline Si film 31 is processed. S
A SiO ₂ film 33 is formed on the surface of the i film 31. When the polycrystalline Si film 31 is processed, its cross-sectional shape is made into a forward tapered shape by a conventionally known method. After that, an n ⁺ -type polycrystalline Si film 34 is deposited on the entire surface, and the polycrystalline Si film 34 is
A SiO ₂ film 35 is deposited on the entire upper surface.

Next, as shown in FIG. 5B, the SiO ₂ film 35 and the polycrystalline Si are formed in a striped pattern extending in the row direction.
The film 34 and the SiO ₂ film 33 are continuously processed. Then, by depositing and etching back the SiO ₂ film 36,
A side wall made of this SiO ₂ film 36 is formed on the side surface of the polycrystalline Si film 34 or the like. Then, using the SiO ₂ film 35 or the like as a mask, Phos ⁺ 37 for adjusting the threshold voltage and Phos ⁺ 38 for turning the polycrystalline Si film 31 into n ⁺ are used.
Ions are continuously implanted with different energies.

Next, as shown in FIG. 6A, the n ⁺ -type polycrystalline Si film 41 is deposited and etched back to form Si.
Striped polycrystalline Si films 41 extending in the row direction are formed by filling the recesses between the O ₂ films 36. Then, a metal film 42 such as a Pt film or a Pt / TiN film having a laminated structure is deposited on the entire surface, and the metal film 42 and the polycrystalline Si films 41 and 31 are processed to have a width similar to that of the polycrystalline Si film 31. As a result, the polycrystalline Si film 41 has an island pattern that is isolated corresponding to each memory cell.

Next, as shown in FIG. 6B, the polycrystalline Si film 4 is formed by depositing and etching back the SiO ₂ film 43.
The concave portion between 1 and 31 is filled with the SiO ₂ film 43 to flatten the surface. Then, as shown in FIG. 3, a ferroelectric film 44 such as PZT, a barrier metal film 45 such as a Ti film, and A
l film 46 is sequentially formed, and polycrystalline S arranged in the row direction is formed.
The Al film 46, the barrier metal film 45, and the ferroelectric film 44 are continuously processed into a word line pattern connecting the i films 41.

The coercive electric field E _C of the ferroelectric film 44 = 6 ×
10 ⁴ V / cm, film thickness t _F = 125 nm, coercive voltage V _C = E _C
・ T _F = 0.75 V and relative permittivity ε _F = 250. After that, a surface protective film (not shown) or the like is formed by a conventionally known method to complete this embodiment.

In the present embodiment manufactured as described above, as shown in FIGS. 1 and 2, the n ⁺ diffusion layer 26a is the common source line S ₁₂ , and the n ⁺ diffusion layer 26b is the bit lines B ₁ , B. ₂ That is, the word line W which is the drain line and is made of the Al film 46
_The memory cells M such as the memory cells M _{11 to} M ₂₂ are formed by the MIS transistor 47 having the gate electrodes ₁ and W ₂ .

The thin film transistor 48 having the polycrystalline Si film 31 as the active layer and the polycrystalline Si film 34 as the gate electrode G _P allows the switching transistors T _{P11 to} T _P11.
P22 etc. are formed. Then, the plate electrodes P ₁ and P ₂ as the control electrodes for writing and erasing are made of polycrystalline S
It is connected to the end (not shown) of the i film 31.

Next, after collective erasure information of all the memory cells M ₁₁ ~M _22, writes selectively information in the memory cell M _11, the operation of reading the further information from the memory cell M ₁₁ This will be described in order. Table 1 below shows the voltage applied in that case. The power supply voltage V _CC is set to 1.5 V, which is twice the coercive voltage V _C = 0.75 V.

First, in order to collectively erase the information in all the memory cells M _{11 to} M ₂₂ , a voltage is applied as shown in Table 1 to make the switching transistors T _{P11 to} T _P22 conductive. Then, in all the memory cells M _{11 to} M ₂₂ ,
14 is formed between the Al film 46 and the polycrystalline Si films 31 and 41.
The voltage of −2V _C shown in FIG. As a result, FIG.
17, the ferroelectric film 44 is polarized, the threshold voltage of the MIS transistor 47 is shifted to the positive side, and V shown in FIG.
becomes _thE .

[0040]

[Table 1]

In order to selectively write information in the memory cell M ₁₁ , a voltage is applied as shown in Table 1 to make the switching transistors T _{P11 to} T _P22 conductive. Then,
In the memory cell M ₁₁ located at the intersection between the polycrystalline Si film 31 connected to the plate electrode P ₁ and the word line W _{1, the area} between the Al film 46 and the polycrystalline Si films 31 and 41 is The voltage of 2V _C shown in 14 is applied. As a result, the ferroelectric film 44 is polarized as shown in FIG. 8, and the threshold voltage of the MIS transistor 47 shifts to the negative side to _reach V _thW shown in FIG.

However, in the memory cell M ₁₂ located at the intersection between the polycrystalline Si film 31 connected to the plate electrode P ₂ and the word line W ₁ , the Al film 46 and the polycrystalline Si film 3 are formed.
Between 1 and 41, only the voltage of 2V _C / 3 shown in FIG. 14 is applied. Therefore, as shown in FIG. 9, the polarization of the ferroelectric film 44 does not reverse from the erased state, and the threshold voltage of the MIS transistor 47 does not change.

In the memory cell M ₂₁ located at the intersection of the word line W ₂ and the polycrystalline Si film 31 connected to the plate electrode P ₁ , the Al film 46 and the polycrystalline Si film 3 are also included.
Only a voltage of 2V _C / 3 is applied between 1 and 41. Therefore, as shown in FIG. 10, the polarization of the ferroelectric film 44 does not reverse from the erased state, and the threshold voltage of the MIS transistor 47 does not change.

Further, even in the memory cell M ₂₂ located at the intersection of the polycrystalline Si film 31 connected to the plate electrode P ₂ and the word line W ₂ , the Al film 46 and the polycrystalline Si film 3 are formed.
A voltage having the same magnitude as that of the memory cells M ₁₂ and M ₂₁ but opposite polarity is applied between 1 and 41. Therefore, as shown in FIG. 11, the polarization of the ferroelectric film 44 does not reverse from the erased state, and the threshold voltage of the MIS transistor 47 does not change.

FIG. 12 shows the application timing of each voltage when the information is selectively written in the memory cell M ₁₁ as described above. Before the switching transistors T _{P11 to} T _P22 are made conductive by applying the voltage V _CC to the gate electrode G _P , the polycrystalline Si films 31 and 41 are in a floating state,
_Only after the switching transistors T _{P11 to} T _P22 are turned on, the potentials of the plate electrodes P ₁ and P ₂ are transmitted to the polycrystalline Si films 31 and 41.

Therefore, as is apparent from FIG. 12, before the voltage V _CC is applied to the gate electrode G _P , the time when the voltage 2 V _CC / 3 is applied to the plate electrode P ₂ is the word lines W ₁ , W 2. Even if it is deviated from the time when the voltage V _CC / 3 is applied to ₂ , the ferroelectric film 44 of the memory cells M _{12 to} M ₂₂ has 2
Only a voltage of V _C / 3 or less is applied. Therefore, the information in these memory cells M _{12 to} M ₂₂ will not be destroyed unintentionally.

Finally, in order to read information from the memory cell M ₁₁ , a voltage is applied as shown in Table 1 to bring the switching transistors T _{P11 to} T _P22 into a non-conducting state.
Then, the polycrystalline Si films 31 and 41 are in a floating state, and the film thicknesses t _OX and t _{F of the} SiO ₂ film 27 and the ferroelectric film 44 are also included.
Since the relative dielectric constants ε _OX and ε _F have the values as described above, the voltage V _FR applied to the ferroelectric film 44 is V _{FR with} respect to the read voltage V _R = V _CC . = V _R / [1+ (ε _F · t _OX ) / (ε _OX · t _F )] = V _R /3.5641.

Then, as described above, V _R = V _CC = 1.5V
Therefore, from the above equation, V _FR = 0.42V. Therefore, the voltage V _FR applied to the ferroelectric film 44 is 2V _C / 3
= V _CC /3=0.5 V or less, the polarization of the ferroelectric film 44 is not inverted from the written state as shown in FIG. 13, and the information in the memory cell M ₁₁ is destroyed with reading. Absent.

As is apparent from the above description, in the present embodiment, the erase voltage V _E , the write voltage V _W , and the read voltage V
_{Since each of R} is equal to the power supply voltage V _CC = 1.5V, it can be operated at a low voltage. Therefore, the booster circuit and the high breakdown voltage circuit are unnecessary, the area of the peripheral circuit is reduced, and the peripheral circuit forming process is simplified and the number of processes is reduced.

Further, in the structure shown in FIG. 16C, a high electric field is applied to the paraelectric film 15 at the time of erasing and writing, and the metal film 16 is in a floating state, so that the Fowler-Nordheim tunnel is used. The carrier that has passed through the paraelectric film 15 is injected into the metal film 16, and the threshold voltage varies. On the other hand, in the present embodiment, it is possible to operate at a low voltage, and the metal film 42 is the polycrystalline Si film 4
Since it is in contact with Nos. 1 and 31 and is not in a floating state, the threshold voltage does not vary due to carrier injection.

Further, as shown in FIG. 3C, in the polycrystalline Si film 31 which is the active layer of the thin film transistor 48, the portion under the polycrystalline Si film 34 which is the gate electrode G _P has a forward tapered shape. It has become. Therefore, the electric field concentration in this portion is alleviated, and the reliability of the thin film transistor 48 is high.

[0052]

[Effect of the Invention] In the nonvolatile semiconductor memory device according to claim 1, it is possible to perform a predetermined operation using the control electrode to the desired memory cell, Lang even if the memory cells are arranged in a matrix Access is available.

[0053] In the nonvolatile semiconductor memory device according to claim 2,
Since the active layer of the switching transistor and the intermediate electrode can be simultaneously formed in the same process, the manufacturing cost is low.

[0054] In the nonvolatile semiconductor memory device according to claim 3,
Since information is not destroyed during reading and rewriting of information is unnecessary, reading can be performed at high speed. In addition, since the number of effective erase / write operations is small and the ferroelectric film is less deteriorated, the number of rewritable times is large and the life is long.

In the method of using the nonvolatile semiconductor memory device according to the fourth aspect, the information is written only in the selected memory cell, and the information is not written in the unselected memory cells. Further, the information in all the memory cells is erased by the batch erase, and the information in any of the memory cells is not destroyed by the read. Therefore, the reliability of the nonvolatile semiconductor memory device is high.

In the method of using the non-volatile semiconductor memory device according to the fifth aspect , the information in the memory cells other than the selected memory cell is not destroyed when the information is written, so that the write disturb can be prevented.

In the method for manufacturing a non-volatile semiconductor memory device according to a sixth aspect of the present invention, the ferroelectric film and the word line can be easily formed even if the space between the gate electrodes of the switching transistors is small. Even a high nonvolatile semiconductor memory device can be manufactured with a high yield.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of a memory cell array according to an embodiment of the present invention.

FIG. 2 is a plan view of a memory cell array according to an embodiment.

3 shows a memory cell array according to one embodiment, (a), (b) and (c) of FIG. 2 are respectively IIIA-III.
It is a sectional side view in the position which follows the A line, the IIIB-IIIB line, and the IIIC-IIIC line.

FIG. 4 is a side sectional view corresponding to FIGS. 3A and 3B, sequentially showing the initial manufacturing process of the embodiment.

FIG. 5 is a side sectional view corresponding to FIGS. 3 (a) and 3 (b), sequentially showing the middle manufacturing process of one embodiment.

FIG. 6 is a side sectional view corresponding to FIGS. 3 (a) and 3 (b), sequentially showing the final manufacturing process of one embodiment.

FIG. 7 is a conceptual diagram of memory cells M _{11 to} M ₂₂ when erasing information.

FIG. 8 is a conceptual diagram of a memory cell M ₁₁ when writing information.

FIG. 9 is a conceptual diagram of the memory cell M ₁₂ at the time of writing information.

FIG. 10 is a conceptual diagram of the memory cell M ₂₁ at the time of writing information.

FIG. 11 is a conceptual diagram of a memory cell M ₂₂ when writing information.

FIG. 12 is a graph showing a voltage application timing at the time of writing information.

FIG. 13 is a conceptual diagram of a memory cell M ₁₁ when reading information.

FIG. 14 is a graph showing an example of a hysteresis characteristic of a ferroelectric substance.

FIG. 15 is an equivalent circuit diagram of a memory cell in a first type semiconductor memory device using a ferroelectric substance.

FIG. 16 shows a second type semiconductor memory device using a ferroelectric substance, (a) is an equivalent circuit diagram of a memory cell,
(B) is a side sectional view of a MIS transistor forming a memory cell, and (b) is a side sectional view of a MIS transistor having another structure forming a memory cell.

FIG. 17 is a graph showing a change in threshold voltage in a MIS transistor of a semiconductor memory device using a ferroelectric substance.

FIG. 18 is an equivalent circuit diagram of a memory cell array of a second type semiconductor memory device using a ferroelectric.

[Explanation of symbols]

27 SiO ₂ film 31 Polycrystalline Si film 34 Polycrystalline Si film 41 Polycrystalline Si film 43 SiO ₂ film 44 Ferroelectric film 46 Al film 47 MIS transistor M ₁₁ memory cell M ₁₂ memory cell M ₂₁ memory cell M ₂₂ memory cell W ₁ word line W ₂ word line T _P11 switching transistor T _P12 switching transistor T _P21 switching transistor T _P22 switching transistor P ₁ plate electrode P ₂ plate electrode

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ identification code FI H01L 29/792 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/8247 G11C 11/22 G11C 11/404 H01L 27/105 H01L 29/788 H01L 29/792 JISC file (JOIS)

Claims (6)

(57) [Claims] 1. A gate insulating film composed of a ferroelectric film on the gate electrode side and a paraelectric film on the channel region side.
A memory cell is formed by the IS transistor, and the plurality of memory cells are arranged in a matrix,
In a nonvolatile semiconductor memory device in which the gate electrodes of the MIS transistors arranged in a row direction are connected to each other to form a word line, an intermediate electrode is provided between the ferroelectric film and the paraelectric film. A switching transistor is provided in each of the plurality of memory cells, the intermediate electrode is connected to the control electrode via the switching transistor, and the switching transistor is arranged in a column direction. A non-volatile semiconductor memory device having a source / drain connected in series with each other. 2. The switching transistor is a thin film transistor, and an active layer of the thin film transistor and the intermediate electrode are formed of a semiconductor film in the same layer.
1. The nonvolatile semiconductor memory device according to 1. 3. Of the read voltages applied between the channel of the MIS transistor and the word line for reading the information of the memory cell, the voltage applied to the ferroelectric film is the ferroelectric substance. as it is smaller than the coercive voltage of the film, according to claim 1, characterized in that the specific permittivity and the thickness of the ferroelectric film and the paraelectric film is set
The nonvolatile semiconductor memory device described. 4. All the switching transistors are made conductive, and a voltage larger than the coercive voltage of the ferroelectric film is applied between all the word lines and all the control electrodes. Erases the information in all the memory cells at once, and makes all the switching transistors conductive.
A voltage, which is larger than the coercive voltage and has a polarity opposite to that of the collective erase, is applied between the first word line and the first control electrode which intersect each other in the selected memory cell, A voltage between the first word line and the first control electrode is lower than the coercive voltage and is applied to the second control electrodes other than the first control electrode. By applying a voltage smaller than the coercive voltage to a second word line other than the first word line, information is written in the selected memory cell, and all the switching transistors are made non-conductive. 4. The non-volatile semiconductor memory device according to claim 3 , wherein information is read from the selected memory cell by applying the read voltage to the word line passing through the selected memory cell. How to use. 5. In the writing, a voltage having a voltage between the first control electrode and the first control electrode is lower than the coercive voltage is applied to the first and second word lines, and at the same time, the first and second word lines are applied. A voltage having a voltage between the first control electrode and the word line is higher and a voltage between the first and second word lines is lower than the coercive voltage is applied to the second control electrode. After all the switching transistors are turned on, the voltage between the second control line and the first control electrode is higher than the second word line and higher than the coercive voltage. 5. The method of using a nonvolatile semiconductor memory device according to claim 4, wherein a voltage having a voltage between the two is smaller than the coercive voltage is applied to the first word line. 6. A step of forming gate electrodes of the switching transistors in a row direction, a step of forming a sidewall made of a first insulating film on the gate electrodes of the switching transistors, the first insulation A step of forming a conductive film that contacts the active layer between the films and fills the recesses between the first insulating films; a step of dividing the conductive film into columns; and a recess between the divided conductive films. after the filling with a second insulating film, according to claim 2, characterized in that it comprises a step of forming the ferroelectric film and said word lines in the upper layer of conductive film and the second insulating film Manufacturing method of non-volatile semiconductor memory device.