JPH1194928A - Automatic gain control circuit of radar receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the AGC circuit of a radar receiver wherein the good image of a small error can be obtained even in the case where large fluctuation occurs in a receiving level. SOLUTION: After a receiving pulse signal output from a variable gain amplifier 101 increasing and decreasing the gain of the receiving pulse signal in response to input data is logarithmically compacted and detected with a detector 104, it is converted into a true value and the average value of a receiving pulse signal level is found. The average value is logarithmically converted to find an error with an error calculation circuit 116, and the feedback of the error is performed to input it to the variable gain amplifier 101.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used, for example, in a radar receiver in which the input signal level varies over a wide range, and which automatically controls a received signal to reference data (hereinafter referred to as AGC (Automatic Gain Control)). Circuit).

[0002]

2. Description of the Related Art Generally, as shown in FIG. 7, a radar receiver comprises an antenna 1 for receiving a reflected pulse wave transmitted from the ground, a first amplifier 2 for amplifying a pulse-like received signal,
Amplified received signal and externally applied frequency signal R
A mixer 3 for mixing the X-CW with the X-CW and converting it to an intermediate frequency, a predetermined STC-ATT externally supplied with the intermediate frequency signal
A variable attenuator 4 for setting gain by performing STC (Sensitivity Time Control) correction with a signal, and a signal output unit 8 for converting an intermediate frequency signal into an AGC-ATT signal.
A variable gain amplifier 5 for controlling the output level of the variable gain amplifier 5 to a reference level, a splitter 6 for splitting the output of the variable gain amplifier 5 into two systems of a signal output unit 8 and an AGC circuit 20, and a desired output level of the variable gain amplifier 5. And an AGC circuit 20 that generates a gain control signal to keep the received signal, and a signal output unit 8 that outputs the input received signal to the image processing apparatus. Variable gain amplifier 5
Is realized by a digital attenuator, and the gain control signal AG
C-ATT is generally provided in a data format.

The AGC circuit 20 includes a variable gain amplifier 5
The gain control signal AG is supplied to the variable gain amplifier 5 so that the output level of the
It generates and outputs C-ATT (hereinafter, gain control signal), and is specifically configured as shown in FIG.

In FIG. 8, a power monitor circuit 31 is shown.
Converts the received signal into a DC signal. The A / D (analog / digital) conversion circuit 32 samples the level of the DC component (hereinafter, referred to as a power monitor signal) of the received signal obtained by the power monitor circuit 31 at a plurality of timings during one received pulse. And convert it to digital data. The integration circuit 33 sequentially adds the signal levels of the power monitor signal obtained during one pulse. The integration circuit 33 includes an addition circuit 34 and a latch circuit 35. The power monitor signal converted into digital data from the A / D conversion circuit 32 and the immediately preceding data latched by the latch circuit 35 are stored in the integration circuit 33. Are added by the adding circuit 34, and the addition result is latched in the latch circuit 35, so that the power monitor signals are sequentially added. The data obtained by the integration circuit 33 is sent to a PROM (programmable read only memory) circuit 36.

The PROM circuit 36 determines the average power level of the power monitor signal from the added data, generates a gain control signal corresponding to this level,
AGC control is performed according to the output.

[0006]

A conventional AGC circuit 20
Since the power monitor signal, that is, the DC component of the received signal is connected to the input of the A / D conversion circuit 32, when a DC offset occurs due to a change in environmental conditions (for example, ambient temperature), the error component is large. Since the power monitor signal is converted into a digital signal, the gain control signal output from the PROM circuit 36 becomes data containing many errors.

Further, since the A / D conversion circuit 32 directly inputs the power monitor signal from the variable gain amplifier 5, a signal exceeding the dynamic range of the input analog signal of the A / D conversion circuit 32 is generated. A / D conversion circuit 32
And if the output of the A / D conversion circuit 32 is obtained in a binary number, all output bits are "0" or "0".
1 ", and the gain control of the variable gain controller 5 for the received signal falls into a fixed state. Therefore, in this case, only a very limited range of the power monitor signal level can be gain controlled, so that the gain can be controlled over a wide range. In the received signal that changes to the level, the gain control function corresponding to it is lost,
This results in S / N deterioration of the observation signal.

A power monitor signal output from the A / D conversion circuit 32 is input to an integration circuit 33 composed of an addition circuit 34 and a latch circuit 35 for integration and the number of integrations can be varied. Since the signal indicating the number of integrations is not connected to the PROM circuit 36 that outputs the gain control data, the reception level obtained as the calculation result is a large value when the power monitor signal of a low level is integrated very many times. As a result, a correct reception level cannot be detected. Since the gain control signal output from the PROM circuit 36 is not input to the PROM circuit 36, the PROM circuit 36 calculates only the signal level integrated value of the currently received signal. In the reflected wave observation of, correct gain control cannot be performed due to the difference in the radar reflection coefficient of the object to be observed.

An object of the present invention is to provide a radar receiver,
An object of the present invention is to provide an AGC circuit capable of obtaining a good image with a small error even when a large fluctuation occurs in the reception level.

[0010]

An AGC circuit according to the present invention for solving the above problems controls the level of a pulse-like received signal received by a radar receiver by a predetermined gain control signal. First means for extracting a change characteristic of a signal level of logarithmic data obtained by logarithmic compression and amplification;
A second means for generating average log data representing an average value of the extracted change characteristics; and a third means for generating the gain control signal at a level for canceling an error component between the generated average log data and predetermined reference data. Means are provided.

The first means has, for example, a dynamic range of the same input level range as the gain control range of the automatic gain control circuit, and a logarithm such that its output value does not exceed the input range of the analog / digital conversion circuit. It comprises a logarithmic compression amplifier for compression.

The second means may be an analog / digital conversion circuit for sampling the logarithmic data and converting the logarithmic data to digital data, and a logarithmic / true value conversion for converting the digitally converted logarithmic data to true number data. Circuit, averaging means for averaging the converted antilog data based on the number of samplings, and a true / log value conversion circuit for inversely converting the averaged antilog data to generate average log data. Be composed. In this case, the averaging means sequentially adds the antilog data obtained during the observation period of the received signal, and divides the addition result by the number of times of addition to obtain the averaged antilog data. Configure to output.

The third means calculates, for example, an error between the average logarithmic data and the reference data during the observation period, and adds / subtracts the error to a gain control signal in the previous observation period which is input as feedback. By doing so, it is configured to include gain control signal generation means for generating a gain control signal. The gain control signal generating means has, for example, a ROM in which a relation value between a signal level of a current reception signal and a previous gain control signal is recorded, and is configured to output a corresponding relation value from the ROM. .

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration example of an AGC circuit 20 according to the present invention applied to the radar receiver shown in FIG. In FIG. 1, a variable gain amplifier 10
1, the received signal amplified to the reference level for the signal output unit 8 is demultiplexed by the coupler 102, input to the logarithmic compression amplifier 103, converted into a logarithmically compressed signal (hereinafter, logarithmic data), and output. Is done. The logarithmic data is detected by the detector 104 to extract a change characteristic of the signal level. The detected received signal is A /
The signal is input to the D converter 105 and is converted into a digital signal.
The converted received signal is input to logarithmic value / true value conversion circuit 106 and is converted to an antilog value. The received signal converted into an antilog is added in adder 107. Adder 107
The result of the addition of the received signal, which is the output of, is divided by the number of additions in the divider 112, and the average value of the received signal is output. The average value of the received signal is calculated by a true value / log value conversion circuit 114.
Is converted to a logarithmic value (hereinafter, average logarithmic data),
It is input to the error calculation circuit 116.

The error calculation circuit 116 calculates the deviation between the average logarithmic data and the preset reference data, and outputs the error calculation circuit 116 latched by a flip-flop circuit (hereinafter referred to as F / F) 117, The gain control signal is fed back to the error calculation circuit 116, and the gain control signal is added to or subtracted from the previous gain control signal by the amount of the shift, a gain control signal is output, and the gain control signal is output to the variable gain amplifier 101 as an AGC-ATT signal.

The function of each section will be described below in more detail.
The logarithmic compression amplifier 103 converts and amplifies a received signal into logarithmic data, and the dynamic range of the logarithmic compression amplifier 103 covers a gain control range value necessary for the AGC circuit 20. The output of the logarithmic compression amplifier 103 is set so as not to exceed the input range of the analog / digital conversion circuit. An example of the output characteristics of the logarithmic compression amplifier 103 is shown in FIG.
Shown in However, for the following description, the variable gain amplifier 10
It is assumed that the output value of 1 is a characteristic at 40 dB.

FIG. 3 shows that when the input of the logarithmic compression amplifier 103, that is, the output of the variable gain amplifier 101 changes from +20 dB to −20 dB, the logarithmic compression amplifier 103
Shows that the output changes linearly from 0V to 4V. The detector 104 detects logarithmic data from the logarithmic compression amplifier 103 and extracts an amplitude component of the received signal.
As shown in FIG. 2, the output of the detector 104 is a pulse signal. The A / D converter 105 converts the amplitude component of the extracted log data into a digital value (binary number). Thus, the level of the sampled received signal is detected as a logarithmic value.

Here, the number of bits required for the A / D converter 105 depends on the gain control accuracy required for the AGC circuit 20 in a change in the output voltage of the logarithmic compression amplifier 103 used. For example, ± 1 dB gain control accuracy
Is required, the output voltage change amount of the logarithmic compression amplifier 103 at the time of a 1 dB input change is determined to be a value that can be detected by the A / D converter 105. In the example of FIG.
The reference voltage of the D converter 105 is 10 V, and the required number of bits is “8”.

The logarithmic value / true value conversion circuit 106 converts the logarithmic data converted into a digital value into a true number (binary number). This is to convert a digital value detected as a logarithmic value into a true value in order for the adder 107 to add the received signal level, and is realized using, for example, a ROM (Read Only Memory).

The input addresses of the ROM (106R) include:
The converted digital value is input from the A / D converter 105, and a converted true value corresponding to the input address value is output. The true value Y to be output is calculated as follows: Y = 10Λ (C × X) where X is the input address value. The symbol Λ indicates a power. The symbol C is a value determined according to the nonlinearity of the output voltage of the logarithmic compression amplifier 103, and is changed according to the hardware. FIG. 4 shows an example of data in the ROM (106R).

In the example of FIG. 4, since the analog input voltage of the A / D converter 105 corresponds to 10 V and the output is 8 bits, the input range of the ROM (106R) is
The value ranges from “0” to “255”. ROM output value (10
If the base number) is Y and the ROM input address value (decimal number) is X, the output true value is represented by the following equation. Y = 10Λ (X × 10 VOLT / 256)

Since the output of the logarithmic compression amplifier 103 is assumed to be saturated at 4 V above the input address "102", the ROM output is fixed at "9732." The input addresses “0” and “102” correspond to the inputs “0” and “4” of the A / D converter 105, respectively. The number of bits required to represent the ROM output value "9732" is at least 14 bits.

As one example, the adder 107 is provided with an F / F 109 at the output of the full adder 108 having two inputs, and outputs the output of the logarithmic value / true value conversion circuit 106 as one input of the full adder 108. Connect F / F10 as the other input
9 output is connected. The number of additions in the adder 107 is determined by the product of the number of samplings in one pulse signal period and the received signal in the observation period, as shown in FIG. The trigger signal 111 is input to the F / F 109. Note that the sample trigger signal 111 input to the F / F 109 has the same frequency as that of the sample trigger signal 111 input to the A / D converter 105 (is out of phase?). Further, the number of bits required for the full adder 108 needs to have a number of bits at which the digit of the full adder 108 does not overflow even if the maximum level of the received pulse signal is added the maximum number of times.

The counter 110 gives the number of times of addition in the adder 107 to the divider 112. Divider 112 divides the total added value of the signal levels of the received signal output from adder 107 by the total number of additions to obtain an average value of the received signal. For the total number of additions, the trigger signal input to the F / F 109 is counted by the counter 110. If the total number of additions is set to be a multiple of 2, the operation of shifting the output of the adder 107 to the 1-bit LSB side is equivalent to dividing by 2 so that the structure of the divider 112 is simplified. Can be In this case, the divider 112 can be realized by connecting a necessary number of data selectors of n: 1 in parallel.

The true value / log value conversion circuit 114 is provided with a divider 1
It converts the average value of the twelve output received signals into a logarithmic value (binary number), that is, average logarithmic data, and is realized using, for example, a ROM (114R). ROM
The average value of the received signal that is a true value is input to the input address of (114R). The output average log data Y is
Assuming that the input address value is X, it is calculated as Y = 10log (10) X. FIG. 5 shows an example of data in the ROM (114R). However, the numerical values to be set are based on the examples in FIGS. The data input to the ROM (114R) is assumed to be output from the ROM (106R) used in the logarithmic value / true value conversion circuit 106 shown in FIG. The data structure may be obtained by reversing the input / output relationship of the ROM (106R). For example, when the ROM input address in FIG. 5 is “9732”, “4” is used as the average log data.
0 ". To represent this average log data,
Six bits are required.

The error calculation circuit 116 calculates an error amount (logarithm) between the average logarithmic data and a logarithmic value (hereinafter referred to as reference data) indicating the reference level output from the variable gain amplifier 101 as R.
Operation is performed using the OM (116R), and the gain control signal 115
Is output. The average logarithmic data is input to the input address of the ROM (116R), and a new gain control signal whose error has been corrected is output. Note that this gain control signal is F / F
It is latched at 117 and is fed back to the input address side of the error calculation circuit 116. The output (logarithm) Y of the error calculation circuit 116 changes under the following conditions, where X is the average logarithmic data and α is the reference data. Where d = | α−X |
And

(1) In the case of (α−X = 0), the reception level is the expected value α, and the output Y does not change its setting. (2) If (α−X> 0), the reception level is smaller than the expected value α, and the output Y is (Y−X> 0).
d). (3) In the case of (α−X <0), the reception level is higher than the expected value α, and the output Y is (Y +
d).

FIG. 6 shows an example of data in the ROM (116R). The average log data input to the ROM (116R) is 6 bits from FIG.
Since the output of the ROM (116R) is feedback-connected to the input of R), the number of bits of the input address signal is
12 bits are required. Here, if the reference level is 4 V at the output of the logarithmic compression amplifier 103, the data shown in FIG. 6 is output. Please note that due to space limitations,
Although omitted, the numerical value decreases to 0 rightward by one. As an example, the ROM (116R) in the case where the average logarithmic data is input to the upper 6 bits of the input address of the ROM (116R) and the output of the F / F 117 connected in feedback to the lower 6 bits of the input address. When the average logarithmic data is “40” and the gain control signal previously set is “40”, the output becomes “40” from FIG. 6, and the gain control signal output to the variable gain amplifier 101 is
It becomes “40”.

The F / F 117 holds the output of the error calculation circuit 116, outputs a gain control signal to the variable gain amplifier 101, and feeds back the error control circuit 116.
A latch signal 118 input to the F / F 117
Is input after the necessary total number of additions in the adder 107 has elapsed, as shown in FIG. The gain control signal held in the F / F 117 performs AGC control on the variable gain amplifier 101.

Next, the operation of the AGC circuit of this embodiment will be described. The graph shown in FIG. 3 shows the output characteristics of the logarithmic compression amplifier 103 when the output value of the variable gain amplifier 101 is 40 dB. Further, as setting conditions, it is assumed that the input of the variable gain amplifier 101 changes from +20 dBm to −20 dBm, the reference voltage of the A / D converter 105 is 10 V, and the output is a digital value represented by 8 bits. AGC control is performed on the output of the variable gain amplifier 101 so that the output of the logarithmic compression amplifier 103 becomes 4 V. At this time, the input of the variable gain amplifier 101 is +20.
It is assumed that the output of the logarithmic compression amplifier 103 is saturated at a little over 4 V above dBm. The gain control signal (data) used for AGC control of the variable gain amplifier 101 is 6 bits.

The number of output bits required for the ROM (106R) is at least 14 bits, and the input address of the ROM (114R) also requires 14 bits. 4 and 5 show data examples of the ROM (106R) and the ROM (114R), respectively. FIG. 6 shows an example of data in the ROM (116R).

Error calculation circuit 11 under the above set conditions
6 will be described. The previously set gain control signal is "4
When the current logarithmic data is “40” and the current average log data is “40”, the new gain control signal output from the ROM (116R) is, as shown in FIG. 6, the upper 6 bits “40” and the lower 6 bits “40”. The latch signal input from the radar receiver system control unit is input after the necessary total number of additions in the adder 107 has elapsed, as shown in FIG. With this latch signal, the F / F 117 holds the output ("40" in this case) of the ROM (116R), outputs it as a gain control signal to the variable gain amplifier 101, and performs AGC operation (here, gain). The value of the control signal is given as an attenuation.)

If the object to be observed changes and the average log data changes to "33", the gain control signal previously set is "40". "3" which is an intersection with 6-bit "40"
3 "is newly selected and becomes a ROM (116R) output. When a latch signal is input to the F / F 117, the currently selected" 33 "is latched by the F / F 117 and the ROM (116R) is output.
At the same time as the feedback input to the lower 6 bits of (116R), this data becomes a gain control signal (AGC-ATT) and changes the gain of the variable gain amplifier 101. At this time, the attenuation of the variable gain amplifier 101 is changed from “40” to “3”.
3 ”, the level of the received signal rises, and the average log data for the next observation period is 33+ (40−33) =
It will be 40.

In this observation period, the average logarithmic data has changed to "40" and the gain control signal previously set is "33".
"33", which is the intersection of 0 and the lower 6 bits "33", is newly selected and becomes the ROM (116R) output.When the latch signal is input to the F / F 117, the currently selected "33" is output. Is latched by the F / F 117 and the ROM
At the same time as the feedback input to the lower 6 bits of (116R), this data becomes a gain control signal (AGC-ATT). Since the gain control signal does not change, the level of the received signal does not change, so that the AGC control is stabilized. Through this series of operations, the output of the variable gain amplifier 101 is always kept constant within the control range of the error calculation circuit 116.

As described above, in the AGC circuit of the present embodiment, the output of the logarithmic compression amplifier 103 is configured to extract only the amplitude component of the received signal by the detector 104 and the influence of the DC offset is eliminated. It is possible to reduce the error of the control signal.

Further, even if the received signal is logarithmically compressed by the logarithmic compression amplifier 103 and the level of the received signal changes over a wide range,
Since the dynamic range of the input signal of the A / D converter 105 is not exceeded, the A / D converter 105 does not saturate at the level at which the logarithmic compression amplifier 103 is saturated.
The output value unit is (dB), and the level of the received signal can be instantaneously determined. Further, since the gain control does not fall into a fixed state, the S / N ratio of the observation signal does not deteriorate.

In the sampling of the received signal a plurality of times, a function of dividing the integrated value of the received signal by the number of samplings is provided, and the gain is calculated after the average value is obtained. It does not fluctuate significantly.

In the error calculation circuit 116 for calculating the gain control signal, two signals are input. One of the inputs is a gain control signal of a previously set gain that has produced the reception level currently being received. Is the average value (average log data) of the current received signal in the gain control state set last time
Therefore, correct gain control can be performed for a received pulse signal from the object to be observed having any radar reflection coefficient.

As described above, even when the level of the received signal fluctuates greatly, the problem that the swell occurs in the observed signal is solved because the level is continuously integrated and averaged during the observation time. If the dynamic range of the input level is the same as the AGC control range of the variable gain amplifier 101, the gain control element does not stick to the maximum or minimum state, so that the reception level can be set appropriately. And an AGC circuit for a radar receiver capable of obtaining a good image.

[0040]

As is apparent from the above description, according to the present invention, there is an effect that a good image with few errors can be obtained in a radar receiver.

[Brief description of the drawings]

FIG. 1 shows an AG of a radar receiver according to an embodiment of the present invention.
FIG. 2 is a block diagram of a C circuit.

FIG. 2 is a timing chart for explaining the operation of the AGC circuit according to the embodiment;

FIG. 3 is a diagram showing characteristics of the logarithmic amplification compressor when the output value of the variable gain amplifier of the AGC circuit according to the embodiment is 40 dB.

FIG. 4 is an explanatory diagram showing an example of data in a ROM used in a logarithmic value / true value conversion circuit.

FIG. 5 is an explanatory diagram showing an example of data in a ROM used in a true value / log value conversion circuit.

FIG. 6 is an explanatory diagram showing an example of data in a ROM used for an error calculation circuit.

FIG. 7 is a block diagram showing a configuration example of a radar receiver to which the present invention is applied.

FIG. 8 is a block diagram of a conventional AGC circuit.

[Explanation of symbols]

 Reference Signs List 10 automatic gain control circuit (AGC circuit) 101 variable gain amplifier 102 coupler 103 logarithmic compression amplifier 104 detector 105 A / D converter 106 logarithmic / true value conversion circuit 107 adder 108 full adder 109, 117 flip-flop circuit (F / F) 110 counter 112 divider 114 true value / log value conversion circuit 116 error calculation circuit

Claims (6)

[Claims] 1. An automatic gain control circuit for controlling the level of a pulse-like received signal received by a radar receiver by a predetermined gain control signal, wherein the signal level of logarithmic data obtained by logarithmically compressing and amplifying the received signal is provided. First means for extracting a change feature; second means for generating average log data representing an average value of the extracted change features; and canceling an error component between the generated average log data and predetermined reference data. Automatic gain control circuit for a radar receiver, comprising: third means for generating the level of the gain control signal. 2. The automatic gain control circuit according to claim 1, wherein the first means has a dynamic range of the same input level range as a gain control range of the automatic gain control circuit, and has a logarithmic scale so that an output value thereof does not exceed an input range of the analog / digital conversion circuit. 2. The automatic gain control circuit according to claim 1, further comprising a logarithmic compression amplifier for performing compression. 3. An analog / digital conversion circuit for sampling said logarithmic data and converting the logarithmic data to digital data, and a logarithmic / true value conversion for converting the digitally converted logarithmic data to antilogarithmic data. Circuit, averaging means for averaging the converted antilog data based on the number of samplings, and a true / log value conversion circuit for inversely converting the averaged antilog data to generate average log data. 2. The automatic gain control circuit according to claim 1, wherein 4. The averaging unit according to claim 1, wherein the averaging unit sequentially adds the antilog data obtained during an observation period of the received signal, and divides the addition result by the number of times of addition to obtain the averaged antilog number. 4. The automatic gain control circuit according to claim 3, wherein the automatic gain control circuit is configured to output data. 5. The third means calculates an error between the average logarithmic data and the reference data during the observation period, and adds and subtracts the error to a gain control signal in a previous observation period which is input as feedback. 2. The automatic gain control circuit according to claim 1, further comprising gain control signal generating means for generating a gain control signal. 6. The gain control signal generating means has a ROM in which a relation value between a signal level of a current reception signal and a previous gain control signal is recorded, and outputs a corresponding relation value from the ROM. 6. The automatic gain control circuit according to claim 5, wherein the automatic gain control circuit is configured.