JPH06174826A - Automatic gain control circuit of radar receiver - Google Patents

Abstract

PURPOSE:To provide an automatic gain control circuit of a radar receiver wherein a receiving level can be properly set even when a level change is remarkable within a single receiving pulse. CONSTITUTION:This automatic gain control circuit of a radar receiver feeds a gain setting data for inputting a power monitor signal detected from a DC component of a receiving pulse signal outputted from a variable gain amplifier to bring the receiving pulse signal to a proper level with respect to the variable gain amplifier for increasing/decreasing a gain of the receiving pulse signal in accordance with an input data. An A/D conversion circuit 18 samples levels of the power monitor signal at plural times in a single receiving pulse period and converts them into digital data. An integration circuit 19 sequentially adds data obtained in the pulse period. A PROM circuit 22 determines an average power level of the power monitor signals from the added data to generate a proper gain setting data in correspondence with this level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic gain control circuit which is used in a radar receiver such as a synthetic aperture radar and which automatically controls a received pulse to an appropriate level.

[0002]

2. Description of the Related Art Generally, a radar receiver such as a synthetic aperture radar is constructed as shown in FIG. In FIG.
Reference numeral 1 denotes an antenna, which receives a transmitted pulse reflected wave from the ground surface or the like. After this received pulse is amplified by the amplifier 2,
The mixer 3 mixes the frequency signal RX-CW1 and converts it into an intermediate frequency.

The received pulse whose frequency has been converted is input to the first variable attenuator 4 and the STC (Sensitivity Time C
ontrol: Sensitivity time control) Receives gain setting by correction (correction amount can be changed by STC-ATT signal given from the outside). The received pulse output from the first variable attenuator 4 is input to the second variable attenuator 5 and the AG
C (Automatic Gain Control) -ATT
The gain setting by the signal is received and converted to an appropriate level.

The received pulse output from the second variable attenuator 5 is demultiplexed into two systems by the hybrid demultiplexer 6, one of which is converted into a DC signal by the power monitor circuit 7 which is a diode and is then converted into the AGC circuit 8. And the other is supplied to the output unit 9.

Here, the AGC circuit 8 discriminates the DC level of the received pulse through the power monitor circuit 7, and the second variable attenuator 5 is set so that this level becomes an appropriate level.
The gain control signal AGC-ATT is generated and output. The second variable attenuator 5 is generally realized by a digital attenuator, and the gain control signal AGC-ATT is generally given in a data format.

Further, the output unit 9 splits the input received pulse by the hybrid duplexer 10 with a phase difference of 90 ° into two systems. Then, one of the demultiplexed outputs is output to the mixer 11
Then, the modulated component is extracted by mixing with the frequency signal RX-CW2 and amplified by the amplifier 12 to obtain the I video signal. Similarly, the other demultiplexed output is mixed by the mixer 13 with the frequency signal RX-C
A modulation component is extracted by mixing with W2 and amplified by an amplifier 14 to obtain a Q video signal. These I and Q video signals are subjected to image processing according to the purpose by an image processing device (not shown) in the subsequent stage, and are appropriately displayed on a display (not shown).

By the way, the above-mentioned AGC circuit is conventionally constructed as shown in FIG.

In FIG. 11, the sample hold circuit 1
The DC component (hereinafter, referred to as a power monitor signal) of the received pulse obtained by the power monitor circuit 7 is supplied to 5. As shown in FIG. 12A, the DC level of the power monitor signal is affected by the ground reflection, and the level is changed.

The sample and hold circuit 15 is shown in FIG.
As shown in (b), one predetermined point is sampled from the power monitor signal. This sample signal is A
Is supplied to the / D (analog / digital) conversion circuit 16,
It is converted into digital data at the timing shown in FIG. 12 (c) and converted to PROM (programmable read only
It is sent to the memory circuit 17.

In this PROM circuit 17, appropriate gain control data for sample data is registered in a table in advance. That is, when the PROM circuit 17 receives the sample data from the A / D conversion circuit 16,
The appropriate aptitude gain setting data is selected at the timing shown in FIG. This data is sent to the second variable attenuator 5 as an AGC-ATT signal.

However, in the conventional automatic gain control circuit as described above, since only one point where the power monitor signal is seen, the level fluctuation of the entire power monitor signal cannot be grasped and the accurate gain control cannot be performed.

That is, since a certain point of the power monitor signal is sampled and the gain of the received pulse is set so that this sample level becomes an appropriate level, the DC level of the received pulse is high overall, If the level of the sample point is low, the gain will be increased. As a result, the received pulse is saturated as a whole, and the portion where the received level is high has a value lower than the actual level.

On the contrary, when the level of the sample point is high, the gain is reduced although the direct current level of the received pulse is low overall. As a result, the received pulse becomes low as a whole, and it becomes difficult to reproduce the video signal due to lack of gain in the portion where the received level is low.

In any case, the S / N ratio of the image is lowered in the subsequent image processing, and in extreme cases, the image data may not be practically usable.

[0015]

As described above, in the conventional automatic gain control circuit of the radar receiver, since only one point of the received pulse power monitor signal is seen, the level fluctuation of the entire power monitor signal can be grasped. I can't
I couldn't control the gain accurately. For this reason, when the received data is image-processed, saturation of the data due to saturation and a decrease in the data level due to insufficient gain occur, which causes brightness and darkness of the image brightness and deterioration of the S / N ratio.

The present invention has been made in order to solve the above problems, and the reception level can be set appropriately even when the level fluctuation within one pulse of the reception pulse signal is severe, whereby a good image can be obtained. It is an object of the present invention to provide an automatic gain control circuit for a radar receiver that can obtain the above.

[0017]

According to the present invention, a variable gain amplifier which increases or decreases the gain of a received pulse signal according to input data is detected from a DC component of a received pulse signal output from the variable gain amplifier. In an automatic gain control circuit of a radar receiver for inputting a power monitor signal and supplying gain setting data for adjusting the received pulse signal to an appropriate level, one pulse period of the received pulse signal by inputting the power monitor signal An analog / digital conversion circuit that samples the level at a plurality of timings and converts it into digital data, an integration circuit that sequentially adds the digital data obtained during the pulse period, and the output data of this integration circuit Gain that calculates the average power level of the power monitor signal and generates appropriate gain setting data corresponding to this level Configured by comprising a constant data generating means.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a basic configuration of an AGC circuit 8 according to the present invention, which is applicable to the radar receiver shown in FIG.

In FIG. 1, the A / D conversion circuit 18 is shown in FIG.
The power monitor signal of the received pulse signal obtained by the power monitor circuit 7 of 0 is input, and two or more points are sampled during one pulse period and converted into digital data. This digital data is sent to the integrating circuit 19.

The integrator circuit 19 is composed of an adder circuit 20 and a latch circuit 21, and the adder circuit 20 adds the data from the A / D converter circuit 18 and the previous data latched by the latch circuit 21, The addition result is latched by the latch circuit 21.
The data sampled during one pulse period is sequentially added by latching the data in the pulse. The data obtained by the integrating circuit 19 is sent to the PROM circuit 22.

The PROM circuit 22 takes in the integrated data from the integrating circuit 19 at the end of one pulse period, obtains the average power level of the received pulse from this integrated data, and selects the appropriate gain setting data corresponding to this level. , AGC-ATT signal is sent to the second variable attenuator 5 in FIG.

That is, in the AGC circuit 8 having the above configuration,
When receiving the power monitor signal as shown in FIG.
In the A / D conversion circuit 18, a large number of sample points are set within one pulse period at the timing shown in FIG. 2B, are sequentially converted into digital data, and are sent to the integration circuit 19. The integrating circuit 19 sequentially adds the sample data. Then, as shown in FIG. 2C, the PROM circuit 22 obtains the average power level within one pulse period from the integration result of the integrator circuit 19, selects the appropriate aptitude gain setting data, and sets the gain of the next reception pulse. I do.

As described above, in the AGC circuit 8 having the above configuration, a plurality of sample points are set, the average power level is obtained from the addition result of all the sample data, and the gain setting data is selected. Compared with the conventional circuit in which only the points are sampled, the reception level can be set appropriately even when the level fluctuation within one pulse of the reception pulse signal is severe. As a result, when the received data is image-processed, the saturation of the data due to saturation and the reduction of the data level due to insufficient gain are suppressed, and the occurrence of the brightness of the image and the deterioration of the S / N ratio are prevented. An image is obtained.

The present invention is not limited to the above embodiment, but is more effective if it is constructed as follows, for example.

FIG. 3 shows an example in which the number of sample points of the A / D conversion circuit 18 can be externally controlled by a command. The sample number control circuit 23 is added to the A / D conversion circuit 18. . This sample number control circuit 2
When receiving a sample point number setting command from the outside, 3 converts the sample clock frequency into a frequency corresponding to the specified point number.

According to this configuration, for example, as shown in FIG. 4, if the command "3" is given to the sample number control circuit 23, the A / D conversion timing can be set three times within one pulse period. If "5" is given, it can be set five times within one pulse period. As a result, the number of samples can be set according to the degree of fluctuation of the reception level, and the load of the circuit operation can be appropriately reduced according to the reception situation.

FIG. 5 shows an example in which the sample timing of the A / D conversion circuit 18 can be externally command-controlled, and a sample point selection circuit 24 is added to the A / D conversion circuit 18. This sample point selection circuit 2
Reference numeral 4 includes a PROM circuit 25 and a timing control circuit 26.

A plurality of sample timing data are registered in advance in the PROM circuit 25, and when a sample timing selection command is given from the outside, the corresponding timing data is sent to the timing control circuit 26.
The timing control circuit 26 generates an A / D timing signal at a timing based on the input timing data and sends it to the A / D conversion circuit 18.

According to this configuration, the sample timing of the A / D conversion circuit 18 can be externally command-controlled, and the load of circuit operation can be appropriately reduced according to the reception situation.

FIG. 6 shows a sample interval of the A / D conversion circuit 18 which can be externally controlled by a command.
A sample interval control circuit 27 for the A / D conversion circuit 18
Is added. This sample interval control circuit 27
Receives a sample interval setting command from the outside, A /
Generate D timing signals at specified intervals.

With this configuration, for example, as shown in FIG. 7, when the command "1" is given to the sample interval control circuit 27, the interval of the A / D timing signal is narrowed and the command "2" is given. Can be wider if As a result, the load of circuit operation can be appropriately reduced according to the reception status.

FIG. 8 shows an arrangement in which the sample timing of the A / D conversion circuit 18 can be arbitrarily controlled from the outside, and a sample timing control circuit 28 is added. This sample timing control circuit 28 is a RAM
It is composed of a (random access memory) circuit 29 and a timing control circuit 30.

According to this structure, when a control program in which the sample timing is registered is given from the outside, it is stored in the RAM circuit 29, and when the external command is received, the corresponding sample timing is selected, and the timing control circuit. The generation timing of the 28 A / D timing signals is controlled. As a result, the load of circuit operation can be appropriately reduced according to the reception status.

FIG. 9 shows a combination of the function of the sample point selection circuit 24 of FIG. 5 and the function of the sample timing control circuit 28 of FIG. 8 so that they can be selectively used according to the purpose. It is configured by adding 31.

The sample timing control circuit 31 is provided with a PROM circuit 32 in which sample timing is registered in advance and a RAM circuit 33 for storing a sample timing control program given from the outside.
The switch circuit 34 is switch-controlled by the / RAM switch signal, and the timing data of either the PROM circuit 32 or the RAM circuit 33 is given to the timing control circuit 35.

With this configuration, it is possible to receive a sample timing control program indicating information such as the number of sample points and sample intervals transmitted by radio waves from the ground and store it in the RAM circuit 33, PRO
The existing data of the M circuit 32 and the new data of the RAM circuit 33 can be selectively used by an external command to arbitrarily control the sample timing.

It is needless to say that the present invention is not limited to any of the above-mentioned embodiments, and that various modifications can be made without departing from the scope of the present invention.

[0039]

As described above, according to the present invention, the reception level can be appropriately set even when the level fluctuation within one pulse of the reception pulse signal is large, and a good image can be obtained. An automatic gain control circuit for a radar receiver can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of an automatic gain control circuit of a radar receiver according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment.

3 is a block diagram showing a configuration in the case where the number of sample points can be externally command-controlled for the A / D conversion circuit of FIG.

FIG. 4 is a timing chart for explaining the operation of the embodiment of FIG.

5 is a block diagram showing a configuration in the case where command control of sample timing can be externally performed on the A / D conversion circuit of FIG. 1;

FIG. 6 is a block diagram showing a configuration in the case where command control of a sample interval can be externally performed on the A / D conversion circuit of FIG. 1;

FIG. 7 is a timing diagram for explaining the operation of the embodiment of FIG.

8 is a block diagram showing a configuration in the case where the A / D conversion circuit shown in FIG. 1 can be arbitrarily controlled with a sample timing from the outside.

9 is a block diagram showing a configuration in the case where the sample point selection circuit of FIG. 5 and the sample timing control circuit of FIG. 8 are combined and can be selectively used according to the purpose.

FIG. 10 is a block diagram showing a configuration of a radar receiver to which the present invention is applied.

FIG. 11 is a block diagram showing a configuration of an automatic gain control circuit of a conventional radar receiver.

FIG. 12 is a timing chart for explaining the circuit operation of FIG. 11.

[Explanation of symbols]

 1 antenna 2 amplifier 3 mixer 4 first variable attenuator 5 second variable attenuator 6 hybrid demultiplexer 7 power monitor circuit 8 AGC circuit 9 output section 10 hybrid demultiplexer 11 mixer 12 amplifier 13 mixer 14 amplifier 15 samples Hold circuit 16 A / D converter circuit 17 PROM circuit 18 A / D converter circuit 19 Integrator circuit 20 Adder circuit 21 Latch circuit 22 PROM circuit 23 Sample number control circuit 24 Sample point selection circuit 25 PROM circuit 26 Timing control circuit 27 Sample interval control Circuit 28 Sample timing control circuit 29 RAM circuit 30 Timing control circuit 31 Timing control circuit 32 PROM circuit 33 RAM circuit 34 Switch circuit 35 Timing control circuit

Claims (6)

[Claims] 1. A power monitor signal detected from a DC component of a received pulse signal output from the variable gain amplifier is input to a variable gain amplifier that increases or decreases the gain of the received pulse signal according to input data and is received. In an automatic gain control circuit of a radar receiver which supplies gain setting data for adjusting a pulse signal to an appropriate level, the power monitor signal is inputted and the level is obtained at a plurality of timings during one pulse period of the received pulse signal. An analog / digital conversion circuit for sampling and converting the data into digital data, an integrating circuit for sequentially adding the digital data obtained during the pulse period, and an average power level of the power monitor signal from the output data of the integrating circuit. And a gain setting data generating means for generating appropriate gain setting data corresponding to this level. An automatic gain control circuit for a radar receiver characterized by: 2. The radar receiver according to claim 1, further comprising a sample number control circuit which is added to the analog / digital conversion circuit and variably controls the number of sample points for analog / digital conversion according to a command set value. Automatic gain control circuit. 3. A sample number selection circuit, which is added to the analog / digital conversion circuit and variably controls the sample timing of the analog / digital conversion from preset timings by command setting values. An automatic gain control circuit for a radar receiver according to claim 1. 4. The radar receiver according to claim 1, further comprising a sample interval control circuit which is added to the analog / digital conversion circuit and variably controls a sample interval for analog / digital conversion according to a command set value. Automatic gain control circuit. 5. A sample timing control circuit, which is added to the analog / digital conversion circuit, stores a sample timing control program given from the outside, and arbitrarily variably controls the sample timing of the analog / digital conversion according to a command set value. An automatic gain control circuit for a radar receiver according to claim 1, wherein: 6. A sample number selection unit, which is added to the analog / digital conversion circuit and variably controls by selecting a sample timing of analog / digital conversion from pre-registered timing according to a command set value, and is externally provided. A sample timing control program that stores a sample timing control program and variably controls the sample timing of analog / digital conversion according to a command setting value, and selects the sample number selection unit and the sample timing control unit according to an external command The automatic gain control circuit for a radar receiver according to claim 1, further comprising: