JPH1188784A - Tdi circuit, image signal reading circuit and image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain high S/N by shielding a pixel signal from a defective pixel in a TDI(time delay and integration) circuit to improve the S/N of a pixel signal obtained from an image pickup sensor. SOLUTION: A TDI function is achieved by supplying the pixel signals G1 to G4 to be outputted from light receiving elements 1-1 to 1-4 formed in a scanning direction of an infrared line sensor to corresponding integration capacity in an integrated circuit with a switching circuit network 5. Also a pixel selection circuit to transmit no pixel signal of the defective pixel to the switching circuit network 5 is provided in an input circuit 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time delay and integration (TDI) circuit for improving the S / N ratio of a pixel signal obtained from an image sensor.
The present invention relates to a circuit, an image signal reading circuit, and an imaging device.

For example, in an image sensor such as an infrared line sensor that performs a mechanical scan relative to a subject, in order to obtain a high S / N ratio, a plurality of pixels are scanned in a direction relative to the subject by the image sensor. And TDI
It is necessary to perform time delay integration of pixel signals at the same imaging point using a circuit.

[0003]

2. Description of the Related Art Conventionally, as a TDI circuit, for example, a signal charge output from an image sensor is converted to a charge coupled device (CCD).
2. Description of the Related Art A TDI circuit that integrates while transferring a charge transfer path composed of an ed device is known.

[0004]

However, in a TDI circuit using a CCD, it is difficult to make defective pixels of an image sensor non-selective, and a high S / N is required in all scanning channels.
There was a problem that it was difficult to achieve the ratio.

In view of the foregoing, the present invention provides a TDI circuit, an image signal readout circuit, and an imaging device capable of cutting off a pixel signal from a defective pixel and obtaining a high S / N ratio. The purpose is to:

[0006]

According to the first aspect of the present invention, there are provided n (n is 2) arranged in the scanning direction of the optical system.
Is an integer greater than or equal to. ) Is a TDI circuit for performing time-delay integration of pixel signals output from the light-receiving elements, and p integration capacitors (where p is an integer satisfying p = kn and k is a positive integer). And a switching network for supplying pixel signals output from the n light receiving elements to the p integration capacitors so that the pixel signals at the same imaging point are supplied to the same integration capacitance. Things.

According to the first aspect of the present invention, the switching circuit is configured to change the pixel signals output from the n light receiving elements so that the pixel signals at the same imaging point are supplied to the same integration capacitor. Since the power is supplied to p integration capacitors, p
The TDI function can be realized by repeating sampling and reset at predetermined timing of the storage voltages of the integral capacitors.

As described above, according to the first aspect of the present invention, the pixel signal output from the n light receiving elements is supplied to the p integration capacitors via the switching network, thereby providing the TDI function. Therefore, a switching element for blocking a pixel signal from a defective pixel is provided between an input terminal for inputting a pixel signal output from n light receiving elements and a switching circuit network. A pixel selection circuit having a simple circuit configuration can be provided.

According to a second aspect of the present invention, in the first aspect, the switching network has p switching unit networks provided corresponding to the p integration capacitors, respectively. The switching unit network is controlled so that one of n pixel signals output simultaneously from the n light receiving elements is selected and supplied to the corresponding integration capacitance.

[0010] In a third aspect of the present invention, in the first aspect, a p is provided corresponding to each of the p integration capacitors, and samples the accumulated voltage of the corresponding integration capacitance.
Sampling circuits, p reset circuits provided corresponding to each of the p integration capacitors, and resetting the accumulated voltage of the corresponding integration capacitors to a fixed voltage value, and p input circuits of the input terminals And an output buffer circuit connected in common to the output terminals of the p. The p number of sampling circuits are controlled so as to sample the accumulated voltage of the corresponding integration capacitance in a predetermined order and periodically, and Is controlled so as to reset the corresponding integrated capacitance sampled from the accumulated voltage to a constant voltage value.

According to a fourth aspect of the present invention, in the first aspect, the input terminal is connected to an electrode to which a pixel signal of the corresponding integration capacitance is applied, the input terminal being provided corresponding to each of the p integration capacitors. P output buffer circuits, and p output samples corresponding to the p output buffer circuits and sampling the output voltage of the corresponding output buffer circuits.
Number of sampling circuits, and p number of reset circuits provided corresponding to each of the p number of integration capacitors and resetting a storage voltage of the corresponding integration capacitance to a constant voltage value. Are controlled so as to sample the output voltage of the corresponding output buffer circuit in a predetermined order and periodically, and the p number of reset circuits set the corresponding integration capacitors sampled from the accumulated voltage to a constant voltage value. It is controlled to reset to.

According to the fourth aspect of the present invention, since the output buffer circuits are provided corresponding to each of the p integration capacitors, the crosstalk between pixel signals output from the p integration capacitors is provided. Can be reduced.

According to a fifth aspect of the present invention, in the first aspect, the n number of light receiving elements provided for each of the n number of light receiving elements for inputting a pixel signal output from the corresponding light receiving element are provided. And n input transistors provided corresponding to each of the n input terminals, a first current input / output electrode is connected to the corresponding input terminal, and a constant voltage is applied to the control electrode. , A first current input / output electrode is connected to a second current input / output electrode of the corresponding input transistor, and the second current input / output electrode is connected to a switching network. And a pixel selection control circuit that controls on / off of each of the n pixel selection transistors based on defective pixel information. That.

According to a fifth aspect of the present invention, a pixel selection circuit for cutting off a pixel signal from a defective pixel is composed of n pixel selection transistors and a pixel selection control circuit.

In a sixth aspect of the present invention based on the fifth aspect, the first current input / output electrode is connected to the second current input / output electrode of the corresponding input transistor, and the second current input / output electrode is connected to the second input / output electrode. And a first electrode connected to a control electrode of the offset current supply transistor, and a second electrode connected to a second current input / output electrode of the offset current supply transistor. A control voltage application capacitor for applying a control voltage to the control electrode of the offset current supply transistor,
A first current input / output electrode is connected to a second current input / output electrode of a corresponding input transistor, and a second current input / output electrode is connected to a second electrode of a control voltage application capacitor. A current mirror circuit comprising a hold signal is applied and a sample and hold transistor for holding the control voltage to be applied to the control electrode of the offset current supply transistor to the control voltage application capacitor corresponding to each of the n input transistors It is to be prepared.

According to the sixth aspect of the present invention, when a dark object is imaged with the sample-and-hold transistor turned on, an offset current flows to the light receiving element via the offset current supply transistor. Since the control voltage of the control transistor can be stored in the control voltage supply capacitor, the offset current can be supplied to the light receiving element even after the sample hold transistor is turned off.

According to a seventh aspect of the present invention, in the second aspect, the n number of light receiving elements provided for each of the n number of light receiving elements for inputting a pixel signal output from the corresponding light receiving element. An input terminal and n input terminals are provided corresponding to each of the n input terminals, a first current input / output electrode is connected to the corresponding input terminal, and a second current input / output electrode is connected to the switching network. Pixel selection transistors,
A pixel selection control circuit that controls on / off of each of the n pixel selection transistors based on the defective pixel information, and a first current input / output that is provided corresponding to each of the p switching unit networks. Electrodes connected to the output end of the corresponding switching unit network, the second current input / output electrode connected to the corresponding integration circuit, and p transistors having a constant voltage applied to the control electrode. Things.

According to a seventh aspect of the present invention, a pixel selection circuit for cutting off a pixel signal from a defective pixel is composed of n pixel selection transistors and a pixel selection control circuit.

According to an eighth aspect of the present invention, in the fifth, sixth or seventh aspect, the pixel selection control circuit comprises n pixel selection transistors provided corresponding to each of the n pixel selection transistors.
Registers provided for each of the RS flip-flop circuits and the n RS flip-flop circuits, for storing defective pixel information, and provided for each of the n RS flip-flop circuits. Is connected to the output terminal of the corresponding register, and the other end is connected to the corresponding R
One end is provided corresponding to each of the n first switch elements connected to the reset signal input terminal of the S flip-flop circuit, the on / off of which is controlled by a write signal, and the n RS flip-flop circuits. Are connected to a high-potential-side power supply line, the other end is connected to a reset signal input terminal of a corresponding RS flip-flop circuit, and n second switch elements whose on / off are controlled by the reset signal are provided. It is that.

In a ninth aspect of the present invention, there is provided an image signal readout circuit. The image signal readout circuit comprises an m-th image sensor having n light receiving elements arranged in a matrix in a scanning direction and m light receiving elements in a direction orthogonal to the scanning direction. M TDI circuits of the first, second, third, fourth, fifth, sixth, seventh, or eighth inventions provided in correspondence with the respective number of scanning channels, and Of the first, second, third, fourth, fifth, sixth, seventh or eighth aspect of the present invention.
The m first, second, third, fourth, fifth, sixth,..., M pixel signals of the scan channels obtained by the DI circuit are converted into one-dimensionally multiplexed image signals. 7th or 8th
And a readout control circuit for controlling reading out of the pixel signal from the TDI circuit of the invention.

According to a tenth aspect of the present invention, there is provided an imaging device, wherein an imaging sensor in which n light receiving elements are arranged in a scanning direction and m light receiving elements are arranged in a matrix in a direction orthogonal to the scanning direction. And an image signal readout circuit according to the ninth aspect.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the first embodiment of the TDI circuit of the present invention will be described.
Embodiments 4 to 4 will be described, including embodiments of the image signal readout circuit and the imaging device of the present invention.

FIG. 1 is a circuit diagram showing a first embodiment of a TDI circuit of the present invention together with a part of a light receiving element formed in an infrared line sensor. Reference numerals 1-1, 1-2, 1-3, and 1-4 denote light receiving elements arranged in a line in the scanning direction of the infrared line sensor, and reference numeral 2 denotes a first embodiment of the TDI circuit of the present invention.

In the first embodiment 2 of the TDI circuit of the present invention, reference numerals 3-1, 3-2, 3-3, and 3-4 denote light receiving elements 1--3.
Pixel signal G output from 1, 1-2, 1-3, 1-4
1, an input terminal for inputting G2, G3, and G4; and 4, an input circuit.

Reference numeral 5 denotes a switching network for supplying pixel signals G1, G2, G3, and G4 output from the input circuit 4 to an integration circuit to be described later; 6-1; 6-2; 6-3;
Reference numeral -4 denotes an integration circuit for integrating the pixel signal supplied from the switching network 5.

Reference numerals 7-1, 7-2, 7-3, and 7-4 denote sampling circuits for sampling the accumulated voltages of the integration circuits 6-1, 6-2, 6-3, and 6-4. , 8-2,
8-3 and 8-4 are integrating circuits 6-1, 6-2, 6-3 and 6
-4 is a reset circuit for resetting.

Reference numeral 9 denotes a sampling circuit 8-1, 8-
An output buffer circuit for outputting the accumulated voltage sampled by 2, 8, 3 and 8-4 as a pixel signal.

Reference numeral 10 denotes a common bus common to other TDI circuits. Reference numeral 11 denotes an nMOS transistor which is turned on and off by an output control signal SR and controls the connection of the output terminal of the output buffer circuit 9 to the common bus 10. It is.

FIG. 2 is a circuit diagram showing the configuration of the input circuit 4. In FIG. 2, reference numerals 13-1, 13-2, 13-3, 13-4
Is an nMOS transistor serving as an input transistor, V _IG
Are nMOS transistors 13-1, 13-2, 13-
3, 13-4 are gate bias voltages applied to the gates.

Further, 14-1, 14-2, 14-3, 1
Reference numeral 4-4 denotes an nMOS transistor serving as a pixel selection transistor for cutting off a pixel signal from a defective pixel. Reference numeral 15 denotes nMOS transistors 14-1, 14-2, and 14-3.
14-4, a pixel selection control circuit for controlling on and off,
S1, DS2, DS3 and DS4 are the pixel selection control circuits 15
Is a pixel selection control signal output from.

FIG. 3 is a circuit diagram showing the configuration of the pixel selection control circuit 15. In FIG. 3, reference numeral 16 denotes a shift register, and 17-
1, 17-2, 17-3 and 17-4 are shift registers 1
6, 1-bit registers, 18-1 and 18-
2, 18-3 and 18-4 are RS flip-flop circuits.

Further, 19-1, 19-2, 19-3, 1
9-4 is p whose on / off is controlled by the write signal W
MOS transistors, 20-1, 20-2, 20-3,
Reference numeral 20-4 denotes a pMOS transistor whose on / off is controlled by the reset signal R, and reference numeral 21 denotes a power supply line for supplying a power supply voltage Vdd.

FIG. 4 shows a switching network 5 and an integrating circuit 6.
FIG. 3 is a circuit diagram illustrating configurations of −1 to 6-4, sampling circuits 7-1 to 7-4, reset circuits 8-1 to 8-4, and an output buffer circuit 9.

In FIG. 4, in the switching network 5,
23-1, 23-2, 23-3, and 23-4 are pixel signals G
1, a switching unit network for selecting G2, G3, and G4.

In the switching unit network 23-1, 24 is controlled to be turned on and off by a switching control signal SW1, and a pixel signal G1 output from the input circuit 4 is output.
Is an nMOS transistor that serves as a switching element for selecting.

Reference numeral 25 denotes a switching control signal SW2.
ON and OFF are controlled by n, and the switching element n selects the pixel signal G2 output from the input circuit 4.
It is a MOS transistor.

Reference numeral 26 denotes a switching control signal SW3.
ON and OFF are controlled by n, and the switching element n selects the pixel signal G3 output from the input circuit 4.
It is a MOS transistor.

Reference numeral 27 denotes a switching control signal SW4.
ON and OFF are controlled by n, and the switching element n selects the pixel signal G4 output from the input circuit 4.
It is a MOS transistor.

In the switching unit circuit network 23-2, reference numeral 28 denotes an nMOS transistor which is turned on and off by a switching control signal SW4 and serves as a switching element for selecting a pixel signal G1 output from the input circuit 4. .

Reference numeral 29 denotes a switching control signal SW1.
ON and OFF are controlled by n, and the switching element n selects the pixel signal G2 output from the input circuit 4.
It is a MOS transistor.

Reference numeral 30 denotes a switching control signal SW2.
ON and OFF are controlled by n, and the switching element n selects the pixel signal G3 output from the input circuit 4.
It is a MOS transistor.

Reference numeral 31 denotes a switching control signal SW3.
ON and OFF are controlled by n, and the switching element n selects the pixel signal G4 output from the input circuit 4.
It is a MOS transistor.

In the switching unit network 23-3, reference numeral 32 denotes an nMOS transistor which is turned on and off by a switching control signal SW3 and serves as a switching element for selecting a pixel signal G1 output from the input circuit 4. .

Reference numeral 33 denotes an nMOS transistor which is turned on and off by a switching SW 4 and serves as a switching element for selecting a pixel signal G 2 output from the input circuit 4.

Reference numeral 34 denotes a switching control signal SW1.
ON and OFF are controlled by n, and the switching element n selects the pixel signal G3 output from the input circuit 4.
It is a MOS transistor.

Reference numeral 35 denotes a switching control signal SW2.
ON and OFF are controlled by n, and the switching element n selects the pixel signal G4 output from the input circuit 4.
It is a MOS transistor.

In the switching unit circuit network 23-4, reference numeral 36 denotes an nMOS transistor which is turned on and off by a switching control signal SW2 and serves as a switching element for selecting a pixel signal G1 output from the input circuit 4. .

Reference numeral 37 denotes a switching control signal SW3.
ON and OFF are controlled by n, and the switching element n selects the pixel signal G2 output from the input circuit 4.
It is a MOS transistor.

Reference numeral 38 denotes a switching control signal SW4
ON and OFF are controlled by n, and the switching element n selects the pixel signal G3 output from the input circuit 4.
It is a MOS transistor.

Reference numeral 39 denotes a switching control signal SW1.
ON and OFF are controlled by n, and the switching element n selects the pixel signal G4 output from the input circuit 4.
It is a MOS transistor.

In the integrating circuit 6-1, 40-1
Is an integration capacitance for integrating a pixel signal output from the switching unit network 23-1, one of the electrodes is connected to a pixel signal output terminal of the switching unit network 23-1,
The other electrode is connected to a ground line 41 that supplies the ground voltage VSS.

In the integrating circuit 6-2, 40-2
Is an integration capacitance for integrating a pixel signal output from the switching unit network 23-2, one of the electrodes is connected to a pixel signal output terminal of the switching unit network 23-2,
The other end is connected to a ground line 41.

Also, in the integrating circuit 6-3, 40-3
Is an integration capacitance for integrating a pixel signal output from the switching unit network 23-3, one of the electrodes is connected to a pixel signal output terminal of the switching unit network 23-3,
The other electrode is connected to a ground line 41.

In addition, in the integrating circuit 6-4, 40-4
Is an integration capacitance for integrating a pixel signal output from the switching unit network 23-4, one electrode of which is connected to a pixel signal output terminal of the switching unit network 23-4,
The other electrode is connected to a ground line 41.

In the sampling circuit 7-1,
Reference numeral 42-1 denotes an nMOS transistor whose on / off is controlled by the sampling signal SP1, whose drain is connected to the electrode of the integration capacitor 40-1 to which the pixel signal is applied, and whose source is the nMOS transistor constituting the output buffer circuit 9. 43 are connected to the gate.

In the sampling circuit 7-2,
Reference numeral 42-2 denotes an nMOS transistor whose on / off is controlled by the sampling signal SP2, the drain of which is connected to the electrode of the integration capacitor 40-2 to which the pixel signal is applied, and the source of which is the nMOS transistor constituting the output buffer circuit 9. 43 are connected to the gate.

In the sampling circuit 7-3,
Reference numeral 42-3 denotes an nMOS transistor whose on / off is controlled by the sampling signal SP3, the drain of which is connected to the electrode of the integration capacitor 40-3 to which the pixel signal is applied, and the source of which is the nMOS transistor constituting the output buffer circuit 9. 43 are connected to the gate.

In the sampling circuit 7-4,
Reference numeral 42-4 denotes an nMOS transistor whose on / off is controlled by the sampling signal SP4, the drain of which is connected to the electrode of the integration capacitor 40-4 to which the pixel signal is applied, and the source of which is the nMOS transistor constituting the output buffer circuit 9. 43 are connected to the gate.

In the reset circuit 8-1, 44
-1 is a pMOS transistor whose on / off is controlled by the reset signal RS1, and has a source connected to the power supply voltage Vdd.
And the drain is connected to the electrode of the integration capacitor 40-1 to which the pixel signal is applied.

In the reset circuit 8-2, 44
Reference numeral -2 denotes a pMOS transistor whose on / off is controlled by the reset signal RS2. The source is connected to the power supply line 45, and the drain is connected to the electrode of the integration capacitor 40-2 to which the pixel signal is applied.

In the reset circuit 8-3, 44
Reference numeral -3 denotes a pMOS transistor whose on / off is controlled by the reset signal RS3. The source is connected to the power supply line 45, and the drain is connected to the electrode of the integration capacitor 40-3 to which the pixel signal is applied.

In the reset circuit 8-4, 44
Reference numeral -4 denotes a pMOS transistor whose on / off is controlled by the reset signal RS4. The source is connected to the power supply line 45, and the drain is connected to the electrode of the integration capacitor 40-4 to which the pixel signal is applied.

The nMOS constituting the output buffer 9
The transistor 43 has a drain connected to the power supply line 45, a source connected to the drain of the nMOS transistor 11, and forms a source follower circuit.

FIG. 5 is a circuit diagram showing the usage of the first embodiment 2 of the TDI circuit of the present invention, and shows one embodiment of the imaging device of the present invention.

In FIG. 5, reference numeral 47 denotes a light-receiving element which is moved 4 times in the scanning direction.
And m infrared ray sensors arranged in a direction orthogonal to the scanning direction, and 48-i1, 48-i2, 48-i.
i3, 48-i4 (where i = 1, 2,..., m) are light receiving elements of the i-th scanning channel.

Reference numeral 49 denotes an embodiment of the image signal reading circuit of the present invention, and reference numeral 50-i denotes light receiving elements 48-i1, 48-i2, 48-i3, 48-i of the i-th scanning channel.
4 of the TDI circuit of the present invention provided corresponding to
This is a TDI circuit having the same configuration as the second embodiment.

Reference numeral 51 denotes TDI circuits 50-1 and 50 having the same configuration as the first embodiment 2 of the TDI circuit of the present invention.
,..., And SRm are output control signals that are sequentially and selectively set to an H level. Is a signal corresponding to the output control signal SR shown in FIG.

FIG. 6 is a timing chart showing the drive timing of the first embodiment 2 of the TDI circuit of the present invention.
In the first embodiment 2 of the TDI circuit of the present invention, the switching control signals SW1 to SW4 and the sampling signal S
P1 to SP4 and reset signals RS1 to RS4 are SW
1 → SP4 → RS4 → SW2 → SP3 → RS3 → SW3
The active level is selectively set in the order of → SP2 → RS2 → SW4 → SP1 → RS1, and this is repeated.

Here, at time T1, the switching control signal SW1 is set to the H level, and in the switching network 5, the nMOS transistors 24, 29, 3
4, 39 = ON, and the integral capacities 40-1, 40-2,
As shown in FIG. 7, pixel signals G1, G2, G3, and G4 are supplied to 40-3 and 40-4, respectively.

When the pixel signal supply period ΔT1 ends, the switching control signal SW1 is set to L level,
nMOS transistors 24, 29, 34, 39 = OFF
And the sampling signal SP4 = H level,
The nMOS transistor 42-4 is turned ON, and the accumulated voltage of the integration capacitor 40-4 is applied to the gate of the nMOS transistor 43.

Subsequently, the sampling signal SP4 = L level, the nMOS transistor 42-4 = OFF, the reset signal RS4 = L level, the pMOS transistor 44-4 = ON, and the accumulation voltage of the integration capacitor 40-4. Is reset to the power supply voltage Vdd.

At time T2, the reset signal RS4 = H level and the pMOS transistor 44-4 = O
FF and the switching control signal SW2 = H
Level, and the nMOS transistors 25, 30, 3
5, 36 = ON, the integration capacitances 40-1, 40-2,
As shown in FIG. 7, pixel signals G2, G3, G4, and G1 are supplied to 40-3 and 40-4, respectively.

When the pixel signal supply period ΔT2 ends, the switching control signal SW2 is set to L level,
nMOS transistors 25, 30, 35, 36 = OFF
And the sampling signal SP3 = H level,
The nMOS transistor 42-3 is turned ON, and the accumulated voltage of the integration capacitor 40-3 is applied to the gate of the nMOS transistor 43.

Subsequently, the sampling signal SP3 = L level, the nMOS transistor 42-3 = OFF, the reset signal RS3 = L level, the pMOS transistor 44-3 = ON, and the accumulated voltage of the integration capacitor 40-3. Is reset to the power supply voltage Vdd.

At time T3, the reset signal RS3 = H level and the pMOS transistor 44-3 = O
FF and the switching control signal SW3 = H
Level, and the nMOS transistors 26, 31, 3
2, 37 = ON, and the integral capacities 40-1, 40-2,
As shown in FIG. 7, pixel signals G3, G4, G1, and G2 are supplied to 40-3 and 40-4, respectively.

When the pixel signal supply period ΔT3 ends, the switching control signal SW3 is set to L level, and
nMOS transistors 26, 31, 32, 37 = OFF
And the sampling signal SP2 = H level,
The nMOS transistor 42-2 is turned ON, and the accumulated voltage of the integration capacitor 40-2 is applied to the gate of the nMOS transistor 43.

Subsequently, the sampling signal SP2 = L level, the nMOS transistor 42-2 = OFF, the reset signal RS2 = L level, the pMOS transistor 44-2 = ON, and the accumulated voltage of the integration capacitor 40-2. Is reset to the power supply voltage Vdd.

At time T4, the reset signal RS2 = H level and the pMOS transistor 44-2 = O
FF and the switching control signal SW2 = H
Level, and the nMOS transistors 27, 28, 3
3, 38 = ON, the integration capacitances 40-1, 40-2,
Pixel signals G4, G1, G2, and G3 are supplied to 40-3 and 40-4, respectively, as shown in FIG.

When the pixel signal supply period ΔT4 ends, the switching control signal SW4 is set to L level,
nMOS transistors 27, 28, 33, 38 = OFF
And the sampling signal SP1 = H level,
The nMOS transistor 42-1 is turned on, and the storage voltage of the integration capacitor 40-1 is applied to the gate of the nMOS transistor 43.

Subsequently, the sampling signal SP1 is set at L level, the nMOS transistor 42-1 is turned off, the reset signal RS1 is set at L level, the nMOS transistor 44-1 is turned on, and the accumulated voltage of the integration capacitor 40-1 is set. Is reset to the power supply voltage Vdd. Hereinafter, the same operation is repeated.

FIG. 8 is a diagram for explaining the result of the time delay integration obtained by the first embodiment 2 of the TDI circuit of the present invention. In FIG. 8, reference numeral 52 denotes an object to be imaged, and a to j indicate pixel signals. This is the imaging point of the imaging target 52 to be shot.

In this example, the light receiving element 1-1 has image pickup points d to j.
Are sequentially scanned, the light receiving element 1-2 sequentially scans the imaging points c to i, the light receiving element 1-3 sequentially scans the imaging points b to h, and the light receiving element 1-4 sequentially scans the imaging points a to g. The case where the infrared line sensor is moved in the scanning direction so as to perform scanning is shown. In addition, A to J indicate pixel signals obtained when one light receiving element images each of the imaging points a to j.

FIG. 9 shows pixel signal supply periods ΔT1 to ΔT7 when the object 52 is scanned as shown in FIG.
And the pixel signal G output from the light receiving elements 1-1 to 1-4
FIG. 3 is a diagram showing a relationship between contents of 1 to G4, pixel signals distributed to integration capacitors 40-1 to 40-4, and pixel signals forming a storage voltage V0 to be sampled.

As described above, in the first embodiment of the TDI circuit of the present invention, after the start of TDI scanning,
From the imaging point a at the end of the third imaging point d, e, f.
For the pixel signals D, E, F,..., The TDI function can be achieved by performing time delay integration four times.

In the first embodiment 2 of the TDI circuit of the present invention, when the set signal S = H level in the pixel selection control circuit 15 shown in FIG. 3, the pixel selection control signals DS1 to DS4 = H level. , NMOS transistors 14-1 to 14-4 serving as pixel selection transistors =
Becomes ON.

When the switching control signal SW1 is at the H level and the switching control signals SW2 to SW4 are at the L level, the nMOS transistors 24, 29, 34, and 39 as the switching transistors are ON, and the nMOS transistors 25 and 2 as the switching transistors are turned on.
7, 28, 30 to 33, 35 to 38 = OFF.

Thus, the light receiving elements 1-1 to 1-1
4 can individually obtain the pixel signals G1 to G4 output from the defective pixel (defective light receiving element) in this state.
Is obtained, and this defective pixel information is stored in an external memory or the like.

Before starting the TDI scanning, the defective pixel information stored in the external memory or the like is stored in the shift register 1.
6 is stored. In this case, an L level is stored in a register of the shift register 16 corresponding to a non-defective pixel, and an H level is stored in a register of the shift register 16 corresponding to a defective pixel.

Next, after the set signal S is set to the H level and the pixel selection control signals DS1 to DS4 are set to the H level, the write signal W is set to the L level, and the registers 17-1 to 17-4 are set.
Is stored in the RS flip-flop circuits 18-1 to 18-1.
8-4 is applied to the reset signal input terminal.

In this way, among the RS flip-flop circuits 18-1 to 18-4, the pixel selection control signal output from the RS flip-flop circuit whose H level is applied to the reset signal input terminal becomes L level. So n
Of the MOS transistors 14-1 to 14-4, the nMOS transistor provided corresponding to the defective pixel is OMOS.
The FF is set, and the pixel signal from the defective pixel is not supplied to the switching network 5.

As described above, according to the first embodiment of the TDI circuit of the present invention, the pixel signals G1 to G4 output from the light receiving elements 1-1 to 1-4 are integrated by the integration capacitance via the switching network 5. Since the TDI function is achieved by supplying the NMOS transistors 40-1 to 40-4 to the input circuit 4, a simple circuit configuration having nMOS transistors 14-1 to 14-4 serving as pixel selection transistors in the input circuit 4 is provided. Since the pixel signal from the defective pixel can be cut off by providing the pixel selection circuit, the S / N ratio can be improved, and this can be applied to an infrared line sensor having four pixels arranged in the scanning direction. When used, a high S / N ratio can be obtained for all scan channels.

Second Embodiment FIG. 10 to FIG. 12 FIG. 10 is a circuit diagram showing a second embodiment of the TDI circuit of the present invention together with a part of a light receiving element formed in an infrared line sensor. , 54 are the second components of the TDI circuit of the present invention.
It is an embodiment.

Second Embodiment 54 of TDI Circuit of the Present Invention
Is provided with an input circuit 55 having a different circuit configuration from the input circuit 4 included in the first embodiment 2 of the TDI circuit of the present invention, and the other configuration is the same as that of the first embodiment 2 of the TDI circuit of the present invention. It is.

FIG. 11 is a circuit diagram showing a configuration of the input circuit 55. The input circuit 55 includes an input transistor 13-i.
(However, i = 1, 2, 3, 4) and the current mirror circuit 57-i between the pixel selection transistor 14-i.
The other components are the same as those of the input circuit 4 of the first embodiment 2 of the TDI circuit of the present invention.

FIG. 12 is a circuit diagram showing the configuration of the current mirror circuit 57-i. In FIG. 12, reference numeral 59 denotes a power supply voltage Vdd.
A pMOS transistor serving as an offset current supply transistor for supplying an offset current flowing through the light receiving element 1-i to the light receiving element 1-i;
Is a gate voltage application capacitor for applying a gate voltage to the gate of the pMOS transistor 60.

Reference numeral 62 denotes a pMOS transistor 60 necessary for supplying an offset current to the light receiving element 1-i.
Is a pMOS transistor serving as a sampling transistor for holding the gate voltage of the pMOS transistor in the gate voltage application capacitor 61;
This is a sample and hold signal for controlling OFF.

Here, for example, the pixel selection control signal DSi
= L level, nMOS transistor 14-i = OFF, sample hold signal SH = L level, p
When the MOS transistor 62 is turned on and a cold subject is imaged, the pMOS transistor 60
Light receiving element 1-i via nMOS transistor 13-i
The offset current flows through the gate voltage supply capacitor 61, and the gate voltage of the pMOS transistor 60 at this time can be stored in the gate voltage supply capacitor 61.
= L level and the pMOS transistor 62 = OFF, the offset current can be supplied to the light receiving element 1-i.

According to the second embodiment 54 of the TDI circuit of the present invention thus constructed, the integration capacitors 40-1 to 40-40 are used.
Since the offset current of the light receiving element can be removed from the current integrated by -4, when the present invention is used in an infrared line sensor having four pixels arranged in the scanning direction, the present invention is applied to all scanning channels. A higher S / N ratio than that of the first embodiment 2 of the TDI circuit can be obtained.

FIG. 13 and FIG. 14 FIG. 13 is a circuit diagram showing a third embodiment of the TDI circuit of the present invention together with a part of a light receiving element formed in an infrared line sensor. , 64 are the third of the TDI circuit of the present invention.
It is an embodiment.

Third Embodiment of TDI Circuit of the Present Invention 64
The output buffer circuits 65-1 to 65-4 and the sampling circuit 66-1 having different circuit configurations from the output buffer circuit 9 and the sampling circuits 7-1 to 7-4 included in the first embodiment 2 of the TDI times of the present invention. To T.66-4, and the others are configured similarly to the first embodiment 2 of the TDI circuit of the present invention.

FIG. 14 shows output buffer circuits 65-1 to 65-1.
FIG. 4 is a circuit diagram showing a configuration of a sampling circuit 66-1 and sampling circuits 66-1 to 66-4.

In output buffer circuit 65-1, 67
Reference numeral -1 denotes an nMOS transistor. The drain is connected to the power supply line 45, and the gate is connected to the electrode of the integration capacitor 40-1 to which the pixel signal is applied, thereby forming a source follower circuit.

In the output buffer circuit 65-2, reference numeral 67-2 denotes an nMOS transistor, the drain is connected to the power supply line 45, and the gate is connected to the electrode of the integration capacitor 40-2 to which the pixel signal is applied. A source follower circuit is configured.

In the output buffer circuit 65-3, reference numeral 67-3 denotes an nMOS transistor, the drain is connected to the power supply line 45, and the gate is connected to the electrode of the integration capacitor 40-3 to which the pixel signal is applied. A source follower circuit is configured.

In the output buffer circuit 65-4, 67-4 is an nMOS transistor, the drain is connected to the power supply line 45, and the gate is connected to the electrode of the integration capacitor 40-4 to which the pixel signal is applied. A source follower circuit is configured.

In the sampling circuit 66-1, reference numeral 68-1 denotes an nMOS transistor whose on / off is controlled by the sampling signal SP1, whose drain is connected to the source of the nMOS transistor 67-1.
The source is connected to the drain of the nMOS transistor 11.

In the sampling circuit 66-2, reference numeral 68-2 denotes an nMOS transistor whose on / off is controlled by the sampling signal SP2, and whose drain is connected to the source of the nMOS transistor 67-2.
The source is connected to the drain of the nMOS transistor 11.

In the sampling circuit 66-3, reference numeral 68-3 denotes an nMOS transistor whose on / off is controlled by the sampling signal SP3, and whose drain is connected to the source of the nMOS transistor 67-3.
The source is connected to the drain of the nMOS transistor 11.

In the sampling circuit 66-4, reference numeral 68-4 denotes an nMOS transistor whose on / off is controlled by the sampling signal SP4, and whose drain is connected to the source of the nMOS transistor 67-4.
The source is connected to the drain of the nMOS transistor 11.

According to the third embodiment 64 of the TDI circuit of the present invention thus constructed, the integration capacitors 40-1 to 40-40
-4, it is possible to reduce the crosstalk between the pixel signals output from the pixel signals. Therefore, when the present invention is applied to an infrared line sensor having four pixels arranged in the scanning direction, the present invention is applied to all scanning channels. A higher S / N ratio than that of the first embodiment 2 of the TDI circuit can be obtained.

Fourth Embodiment FIGS. 15 to 23 FIG. 15 is a circuit diagram showing a TDI circuit according to a fourth embodiment of the present invention together with a part of a light receiving element formed in an infrared line sensor.

In FIG. 15, 70-1, 70-2, 70-
Numerals 3 and 70-4 denote light receiving elements arranged in the scanning direction of the infrared line sensor, 71-1, 71-2 and 71-3 denote sampling points for one pixel, and 72 denotes a fourth embodiment of the TDI circuit of the present invention. It is a form.

In the fourth embodiment 72 of the TDI circuit of the present invention, 73-1, 73-2, 73-3 and 73-4 are connected to light receiving elements 70-1, 70-2, 70-3 and 70-4. An input terminal 74 for inputting the pixel signals G1, G2, G3, G4 to be output, and an input circuit 74 is configured similarly to the input circuit 4 shown in FIG.

Reference numeral 75 denotes a switching network for supplying pixel signals G1, G2, G3, and G4 output from the input circuit 74 to an integration circuit described later.
6-3, 76-4, 76-5, 76-6, 76-7, 7
Reference numeral 6-8 denotes an integration circuit for integrating the pixel signal supplied from the switching network 75.

Also, 77-1, 77-2, 77-3, 7
7-4, 77-5, 77-6, 77-7, 77-8 are integrating circuits 76-1, 76-2, 76-3, 76-4, 76
This is a sampling circuit for sampling the accumulated voltages of -5, 76-6, 76-7, and 76-8.

Also, 78-1, 78-2, 78-3, 7
8-4, 78-5, 78-6, 78-7, 78-8 are integrating circuits 76-1, 76-2, 76-3, 76-4, 76
-5, 76-6, 76-7, and 76-8 are reset circuits.

Further, 79 is a sampling circuit 78-1,
78-2, 78-3, 78-4, 78-5, 78-6,
This is an output buffer circuit for outputting the accumulated voltage sampled by 78-7 and 78-8 as a pixel signal.

Reference numeral 80 denotes a common bus common to other TDI circuits. Reference numeral 81 denotes an nMOS transistor which is turned on and off by an output control signal SR and controls the connection of the output terminal of the output buffer circuit 79 to the common bus 80. It is.

FIGS. 16 and 17 show the switching network 5.
FIG. 17 is a circuit diagram showing the configuration of FIG.
, 83-1, 83-2, 83-3, 83-4,
83-5, 83-6, 83-7 and 83-8 are pixel signals G
1, a switching unit network for selecting G2, G3, and G4.

In the switching unit circuit 83-1, ON and OFF are controlled by the switching control signal SW2, and the pixel signal G output from the input circuit 74 is output.
1 is an nMOS transistor that serves as a switching element for selecting 1.

Reference numeral 85 denotes a switching control signal SW4
Is an on-off transistor, and is an nMOS transistor serving as a switching element for selecting a pixel signal G2 output from the input circuit 74.

Reference numeral 86 denotes a switching control signal SW6.
Is an on-off transistor, and is an nMOS transistor serving as a switching element for selecting a pixel signal G3 output from the input circuit 74.

Reference numeral 87 denotes a switching control signal SW8.
Is an on-off transistor, and is an nMOS transistor serving as a switching element for selecting a pixel signal G4 output from the input circuit 74.

In the switching unit network 83-2, reference numeral 88 denotes an nMOS which is turned on / off by a switching control signal SW1 and serves as a switching element for selecting a pixel signal G1 output from the input circuit 74.
It is a transistor.

Also, 89 is a switching control signal SW3
Is an on-off transistor, and is an nMOS transistor serving as a switching element for selecting a pixel signal G2 output from the input circuit 74.

90 is a switching control signal SW5.
Is an on-off transistor, and is an nMOS transistor serving as a switching element for selecting a pixel signal G3 output from the input circuit 74.

Reference numeral 91 denotes a switching control signal SW7.
Is an on-off transistor, and is an nMOS transistor serving as a switching element for selecting a pixel signal G4 output from the input circuit 74.

In the switching unit network 83-3, reference numeral 92 denotes an nMOS which is turned on and off by a switching control signal SW4 and serves as a switching element for selecting a pixel signal G1 output from the input circuit 74.
It is a transistor.

Further, 93 is a switching control signal SW6
Is an on-off transistor, and is an nMOS transistor serving as a switching element for selecting a pixel signal G2 output from the input circuit 74.

A switching control signal SW8 94 is provided.
Is an on-off transistor, and is an nMOS transistor serving as a switching element for selecting a pixel signal G3 output from the input circuit 74.

The reference numeral 95 denotes a switching control signal SW2
Is an on-off transistor, and is an nMOS transistor serving as a switching element for selecting a pixel signal G4 output from the input circuit 74.

In the switching unit circuit network 83-4, reference numeral 96 denotes an nMOS which is turned on / off by a switching control signal SW3 and serves as a switching element for selecting a pixel signal G1 output from the input circuit 74.
It is a transistor.

Reference numeral 97 denotes a switching control signal SW5.
Is an on-off transistor, and is an nMOS transistor serving as a switching element for selecting a pixel signal G2 output from the input circuit 74.

Reference numeral 98 denotes a switching control signal SW7.
Is an on-off transistor, and is an nMOS transistor serving as a switching element for selecting a pixel signal G3 output from the input circuit 74.

Further, reference numeral 99 denotes a switching control signal SW1.
Is an on-off transistor, and is an nMOS transistor serving as a switching element for selecting a pixel signal G4 output from the input circuit 74.

In the switching unit network 83-5, reference numeral 100 denotes an nMOS which is turned on / off by a switching control signal SW6 and serves as a switching element for selecting a pixel signal G1 output from the input circuit 74.
It is a transistor.

Reference numeral 101 denotes a switching control signal SW
An nMOS transistor which is turned on and off by 8 and serves as a switching element for selecting a pixel signal G2 output from the input circuit 74.

Reference numeral 102 denotes a switching control signal SW
2 is an nMOS transistor which is turned on / off by 2 and serves as a switching element for selecting a pixel signal G3 output from the input circuit 74.

Reference numeral 103 denotes a switching control signal SW
4 is an nMOS transistor which is turned on and off by an NMOS transistor 4 and serves as a switching element for selecting a pixel signal G4 output from the input circuit 74.

In the switching unit network 83-6, 104 is turned on by the switching control signal SW5,
An nMOS transistor that is turned off and serves as a switching element for selecting the pixel signal G1 output from the input circuit 74.

Reference numeral 105 denotes a switching control signal SW
7 is an nMOS transistor which is turned on and off by 7 and serves as a switching element for selecting a pixel signal G2 output from the input circuit 74.

Reference numeral 106 denotes a switching control signal SW
1 is an nMOS transistor which is turned on and off by 1 and serves as a switching element for selecting a pixel signal G3 output from the input circuit 74.

Reference numeral 107 denotes a switching control signal SW
3 is an nMOS transistor that is turned on and off by 3 and selects the pixel signal G4 output from the input circuit 74.

In the switching unit network 83-7, reference numeral 108 denotes an nMOS which is turned on / off by a switching control signal SW8 and serves as a switching element for selecting a pixel signal G1 output from the input circuit 74.
It is a transistor.

Reference numeral 109 denotes a switching control signal SW
2 is an nMOS transistor that is turned on and off by 2 and serves as a switching element for selecting a pixel signal G2 output from the input circuit 74.

Further, 110 is a switching control signal SW
4 is an nMOS transistor which is turned on and off by 4 and serves as a switching element for selecting a pixel signal G3 output from the input circuit 74.

Further, 111 is a switching control signal SW
6 is an nMOS transistor whose on / off is controlled and selects the pixel signal G4 output from the input circuit 74.

In the switching unit circuit network 83-8, reference numeral 112 denotes an nMOS which is turned on / off by a switching control signal SW7 and serves as a switching element for selecting a pixel signal G1 output from the input circuit 74.
It is a transistor.

Reference numeral 113 denotes a switching control signal SW
1 is an nMOS transistor that is turned on and off by 1 and serves as a switching element for selecting a pixel signal G2 output from the input circuit 74.

Reference numeral 114 denotes a switching control signal SW
3 is an nMOS transistor which is turned on and off by 3 and serves as a switching element for selecting a pixel signal G3 output from the input circuit 74.

The reference numeral 115 denotes a switching control signal SW
5 is an nMOS transistor which is turned on / off by 5 and serves as a switching element for selecting a pixel signal G4 output from the input circuit 74.

FIG. 18 shows the integration circuits 76-1 to 76-4, the sampling circuits 77-1 to 77-4, and the reset circuit 7.
FIG. 19 is a circuit diagram showing a configuration of each of 8-1 to 78-4, FIG. 19 is an integrating circuit 76-5 to 76-8, and a sampling circuit 77-5 to 7-7.
7 is a circuit diagram illustrating a configuration of 7 to 8, reset circuits 78-5 to 78 to 8, and an output buffer circuit 79. FIG.

In the integration circuit 76-1, reference numeral 117-1 denotes an integration capacitance for integrating a pixel signal output from the switching unit network 83-1. One electrode is connected to the output terminal of the switching unit network 83-1. The other electrode is connected to a ground line 118 for supplying the ground voltage Vss.

In the integrating circuit 76-2, 117
Reference numeral -2 denotes an integration capacitor for integrating a pixel signal output from the switching unit network 83-2. One electrode is connected to the output terminal of the switching unit network 83-2, and the other electrode is connected to the ground line 118. It is connected.

In the integrating circuit 76-3, 117
Reference numeral -3 denotes an integration capacitance for integrating a pixel signal output from the switching unit network 83-3. One electrode is connected to the output terminal of the switching unit network 83-3, and the other electrode is connected to the ground line 118. It is connected.

In the integrating circuit 76-4, 117
Reference numeral -4 denotes an integration capacitor for integrating a pixel signal output from the switching unit network 83-4. One electrode is connected to the output terminal of the switching unit network 83-4, and the other electrode is connected to the ground line 118. It is connected.

In the integrating circuit 76-5, 117
Reference numeral -5 denotes an integration capacitance for integrating a pixel signal output from the switching unit network 83-5. One electrode is connected to the output terminal of the switching unit network 83-5, and the other electrode is connected to the ground line 118. It is connected.

In the integrating circuit 76-6, 117
Reference numeral -6 denotes an integration capacitor for integrating a pixel signal output from the switching unit network 83-6. One electrode is connected to the output terminal of the switching unit network 83-6, and the other electrode is connected to the ground line 118. It is connected.

In the integrating circuit 76-7, 117
Reference numeral -7 denotes an integration capacitor for integrating a pixel signal output from the switching unit network 83-7. One electrode is connected to the output terminal of the switching unit network 83-7, and the other electrode is connected to the ground line 118. It is connected.

In the integrating circuit 76-8, 117
Reference numeral -8 denotes an integration capacitance for integrating a pixel signal output from the switching unit network 83-8. One electrode is connected to the output terminal of the switching unit network 83-8, and the other electrode is connected to the ground line 118. It is connected.

In the sampling circuit 77-1, 119-1 is turned on by the sampling signal SP1, and
An nMOS transistor whose OFF is controlled, the drain is connected to the electrode of the integration capacitor 117-1 to which the pixel signal is applied, and the source is an n constituting the output buffer circuit 79.
It is connected to the gate of the MOS transistor 120.

In the sampling circuit 77-2, 119-2 is turned on by the sampling signal SP2,
The nMOS transistor is turned off. The drain is connected to the electrode of the integration capacitor 117-2 to which the pixel signal is applied, and the source is connected to the gate of the nMOS transistor 120.

In the sampling circuit 77-3, 119-3 is turned on by the sampling signal SP3,
The nMOS transistor is turned off. The drain is connected to the electrode of the integration capacitor 117-3 to which the pixel electrode is applied, and the source is connected to the gate of the nMOS transistor 120.

In the sampling circuit 77-4, 119-4 is turned on by the sampling signal SP4.
The nMOS transistor is turned off. The drain is connected to the electrode of the integration capacitor 117-4 to which the pixel signal is applied, and the source is connected to the gate of the nMOS transistor 120.

In the sampling circuit 77-5, 119-5 is turned on by the sampling signal SP5,
The nMOS transistor is turned off. The drain is connected to the electrode of the integration capacitor 117-5 to which the pixel signal is applied, and the source is connected to the gate of the nMOS transistor 120.

In the sampling circuit 77-6, 119-6 is turned on by the sampling signal SP6,
The nMOS transistor is controlled to be off. The drain is connected to the electrode of the integration capacitor 117-6 to which the pixel signal is applied, and the source is connected to the gate of the nMOS transistor 120.

In the sampling circuit 77-7, 119-7 is turned on by the sampling signal SP7,
The nMOS transistor is turned off. The drain is connected to the electrode of the integration capacitor 117-7 to which the pixel signal is applied, and the source is connected to the gate of the nMOS transistor 120.

In the sampling circuit 77-8, 119-8 is turned on by the sampling signal SP8,
The nMOS transistor is turned off. The drain is connected to the electrode of the integration capacitor 117-8 to which the pixel signal is applied, and the source is connected to the gate of the nMOS transistor 120.

In reset circuit 78-1, 121-
Reference numeral 1 denotes a pMOS transistor whose on / off is controlled by the reset signal RS1, whose source is connected to the power supply line 122 supplying the power supply voltage Vdd, and whose drain is connected to the electrode of the integration capacitor 117-1 to which the pixel signal is applied Have been.

In reset circuit 78-2, 1
Reference numeral 21-2 denotes a pMOS transistor which is turned on and off by a reset signal RS2, and has a source connected to the power line 1
The drain is connected to the electrode of the integration capacitor 117-2 to which the pixel signal is applied.

In reset circuit 78-3, 1
Reference numeral 21-3 denotes a pMOS transistor whose on / off is controlled by the reset signal RS3.
The drain is connected to the electrode of the integration capacitor 117-3 to which the pixel signal is applied.

In reset circuit 78-4, 1
Reference numeral 21-4 denotes a pMOS transistor whose on / off is controlled by the reset signal RS4.
The drain is connected to the electrode of the integration capacitor 117-4 to which the pixel signal is applied.

In reset circuit 78-5, 1
Reference numeral 21-5 denotes a pMOS transistor whose on / off is controlled by the reset signal RS5.
The drain is connected to the electrode of the integration capacitor 117-5 to which the pixel signal is applied.

In reset circuit 78-6, 1
Reference numeral 21-6 denotes a pMOS transistor whose on / off is controlled by the reset signal RS6.
The drain is connected to the electrode of the integration capacitor 117-6 to which the pixel signal is applied.

In the reset circuit 78-7, 1
Reference numeral 21-7 denotes a pMOS transistor whose on / off is controlled by the reset signal RS7.
The drain is connected to the electrode of the integration capacitor 117-7 to which the pixel signal is applied.

Also, in the reset circuit 78-8, 1
Reference numeral 21-8 denotes a pMOS transistor whose on / off is controlled by the reset signal RS8.
The drain is connected to an electrode of the integration capacitor 117-8 to which a pixel signal is applied.

Further, nMO constituting output buffer 79 is
The S transistor 120 has a drain connected to the power supply line 122 and a source connected to the drain of the nMOS transistor 81 to form a source follower circuit.

FIG. 20 is a timing chart showing the drive timing of the fourth embodiment 72 of the TDI circuit of the present invention. In the fourth embodiment 72 of the TDI circuit of the present invention, the switching control signals SW1 to SW8, the sampling signal SP1 to SP8 and reset signals RS1 to RS8
Means SW1 → SP8 → RS8 → SW2 → SP7 → RS7
→ SW3 → SP6 → RS6 → SW4 → SP5 → RS5 →
SW5 → SP4 → RS4 → SW6 → SP3 → RS3 → S
The active level is selectively set in the order of W7 → SP2 → RS2 → SW8 → SP1 → RS1, and this is repeated.

Here, at time T1, the switching control signal SW1 is set to the H level, and in the switching network 75, the nMOS transistors 88, 99, 1
06, 113 = ON, and the integral capacitors 117-2, 11
7-4, 117-6 and 117-8 respectively correspond to FIG.
As shown in FIG. 1, pixel signals G1, G4, G3, and G2 are supplied.

When the pixel signal supply period ΔT1 ends, the switching control signal SW1 is set to L level,
nMOS transistors 88, 99, 106, 113 = O
At the same time as the FF, the sampling signal SP8 = H level, the nMOS transistor 119-8 = ON, and the accumulated voltage of the integration capacitor 117-8 is changed to the nMOS transistor 1
20 applied to the gate.

Subsequently, the sampling signal SP8 = L level, the nMOS transistor 119-8 = OFF, the reset signal RS8 = L level, the pMOS transistor 121-8 = ON, and the integration capacitance 117-8.
Is reset to the power supply voltage Vdd.

At time T2, the reset signal RS8 = H level and the pMOS transistor 121-8 =
OFF and the switching control signal SW2 =
H level, and in the switching network 75,
nMOS transistors 84, 95, 102, 109 = O
N, and the integral capacities 117-1, 117-3, 117-
5, 117-7 respectively, as shown in FIG.
Pixel signals G1, G4, G3, G2 are supplied.

When the pixel signal supply period ΔT2 ends, the switching control signal SW2 is set to L level, and
nMOS transistors 84, 95, 102, 109 = O
FF, the sampling signal SP7 = H level, the nMOS transistor 119-7 = ON, and the accumulated voltage of the integration capacitor 117-7 is changed to the nMOS transistor 1
20 applied to the gate.

Subsequently, the sampling signal SP7 = L level, the nMOS transistor 119-7 = OFF, the reset signal RS7 = L level, the pMOS transistor 121-7 = ON, and the integration capacitor 117-7.
Is reset to the power supply voltage Vdd.

At time T3, the reset signal RS7 = H level and the pMOS transistor 121-7 =
OFF and the switching control signal SW3 =
H level, and in the switching network 75,
nMOS transistors 89, 96, 107, 114 = O
N and the integral capacity 117-2, 117-4, 117-
6, 117-8 respectively, as shown in FIG.
The pixel signals G2, G1, G4, G3 are supplied.

When the pixel signal supply period ΔT3 ends, the switching control signal SW3 is set to L level, and
nMOS transistors 89, 96, 107, 114 = O
At the same time as the FF, the sampling signal SP6 = H level, the nMOS transistor 119-6 = ON, and the accumulated voltage of the integration capacitor 117-6 is changed to the nMOS transistor 1
20 applied to the gate.

Subsequently, the sampling signal SP6 = L level, the nMOS transistor 119-6 = OFF, the reset signal RS6 = L level, the pMOS transistor 121-6 = ON, and the integration capacitance 117-6.
Is reset to the power supply voltage Vdd.

Then, at time T4, the reset signal RS6 = H level and the pMOS transistor 121-6 =
OFF and the switching control signal SW4 =
H level, and in the switching network 75,
nMOS transistors 85, 92, 103, 110 = O
N, and the integral capacities 117-1, 117-3, 117-
5, 117-7 respectively, as shown in FIG.
The pixel signals G2, G1, G4, G3 are supplied.

When the pixel signal supply period ΔT4 ends, the switching control signal SW4 is set to L level, and
nMOS transistors 85, 92, 103, 110 = O
At the same time as the FF, the sampling signal SP5 = H level, the nMOS transistor 119-5 = ON, and the accumulated voltage of the integration capacitor 117-5 is changed to the nMOS transistor 1
20 applied to the gate.

Subsequently, the sampling signal SP5 = L level, the nMOS transistor 119-5 = OFF, the reset signal RS5 = L level, the pMOS transistor 121-5 = ON, and the integration capacitance 117-5.
Is reset to the power supply voltage Vdd.

At time T5, the reset signal RS5 = H level and the pMOS transistor 121-5 =
OFF and the switching control signal SW5 =
H level, and in the switching network 75,
nMOS transistors 90, 97, 104, 115 = O
N and the integral capacity 117-2, 117-4, 117-
6, 117-8 respectively, as shown in FIG.
The pixel signals G3, G4, G1, G2 are supplied.

When the pixel signal supply period ΔT5 ends, the switching control signal SW5 is set to L level,
nMOS transistors 90, 97, 104, 115 = O
FF, the sampling signal SP4 = H level, the nMOS transistor 119-4 = ON, and the integration value of the integration capacitor 117-4 is changed to the nMOS transistor 12
0 is applied to the gate.

Subsequently, the sampling signal SP4 = L level, the nMOS transistor 119-4 = OFF, the reset signal RS4 = L level, the pMOS transistor 121-4 = ON, and the integration capacitance 117-4.
Is reset to the power supply voltage Vdd.

Then, at time T6, the reset signal RS4 = H level and the pMOS transistor 121-4 =
OFF and the switching control signal SW6 =
H level, and in the switching network 75,
nMOS transistors 86, 93, 100, 111 = O
N, and the integral capacities 117-1, 117-3, 117-
5, 117-7 respectively, as shown in FIG.
The pixel signals G3, G4, G1, G2 are supplied.

When the pixel signal supply period ΔT6 ends, the switching control signal SW6 is set to L level,
nMOS transistors 86, 93, 100, 111 = O
FF, the sampling signal SP3 = H level, the nMOS transistor 119-3 = ON, and the accumulated voltage of the integration capacitor 117-3 is changed to the nMOS transistor 1
20 applied to the gate.

Subsequently, the sampling signal SP3 = L level, the nMOS transistor 119-3 = OFF, the reset signal RS3 = L level, the pMOS transistor 121-3 = ON, and the integration capacitance 117-3.
Is reset to the power supply voltage Vdd.

Then, at time T7, the reset signal RS3 = H level, the pMOS transistor 121-3 =
OFF and the switching control signal SW7 =
H level, and in the switching network 75,
nMOS transistors 91, 98, 105, 112 = O
N and the integral capacity 117-2, 117-4, 117-
6, 117-8 respectively, as shown in FIG.
Pixel signals G4, G1, G2, G3 are supplied.

When the pixel signal supply period ΔT7 ends, the switching control signal SW7 is set to L level,
nMOS transistors 91, 98, 105, 112 = O
FF, the sampling signal SP2 = H level, the nMOS transistor 119-2 = ON, and the accumulated voltage of the integration capacitor 117-2 is changed to the nMOS transistor 1
20 applied to the gate.

Subsequently, the sampling signal SP2 = L level, the nMOS transistor 119-2 = OFF, the reset signal RS2 = L level, the pMOS transistor 121-2 = ON, and the integration capacitance 117-2.
Is reset to the power supply voltage Vdd.

Thereafter, at time T8, reset signal RS2 = H level, pMOS transistor 121-2 =
OFF and the switching control signal SW8 =
H level, and in the switching network 75,
nMOS transistors 87, 94, 101, 108 = O
N, and the integral capacities 117-1, 117-3, 117-
5, 117-7 respectively, as shown in FIG.
Pixel signals G4, G1, G2, G3 are supplied.

When the pixel signal supply period ΔT8 ends, the switching control signal SW8 is set to L level, and
nMOS transistors 87, 94, 101, 108 = O
At the same time, the sampling signal SP1 is set to the H level, the nMOS transistor 119-1 is set to ON, and the accumulated voltage of the integration capacitor 117-1 is changed to the FF.
20 applied to the gate.

Subsequently, the sampling signal SP1 is set at the L level, the nMOS transistor 119-1 is turned off, the reset signal RS1 is set at the L level, the pMOS transistor 121-1 is turned on, and the integration capacitance 117-1 is set.
Is reset to the power supply voltage Vdd. Hereinafter, the same operation is repeated.

FIG. 22 is a diagram for explaining the time delay integration result obtained by the fourth embodiment 72 of the TDI circuit of the present invention. In FIG. 22, reference numeral 124 denotes an imaging object, and a to p obtain image signals. This is the imaging point of the imaging target 124 to be taken.

In this example, the light receiving element 70-1 has the imaging points g to
p, the light receiving element 70-2 sequentially scans the imaging points e to n, the light receiving element 70-3 sequentially scans the imaging points c to l, and the light receiving element 70-4 scans the imaging points a to j. The case where the infrared line sensor is moved in the scanning direction so as to scan sequentially is shown. A to P indicate pixel signals obtained when one light receiving element captures each of the imaging points a to p.

FIG. 23 is a view showing the state of the imaging object 12 as shown in FIG.
4 when the pixel signal is supplied.
T10, pixel signals G1 to G4 output from the light receiving elements 70-1 to 70-4, and integration capacitors 117-1 to 117-
FIG. 4 is a diagram illustrating a relationship between a pixel signal supplied to a pixel signal No. 4 and a pixel signal forming a sampled accumulated voltage V0.

That is, in the fourth embodiment 72 of the TDI circuit of the present invention, after the start of TDI scanning, the seventh and subsequent imaging points g, h, i,.
The time delay integration can be performed four times for the pixel signals G, H, I,.

As described above, according to the fourth embodiment 72 of the TDI circuit of the present invention, the pixel signals G1 to G4 output from the light receiving elements 70-1 to 70-4 are switched to the switching network 7
The TDI function is achieved by supplying the integration capacitors 117-1 to 117-8 via the input / output circuit 5, thereby providing a simple pixel selection circuit having a circuit configuration including a pixel selection transistor in the input circuit 74. Since the pixel signal from the defective pixel can be cut off, the S / N ratio can be improved, and the infrared signal is formed by arranging four pixels in the scanning direction at intervals of one pixel. When used for a line sensor, a high S / N ratio can be obtained in all scanning channels.

In the input circuit 74 of the fourth embodiment 72 of the TDI circuit of the present invention, the current mirror circuits 57-1 to 57-4 provided in the input circuit 55 of the second embodiment 54 of the TDI circuit of the present invention. However, the current mirror circuits 57-1 to 57-4 may be provided in the input circuit 74.

Also, in the fourth embodiment 72 of the TDI circuit of the present invention, the sampling circuits 77-1 to 77-4
Is provided with a common output buffer circuit 79, but instead of this, an output buffer circuit may be provided for each integration capacitor as in the third embodiment 64 of the TDI circuit of the present invention.

In the first, second, third, and fourth embodiments of the TDI circuit of the present invention, an input transistor is provided between an input terminal and a pixel selection transistor. Although we are trying to provide
A transistor having the same function as these input transistors may be provided between the switching network and the integration capacitor.

[0211]

According to the first, second or third aspect of the present invention (TDI circuit according to claim 1, 2 or 3), n
By supplying pixel signals output from the light receiving elements to p integration capacitors via a switching network, T
Since the DI function is achieved, a switching element for cutting off a pixel signal from a defective pixel is provided between an input terminal for inputting a pixel signal output from the n light receiving elements and the switching network. A pixel selection circuit having a simple circuit configuration can be provided, and a high S / N ratio can be obtained.

[0212] In the present invention, the fourth invention (T described in claim 4)
According to the DI circuit, since the output buffer circuit is provided for each integration capacitor, crosstalk between image signals output from the integration capacitor can be reduced, and the S / N ratio is higher than that of the third invention. Can be obtained.

[0213] In the present invention, the fifth invention (T described in claim 5)
DI circuit), a pixel selection circuit including a pixel selection transistor and a pixel selection control circuit is provided between an input terminal for inputting pixel signals output from n light receiving elements and a switching network. Therefore, a high S / N ratio can be obtained.

In the present invention, the sixth invention (T as described in claim 6)
According to the DI circuit, since the offset current can be supplied to the light receiving element, the offset current of the light receiving element can be removed from the current integrated by the integration capacitor. High S / N ratio can be obtained.

In the present invention, the seventh invention (T described in claim 7)
DI circuit), a pixel selection circuit including a pixel selection transistor and a pixel selection control circuit is provided between an input terminal for inputting pixel signals output from n light receiving elements and a switching network. Therefore, a high S / N ratio can be obtained.

In the present invention, the eighth invention (T described in claim 8)
According to the DI circuit, the same effects as those of the fifth, sixth, and seventh aspects can be obtained, and the pixel selection control circuit can have a simple circuit configuration.

According to the ninth aspect of the present invention, according to the ninth aspect (the image signal reading circuit of the ninth aspect), the first, second, third, fourth,
Since the fifth, sixth, seventh or eighth invention is provided, the present invention is used for an image sensor in which n light receiving elements are arranged in a scanning direction and m light receiving elements are arranged in a matrix in a direction orthogonal to the scanning direction. In such a case, a high S / N ratio can be obtained in all the scanning channels.

According to the tenth aspect of the present invention (the imaging device of the tenth aspect), since the image signal readout circuit of the ninth aspect is provided, a high S / S ratio is obtained in all the scanning channels.
An N ratio can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a TDI circuit of the present invention together with a part of a light receiving element formed in an infrared line sensor.

FIG. 2 is a circuit diagram showing a configuration of an input circuit provided in the first embodiment of the TDI circuit of the present invention.

FIG. 3 is a circuit diagram illustrating a configuration of a pixel selection control circuit included in an input circuit included in the first embodiment of the TDI circuit of the present invention.

FIG. 4 is a circuit diagram showing configurations of a switching network, an integration circuit, a sampling circuit, a reset circuit, and an output buffer circuit provided in the first embodiment of the TDI circuit of the present invention.

FIG. 5 is a circuit diagram showing an embodiment of the imaging device of the present invention.

FIG. 6 is a timing chart showing the drive timing of the first embodiment of the TDI circuit of the present invention.

FIG. 7 is a diagram illustrating a relationship between an integration capacitance and a pixel signal supplied to the integration capacitance in the first embodiment of the TDI circuit of the present invention.

FIG. 8 is a diagram for explaining a time delay integration result obtained by the first embodiment of the TDI circuit of the present invention.

FIG. 9 shows a pixel signal supply period when an imaging target is scanned as shown in FIG. 8, a pixel signal output from a light receiving element, a pixel signal supplied to an integration capacitor, and a sampled voltage V0. FIG. 6 is a diagram showing a relationship with a pixel signal obtained.

FIG. 10 is a circuit diagram showing a second embodiment of the TDI circuit of the present invention together with a part of a light receiving element formed in an infrared line sensor.

FIG. 11 is a circuit diagram showing a configuration of an input circuit provided in a second embodiment of the TDI circuit of the present invention.

FIG. 12 is a circuit diagram illustrating a configuration of a current mirror circuit included in an input circuit included in a second embodiment of the TDI circuit of the present invention.

FIG. 13 is a circuit diagram showing a third embodiment of the TDI circuit of the present invention together with a part of a light receiving element formed in an infrared line sensor.

FIG. 14 is a circuit diagram showing configurations of an output buffer circuit and a sampling circuit provided in a third embodiment of the TDI circuit of the present invention.

FIG. 15 is a circuit diagram showing a fourth embodiment of the TDI circuit of the present invention together with a part of a light receiving element formed in an infrared line sensor.

FIG. 16 is a circuit diagram separately illustrating a configuration of a switching network included in a fourth embodiment of the TDI circuit of the present invention.

FIG. 17 is a circuit diagram separately illustrating a configuration of a switching network included in a fourth embodiment of the TDI circuit of the present invention.

FIG. 18 is a circuit diagram illustrating a configuration of a part of an integration circuit, a part of a sampling circuit, and a part of a reset circuit included in a fourth embodiment of the TDI circuit of the present invention.

FIG. 19 is a circuit diagram showing a configuration of a part of an integration circuit, a part of a sampling circuit, a part of a reset circuit, and an output buffer circuit included in a fourth embodiment of the TDI circuit of the present invention.

FIG. 20 is a timing chart showing the drive timing of a fourth embodiment of the TDI circuit of the present invention.

FIG. 21 is a diagram illustrating a relationship between an integration capacitance and a pixel signal supplied to the integration capacitance in a fourth embodiment of the TDI circuit of the present invention.

FIG. 22 is a diagram for explaining a time delay integration result obtained by a fourth embodiment of the TDI circuit of the present invention.

FIG. 23 is a diagram illustrating a pixel signal supply period when a target to be imaged is scanned as shown in FIG. 22, a pixel signal output from a light receiving element, a pixel signal supplied to an integration capacitor, and a sampled storage voltage; FIG. 6 is a diagram showing a relationship with a pixel signal obtained.

[Explanation of symbols]

 1-1 to 1-4 Light receiving elements G1 to G4 Pixel signal 6-1 to 6-4 Integrating circuit 7-1 to 7-4 Sampling circuit 8-1 to 8-4 Reset circuit

Claims (10)

[Claims] 1. A TDI circuit for time-delay integrating pixel signals output from n light-receiving elements arranged in a scanning direction of an optical system (where n is an integer of 2 or more). (Where p is an integer that satisfies p = kn and k is a positive integer) and the pixel signals at the same imaging point are supplied to the same integration capacitance. a switching network for supplying pixel signals output from the n light receiving elements to the p integration capacitors. 2. The switching network has p switching unit networks provided corresponding to each of the p integration capacitors, and each switching unit network includes the n light receiving elements. Select one of the n pixel signals output simultaneously from
2. The TDI circuit according to claim 1, wherein the TDI circuit is controlled so as to supply a corresponding integral capacitance. 3. A p-number of sampling circuits which are provided corresponding to each of said p-number of integration capacitors and sample the accumulated voltage of the corresponding integration capacitance, and are provided corresponding to each of said p-number of integration capacitors. And
A plurality of p reset circuits for resetting a storage voltage of a corresponding integration capacitor to a constant voltage value; and an output buffer circuit having an input terminal commonly connected to an output terminal of the p sampling circuits. Are controlled so as to sample the accumulated voltage of the corresponding integration capacitance in a predetermined order and periodically, and the p reset circuits keep the corresponding integration capacitance of which the accumulation voltage is sampled constant. 2. The TDI according to claim 1, wherein the TDI is controlled to be reset to a predetermined voltage value.
circuit. 4. An output buffer circuit provided in correspondence with each of the p integration capacitors and having an input terminal connected to an electrode to which a pixel signal of the corresponding integration capacitance is applied, And p sampling circuits for sampling the output voltage of the corresponding output buffer circuit are provided in correspondence with each of the output buffer circuits, and provided in correspondence with each of the p integration capacitors.
And p reset circuits for resetting the accumulation voltage of the corresponding integration capacitance to a constant voltage value, wherein the p sampling circuits output the output of the corresponding output buffer circuit in a predetermined order and periodically. 2. The control circuit according to claim 1, wherein the p reset circuits are controlled to sample a voltage, and the p reset circuits are controlled to reset a corresponding integration capacitance sampled from the accumulated voltage to a constant voltage value. TDI
circuit. 5. An n input terminal provided corresponding to each of said n light receiving elements, for inputting a pixel signal output from the corresponding light receiving element, and each of said n input terminals Is provided corresponding to the
A first current input / output electrode is connected to a corresponding input terminal;
N input transistors to which a constant voltage is applied to the control electrode; and a second current input / output of a corresponding input transistor provided corresponding to each of the n input transistors. A second current input / output electrode connected to the switching circuit network and a second current input / output electrode; and turning on / off each of the n pixel selection transistors based on defective pixel information. 2. The TD according to claim 1, further comprising a pixel selection control circuit for controlling.
I circuit. 6. An offset current supply transistor, wherein a first current input / output electrode is connected to a second current input / output electrode of a corresponding input transistor, and a predetermined voltage is applied to the second current input / output electrode. A first electrode connected to a control electrode of the offset current supply transistor, a second electrode connected to a second current input / output electrode of the offset current supply transistor, and control of the offset current supply transistor A control voltage application capacitor for applying a control voltage to the electrode; a first current input / output electrode connected to a second current input / output electrode of a corresponding input transistor; A sample and hold signal is applied to the control electrode, which is connected to the second electrode of the voltage application capacitor, and should be applied to the control electrode of the offset current supply transistor. TD according to claim 5, characterized in that it comprises in correspondence with each of the n input transistor a current mirror circuit of the control voltage and a sample hold transistor to hold the control voltage applying capacitor
I circuit. 7. An n number of input terminals provided to correspond to each of said n light receiving elements, for inputting a pixel signal output from the corresponding light receiving element; Provided correspondingly,
A first current input / output electrode is connected to a corresponding input terminal;
A pixel selection transistor having a second current input / output electrode connected to the switching network; and a pixel selection control for controlling on / off of each of the n pixel selection transistors based on defective pixel information. A first current input / output electrode is connected to an output end of the corresponding switching unit network, and a second current input / output electrode is connected to the output terminal of the corresponding switching unit network. 3. The TDI circuit according to claim 2, further comprising: p transistors connected to the integrating circuit for applying a constant voltage to the control electrode. 8. A pixel selection control circuit comprising: n RS flip-flop circuits provided corresponding to each of said n pixel selection transistors; and a plurality of RS flip-flop circuits corresponding to each of said n RS flip-flop circuits. A register for storing defective pixel information, and an RS flip-flop circuit provided corresponding to each of the n RS flip-flop circuits, one end of which is connected to the output end of the corresponding register, and the other end of which corresponds to the RS flip-flop circuit. N switch elements, each of which is connected to a reset signal input terminal thereof and whose on / off state is controlled by a write signal, and which is provided in correspondence with each of the n RS flip-flop circuits, and has one end connected to a high potential. Connected to the power line on the
6. The semiconductor device according to claim 5, further comprising: n second switch elements connected to the reset signal input terminal of the corresponding RS flip-flop circuit at the other end, the on / off states of which are controlled by the reset signal. The TDI circuit according to 6 or 7. 9. An image sensor in which n light receiving elements are arranged in a matrix in a scanning direction and m light receiving elements in a direction perpendicular to the scanning direction are provided in correspondence with m scanning channels.
T according to claim 1, 2, 3, 4, 5, 6, 7 or 8
A DI circuit, and pixel signals of the m scanning channels obtained by the m TDI circuits according to claim 1, 2, 3, 4, 5, 6, 7, or 8 are one-dimensionally multiplexed. A read control circuit for controlling reading of pixel signals from the m TDI circuits according to any one of claims 1, 2, 3, 4, 5, 6, 7 and 8 so as to generate an image signal. An image signal reading circuit characterized by the above-mentioned. 10. An image sensor in which n light-receiving elements in a scanning direction and m light-receiving elements in a direction orthogonal to the scanning direction are arranged in a matrix, and the image signal reading circuit according to claim 9 is provided. Characteristic imaging device.