JPH1188724A - Signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal processor where the narrowing of the angle of view is dissolved and an outline can be enhanced by using a frame part colored in regular outline enhancement as a video. SOLUTION: A signal which is image-picked up by CCD is inputted to an outline enhancement circuit 5A in a digital signal processing circuit through a process circuit and an A/D converter in the processor. An outline enhancement component signal by a high pass frequency component is generated in a high pass filter 11 and it is inputted to an adder 13 with an original signal which passes through a delay circuit 12 and whose outline is not houced. A signal HPLUS from a control signal generation circuit is applied to the adder 13 and the addition of the outline enhancement component signal is inhibited in the boundary part of a video area and a non-video area with the signal HPLUS. Thus, the frame part is used as the frame of a video display area without coloring the frame part and the angle of view is not narrowed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device for performing signal processing such as enhancing the outline of a digital image.

[0002]

2. Description of the Related Art The prior art is disclosed in Japanese Patent Application Laid-Open No. 2-24143.
No. 0 publication. In Japanese Patent Application Laid-Open No. 2-241430, a frame portion colored by normal edge enhancement is removed by making it a non-video portion (having a luminance value of 0).

[0003]

However, in this method, several pixels of the frame portion that can be captured by the CCD are invalidated, and the angle of view becomes narrow.

(Object of the Invention) An object of the present invention is to provide a signal processing apparatus capable of enhancing the contour without narrowing the angle of view by utilizing a frame portion which is colored in normal contour enhancement as an image. Is to do.

[0005]

According to the present invention, for an input image signal,
In a signal processing apparatus for obtaining a contour-enhanced image signal by superimposing a contour emphasis component signal of the input image signal, the contour emphasis component signal for a boundary portion between a video signal portion and a non-video signal portion in the input image signal By providing means for restricting the superimposition of the image, the frame portion is also used as an image, and the outline is enhanced so that the angle of view is not narrowed.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIGS. 1 to 4 relate to a first embodiment of the present invention, FIG. 1 shows a configuration of a signal processing device of the first embodiment, and FIG. Shows the configuration of
FIG. 3 shows the configuration of the HPF, and FIG. 4 shows a timing chart for explaining the operation. A detachable imaging device is connected to the signal processing device 1A according to the first embodiment of the present invention shown in FIG. 1, and for example, a charge-coupled device (abbreviated as CCD) 2 as a solid-state imaging device constituting this imaging device. The video signal (or image signal) that has been picked up and photoelectrically converted is input to a pre-processing circuit 3 in the signal processing device 1 and subjected to pre-processing such as gamma correction.

The output signal of the pre-processing circuit 3 is A /
A / D conversion is performed by the D converter 4. The converted digital signal is subjected to signal processing such as enlargement and white balance by the digital signal processing circuit 5, and signal processing for contour enhancement is also performed by the contour enhancement circuit 5A.

The signal processed by the digital signal processing circuit 5 is D / A-converted by a D / A converter 6 and converted into a standard TV signal by a post-processing circuit 7. Also,
A control signal is passed from a control signal generation circuit 8 to the CCD 2, pre-processing circuit 3, digital signal processing circuit 5, and post-processing circuit 7.

Next, the outline emphasis circuit 5A will be described with reference to FIGS. As shown in FIG. 2, the video signal is input to a high-pass filter (abbreviated as HPF) 11 that generates an outline emphasis component signal based on a high frequency component, and a delay circuit 12 that performs timing adjustment by delay. As shown in FIG. 3, the HPF 11 includes two spatial filters 21 and 22, a clip circuit 23, two ROMs 24,
It is composed of five and four two-line memories 26, 27, 28 and 29. The spatial filters 21 and 22 have, for example, a 5 × 5 template and operate on each pixel value of input image data to perform a product-sum operation for edge enhancement.

The two line memories 26 to 29 have a line delay,
The ROMs 24 and 25 store coefficients used for inputting coefficients to the spatial filters 21 and 22. The outline component of the video is extracted by the HPF 11, and the delay circuit 12 adjusts by delay so that the timing of the original image signal matches the timing of the outline component.

These two signals are input to the adder 13. At this time, a signal HPPLUS for permitting addition with the contour component is received from the control signal generating circuit 8, and whether to perform addition is determined based on the value. I do.

The control signal generating circuit 8 stores in advance information of an image pickup area (video signal area) where the CCD 2 actually picks up an image of a subject and a non-image pick-up area (non-image area) where no image is picked up. In these boundary portions, a means for inhibiting (restricting) addition with the contour component by the signal HPLS is formed.

For example, when HPPLUS = 0, the contour component is added to the original video as usual, but when HPPLUS = 1, the original signal is output without superimposing the contour component. The value output from the adder 13 proceeds to the next signal processing circuit.

In this embodiment, an imaging area (video area) in a signal read from the CCD 2 and a non-video area, more specifically, an optical black area (abbreviated as an OB area) used for detecting a black level. ), HPLUS = 0 in the video area. Also, in this case, the original signal is output as it is without superimposing the contour component by setting HPLUS = 1 even in the video area at the level of the contour emphasis width at the boundary (in other words, it is necessary to superimpose the contour component on the original signal). This is characterized in that the frame portion which is usually colored by outline enhancement is not enhanced and the display of the frame is used as it is. In addition, it is possible to display an image whose outline is emphasized without reducing the angle of view (or the image display area).

Next, the operation of the present embodiment will be described. As described above, the signal HPLUS for permitting addition is controlled so that the outline component is not superimposed on several pixels near the boundary between the video portion and the non-video portion. If the HPF 11 has the configuration as shown in FIG. 3, even a contour component at a position at a maximum of 4 pixels away from the boundary may cause a thick frame.
Is to prohibit addition of contour components during a period between four pixels from the boundary between video and non-video.

FIG. 4 illustrates this. The enhancement signal generated near the boundary between the OB area as a non-image area and the image area is a signal that causes the frame to be colored. When added to the original video signal as it is, a thick frame which is colored for edge enhancement at the boundary between the video portion and the non-video portion occurs as represented by the superimposed signal in FIG. 4 (and this thick frame) This requires a masking process that reduces the angle of view for removing the image.)

To prevent this, the HPLUS prohibits the addition of an emphasis signal (emphasis component signal) which causes a thick frame such as coloring (HPLUS = '1'). After that, the addition is permitted (HPLUS = '0') after passing the frame,
Edge enhancement is performed. No addition is performed in the OB region because no enhancement signal is needed.

As a result, the original image which is not emphasized near the video portion and the non-video portion is output,
Since the signal represented by the output signal of FIG. 4 and having a thick frame in the contour emphasis component is not added to the video component, an output signal that does not generate a colored thick frame and does not degrade the image quality. (In the conventional example, if the thick frame is left as it is, the quality is deteriorated and the image is displayed in a narrow image display area, and if the mask processing is further performed to remove the thick frame, the image display area is further narrowed.)

According to the present embodiment, the following effects are obtained. Since the signal portion of the contour emphasis component signal which causes a thick frame is not added to the original video signal (that is, the input image signal) (outline emphasis is not performed), a thick frame such as coloring does not occur, and Video display can be performed without deteriorating quality. Further, since pixels near video and non-video are almost never invalidated, even if a filter having a large template is used, the angle of view is not reduced and pixels can be used effectively.

The superimposition of the contour emphasizing signal may be restricted (prohibited) only for the number of pixels corresponding to the maximum value of the emphasis width by the contour emphasis. Although depending on the processing characteristics of contour emphasis or the contour emphasis level, the present embodiment restricts (prohibits) superimposition of a contour emphasis signal on a boundary portion during a period corresponding to at least one pixel vertically or horizontally. Included in the form.

For example, when the frame is in the horizontal direction, when the superimposition of the period contour enhancement signal corresponding to one pixel is restricted (prohibited) on the image area side of the frame, the outline enhancement signal of one horizontal line period is limited. In some cases, superposition may be restricted (prohibited).

(Second Embodiment) FIG. 5 shows a second embodiment of the present invention.
1 shows a configuration of a signal processing device 1B according to the embodiment. In this embodiment, in FIG. 1, the digital signal processing circuit 5 has a filtering signal processing circuit 5B and a contour emphasizing circuit 5A.

Next, the filtering signal processing circuit 5B will be described with reference to FIG. FIG. 6 shows a configuration example in which two stages of low-pass filters (abbreviated as LPFs) having two kinds of frequency characteristics are arranged in series. This filtering signal processing circuit 5
B is composed of two spatial filter circuits 31, 33 and two bit shift / clip circuits 32, 34.

As shown in FIG. 7, the spatial filter circuit 31
Is a spatial filter 35 for performing a process to act on the pixel value of the input image using a 5 × 5 template, a ROM 36 for writing coefficients into the spatial filter 35, and two two-line memories 37 for line delay, 38.

The result of the product-sum operation performed by the spatial filter circuit 31 has a maximum bit width of 21 bits (the highest bit is a sign bit), and the information is reduced to 8 bits by passing through the bit shift / clip circuit 32. It is input to the spatial filter circuit 33 of the stage.

In the bit shift / clip circuit 32, a signal SHIFT1 indicating how many bits the image data is shifted
Is input from the control signal generation circuit 8. The result of the product-sum operation by the spatial filter circuit 33 also passes through the bit shift / clip circuit 34 as in the first stage, is clipped to 8 bits, and is output to the contour emphasizing circuit 5A serving as the next signal processing circuit.

In the present embodiment, the value of the denominator of the coefficient is changed so that different coefficients can be input in accordance with the mode of the filtering process. Control to adjust by shift is performed.

For example, the bit shift / clip circuit 32 receives the output signal width n bits from the spatial filter circuit 31 as an input, and inputs an arbitrary amount of bits when performing a clip operation for reducing the information amount to m bits (n> m) in the circuit. After shifting, clipping is performed. Other configurations are first
This is the same configuration as that of the embodiment.

Next, the operation of the present embodiment will be described. now,
It is assumed that a template used for processing by the spatial filter circuit 31 in a certain mode is as shown in FIG. In this case, the denominator of the coefficient is 2 7 (that is, 128).
In the spatial filter 35, since the coefficients are integer inputs, when such coefficients are set, the result is calculated by shifting the product-sum operation result by the spatial filter to the right by 7 bits and ignoring the lower bits.

At this time, how many bits are shifted by SH
Obtained from IFT1. In the example of FIG. 8A, SHIFT1 =
It becomes 7. After the bit shift, the remaining 14-bit data is clipped to the bit width of the image data of 8 bits and output.

When the mode is changed and, for example, a template as shown in FIG. 8B is provided, if the denominator of the coefficient is 2 to the fifth power (that is, 32), SHIFT1 = 5, and the right 5 bits Shift and leave the remaining 16 bits to 8
Clip to bits.

As described above, the exponent of the bit of the denominator of the coefficient is changed according to the mode (the exponent is 7 in FIG.
In (B), the exponent is 5), and a different coefficient can be input by performing a bit shift on the processing result of the spatial filter 35 to eliminate the change in the exponent of the denominator bit of the coefficient (conventional example). Has fixed the denominator, and simply ignores the low-order bits of the processing result up to the digit of the denominator value.If clipping is performed with the fixed denominator, the most important bit is invalidated depending on the type of filter template. Such disadvantages can be avoided by not fixing the denominator).

Here, since digital image data is usually always positive, even if smoothing is performed, the result is always positive. Therefore, the clipping range is set to 0 to 255 (unsigned 8 bits). FIG. 9 shows input / output responses before and after clip processing.

The configuration of the second-stage filter is the same, and performs a bit shift based on SHIFT2. The second stage is an LPF as shown in FIG. 10, and if the denominator of the coefficient is 2 to the fifth power (that is, 32), SHIFT2 = 5. The output image data is sent to the edge enhancement circuit 5A. Since the outline emphasizing circuit 5A has been described in the first embodiment, its description is omitted.

According to the present embodiment, the value of the exponent of the denominator of the coefficient in the spatial filter 35 or the like to be filtered is changed according to the mode, and the product-sum operation result in the spatial filter 35 or the like is changed to the value of the denominator. Is adjusted by the bit shift in accordance with the change of, so that the processing can be performed with different coefficients depending on the mode. In addition, it is possible to appropriately perform the required accuracy processing according to the mode. The other effects are the same as those of the first embodiment.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIGS. In the present embodiment, the filtering process is performed for both the case where the image data is in a positive integer format and the case where the image data is in a complement format including a negative value, and the number of bits is determined according to the presence or absence of a sign bit. FIG. 11 shows a filtering processing circuit 5C mounted in the digital signal processing circuit 5 shown in FIG. 5 instead of the filtering processing circuit 5B.

This filtering processing circuit 5C includes two spatial filter circuits 41 and 43 and two bit shift /
A clipping circuit 42, 44, an adder 45 for adding the output signal of the second-stage bit shift / clip circuit 44 and the signal passed through the delay circuit 47, and a clipping circuit 46 for clipping the output of the adder 45; , And a delay circuit 47 for delaying an input signal. The first-stage spatial filter circuit 41 includes the spatial filter circuit 3 shown in FIG.
This is the same configuration as in FIG.

The result of the product-sum operation by the spatial filter circuit 41 has a bit width of 21 bits, and the information is reduced to 8 bits by passing through a bit shift / clip circuit 42. Is input to

In the bit shift / clip circuit 42, a signal SHIFT1 indicating how many bits the image data is shifted
And a signal FLT1 for identifying whether or not the output from the spatial filter is always positive is input from the control signal generation circuit 8.

The FLT 1 is also input to the next spatial filter circuit 43 to recognize whether the data is a positive number or a complement. The result of the product-sum operation by the spatial filter circuit 43 is also the same as that of the first stage.
And is clipped to 8 bits.

After that, the signal is added to the original image signal before the filtering process by the adder 45, and is clipped again by the clipping circuit 46 and output. The delay circuit 47 is a circuit for delaying the original image signal for time alignment with the signal to be filtered.

Next, the operation of the present embodiment will be described. It is assumed that the spatial filter circuit 41 has a template as shown in FIG. 8A and the spatial filter circuit 43 has a template as shown in FIG. 10 in a certain mode. As described in the second embodiment, the signal SH
IFT1 is 7 and SHIFT2 is 5, and the lower bits of the output from each spatial filter are ignored as appropriate and clipped to 8 bits.

Next, the mode changes due to the replacement of the CCD 2, the enlargement of the image, etc., and the filter coefficients of the spatial filter circuits 41 and 43 are changed during the blanking period as shown in FIG.
Suppose that it is rewritten as shown in (A) and (B). SHIFT
1 = 3, SHIFT2 = 0. At this time, the spatial filter circuit 41 becomes a so-called Laplacian filter,
The output is the complement.

The bit shift / clip circuit 42 can handle the image data as a positive number because the spatial filter circuit 41 was the LPF in the previous mode, but the image data output from the spatial filter circuit 41 due to the mode change is lost. Because of the complement, the most significant bit must be treated as a sign.

Therefore, the format of the image data is determined based on the signal FLT1. For example, when the image data is a positive number, F
LT1 = '0', and the data is treated as positive. FLT
When 1 = '1', it recognizes that the image data is in the complement format. If the image data is in the complement format, the clip range will be -128 to 127 (signed 8 bits). FIG. 13 shows input / output responses before and after clipping in this case.

The image data input to the spatial filter circuit 43 in the complement format must be transmitted to the spatial filter circuit 43, so that the FLT1 is also input to the spatial filter circuit 43. Spatial filter circuit 43
Since the template (1) outputs the input image data as it is, the data format of the image is a complement.

The signal that has passed through the bit shift / clip circuit 44 is added to the original image signal whose timing has been adjusted by the delay circuit 47, output again after clipping.

This embodiment has the following effects. According to the above configuration, it is possible to easily create a filter having a template that operates with very different characteristics, and to perform optimal bit allocation with the same circuit. In addition, the calculation accuracy due to the serial connection can be improved, and the bit allocation based on the mode change can be optimally performed.

With such a configuration, SHIFT
By simply reducing the numerical value of by one, a filter having twice the strength of the current emphasis level can be easily obtained, so that it can be effectively used even when the emphasis level is changed.

[Supplementary Notes] In a signal processing apparatus for obtaining an outline-enhanced image signal by superimposing an outline enhancement component signal of the input image signal on an input image signal, a boundary between a video signal portion and a non-video signal portion in the input image signal is provided. A signal processing device comprising means for restricting superimposition of the contour emphasis component signal on a portion. 2. A signal processing apparatus for obtaining a contour-enhanced digital image signal by superimposing a contour enhancement component signal of the input image signal on a digital input image signal, wherein a video signal portion and a non-video signal portion in the input image signal are provided. A signal processor comprising means for prohibiting superimposition of the contour emphasis component signal corresponding to the boundary portion with at least one pixel period.

3. In a signal processing device for obtaining a contour-enhanced digital image signal by superimposing a contour enhancement component signal of the input image signal on a digital input image signal, a video signal component and a non-video signal component in the input image signal A signal processor comprising means for prohibiting at least one horizontal line period from superimposing the contour emphasis component signal corresponding to a boundary portion with the boundary. 4. In a signal processing device for obtaining a contour-enhanced digital image signal by superimposing a contour emphasis component of the input image signal on a digital input image signal in accordance with the contour emphasis control signal, A signal processing apparatus comprising: means for generating the contour emphasis control signal for inhibiting superimposition of the contour emphasis component signal corresponding to a boundary portion between a video signal component and a non-video signal component for at least one pixel period.

5. In a signal processing device for obtaining a contour-enhanced digital image signal by superimposing a contour emphasis component of the input image signal on a digital input image signal in accordance with the contour emphasis control signal, A signal processing device for generating the contour emphasis control signal for inhibiting superimposition of the contour emphasis component signal corresponding to a boundary portion between a video signal component and a non-video signal component for at least one horizontal line period. . 6. In a signal processing device for obtaining a contour-enhanced digital image signal by superimposing a contour enhancement component signal of the input image signal on a digital input image signal, a video signal component and a non-video signal component in the input image signal A signal processing device having means for prohibiting superimposition at a boundary between the pixel and the pixel for a period corresponding to the number of pixels corresponding to the maximum value of the emphasis width of the contour emphasis component signal.

7. An image processing apparatus for performing a filtering process on a digital image signal by using a plurality of serially connected spatial filters, wherein a digital image signal input to the spatial filter has an unsigned first mode and a signed second mode. A signal processing device that performs a filtering process corresponding to any of the modes. 8. In the supplementary note 7, in the signed second mode, filtering is performed with a predetermined number of bits including a sign bit, and in the first mode without a sign, filtering is performed with a predetermined number of bits without including a sign bit. A signal processing device characterized by the above-mentioned.

9. Appendix 7 or 8, wherein in a circuit having an input of an output signal width of n bits from the spatial filter, m
At the time of a clip operation that reduces the amount of information to bits (n> m),
A signal processing apparatus characterized in that an input is bit-shifted by an arbitrary amount before clipping is performed. 10. 7. The signal processing device according to claim 7, wherein the selection is performed by an external signal input when selecting a mode or performing a clip operation.

(Background of Supplementary Notes 7 to 10) (Prior Art) As a prior art relating to a signal processing apparatus for performing a filtering process on a digital image signal, Japanese Patent Application Laid-Open No.
There is 168326 publication.

In JP-A-6-168326, a large template is formed by connecting a plurality of 3 × 3 templates in series because the processing time when a 5 × 5 template is used is too slow.

(Problem to be solved)
Currently, there are devices that have a 5 × 5 template and are capable of high-speed pipeline processing.

Japanese Patent Application Laid-Open No. 6-168326 describes
It is stated that a large template with a complicated frequency characteristic such as 9 × 9 or 11 × 11 can be created by stacking a number of × 3 templates in series, but when connecting in series, The output needs to be clipped before entering the next filter.

Since the bit width is limited by the operation of the clip, if this operation is performed many times, the calculation accuracy will be reduced even if a filter having complicated frequency characteristics is created.

When a mode change function for rewriting a filter coefficient of a template by enlarging an image or replacing an image pickup device is provided, clipping is uniformly performed from the output of each filter to the lower m bits regardless of the mode. In some cases, redundant bit allocation is performed.

(Purpose) The purpose of Supplementary Notes 7 and 8 is to effectively use the most significant bit. The purpose of Supplementary Note 9 is to perform optimal bit allocation to a fixed bit width m in the signal processing device when a filter coefficient is rewritten due to a mode change. The purpose of Supplementary Note 10 is to enable the same circuit to easily cope with a case where there are many types of modes.

[0062]

As described above, according to the present invention, there is provided a signal processing apparatus for obtaining an edge-enhanced image signal by superimposing an edge enhancement component signal of the input image signal on the input image signal. Since the means for limiting the superimposition of the contour emphasis component signal on the boundary between the video signal portion and the non-video signal portion in the input image signal is provided, the frame portion is also used as a video, and the angle of view is reduced. Can be emphasized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a signal processing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an outline emphasis circuit.

FIG. 3 is a block diagram illustrating a configuration of an HPF.

FIG. 4 is a diagram showing a timing chart for explaining the operation of the present embodiment.

FIG. 5 is a block diagram showing a configuration of a signal processing device according to a second embodiment of the present invention.

FIG. 6 is a block diagram illustrating a configuration of a filtering processing circuit.

FIG. 7 is a block diagram illustrating a configuration of a spatial filter circuit.

FIG. 8 is a diagram showing a template by a spatial filter circuit.

FIG. 9 is a characteristic diagram showing input / output characteristics for image data when clipping is performed.

FIG. 10 is a diagram showing a template formed by a spatial filter circuit in a second stage.

FIG. 11 is a block diagram illustrating a configuration of a signal processing device according to a third embodiment of the present invention.

FIG. 12 is a diagram showing a template using two spatial filter circuits.

FIG. 13 is a characteristic diagram showing input / output characteristics for image data when clipping is performed.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Signal processing apparatus 2 ... CCD 3 ... Preprocessing circuit 4 ... A / D converter 5 ... Digital signal processing circuit 5A ... Outline emphasis circuit 5B ... Filtering processing circuit 6 ... D / A converter 7 ... Post processing circuit 8 ... Control signal Generating circuit 11 ... HPF 12 ... Delay circuit 13 ... Adder 21, 22 ... Spatial filter 23 ... Clip circuit 24, 25 ... ROM 26-29 ... 2-line memory

Claims (1)

[Claims] 1. A signal processing apparatus for obtaining an edge-enhanced image signal by superimposing an edge enhancement component signal of the input image signal on an input image signal, comprising: A signal processing device comprising means for restricting superimposition of the contour emphasis component signal on a boundary portion with a signal portion.