JPH1187636A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To minimize the occupation area of a memory cell capacitor, by equalizing the thickness of an induced insulating film of the capacitor to thinner one either of a gate insulating film of a MOS transistor or a gate insulating film adjacent to a semiconductor substrate of an EPROM. SOLUTION: A gate oxide film Lox is pattern-formed on a gate electrode forming region of a MOS transistor at a first oxide film 3, and a second oxide film 5 thinner than the film Lox and covering a surface of a silicon substrate 1 or the other region is formed. The film 5 covers a gate oxide film E<2> ox of an E<2> PROM region and an oxide film Cox as a dielectric film of a memory capacitor region of a DRAM. It is divided into the films 3 and 5 to be optimized. And, a thickness of Cox can be matched to smaller thickness of the E<2> ox and Lox . The thickness of the capacitor is reduced to minimize the occupation area of the capacitor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a logic section including a MOS transistor and a memory section are mixedly mounted, and more particularly to a logic section and a memory section including a dynamic random access memory and a rewritable nonvolatile memory. And a semiconductor device in which the same is mixedly mounted on the same chip.

[0002]

2. Description of the Related Art Conventionally, a semiconductor device in which a logic portion including a MOS transistor and a memory portion are mixedly mounted has a nonvolatile memory (hereinafter referred to as E ² PRO) which can be rewritten with the logic portion.
M; Electrically Erasable and Programmable Read On
ly Memory) and a logic part and a dynamic random access memory (hereinafter abbreviated as DRAM). There is no device in which a memory device, a DRAM, and an E ² PROM are mixedly mounted on one chip, and an appropriate method of forming a memory cell capacitor corresponding to this is not known.

[0003]

As described above, a conventional logic / memory mixed type semiconductor device includes a logic section including a MOS transistor, a DRAM and an E ² PROM.
However, there is a problem in that there is no device in which the above three are mixed, and there is no corresponding method of forming a memory cell capacitor.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a memory cell capacitor suitable for a semiconductor device in which the above three components are mixed and a manufacturing method thereof.

[0005]

According to the present invention, there is provided a semiconductor device comprising:
A logic / memory mixed type semiconductor device in which a logic portion including a MOS transistor and a memory portion are mounted on the same chip, wherein the memory portion includes a portion including a DRAM including a memory cell capacitor and an E ² PROM. Wherein the thickness of the dielectric insulating film of the memory cell capacitor is either the thickness of the gate insulating film of the MOS transistor or the thickness of the gate insulating film adjacent to the semiconductor substrate of the E ² PROM. Or thinner.

According to a method of manufacturing a semiconductor device of the present invention, a step of forming a first insulating film on a semiconductor substrate having an element isolation region formed thereon, and a step of forming a gate electrode of a MOS transistor on the first insulating film are performed. Patterning a resist film on the substrate and etching the first insulating film using the resist film as a mask, so that M
Removing the first insulating film other than the gate electrode formation region of the OS transistor; and removing the first insulating film in the region where the first insulating film is removed and exposing the semiconductor substrate. Forming an insulating film.
The same insulating film of DRAM memory cell capacitor of the dielectric insulating film, and a gate insulating film adjacent to the semiconductor substrate of the E ² PROM, a memory unit including a DRAM and E ² PROM, and a logic portion including said MOS transistor It is characterized by being mixedly mounted on a chip.

Further, according to the method of manufacturing a semiconductor device of the present invention, a step of forming a first insulating film on a semiconductor substrate having an element isolation region formed thereon, and a step of forming a gate electrode of an E ² PROM on the first insulating film A step of patterning a resist film in the formation region, and etching of the first insulating film using the resist film as a mask, thereby forming E ² covered with the resist film.
Removing the first insulating film other than the gate electrode forming region of the PROM; and removing the first insulating film and exposing the semiconductor substrate to a second insulating film thinner than the first insulating film in a region where the semiconductor substrate is exposed. Forming the second insulating film with D
Dielectric insulating film of memory cell capacitor of RAM and MO
DRAM and E as the gate insulating film of the S transistor
A memory unit including a ² PROM, characterized in that it mounted on the same chip and a logic portion including the MOS transistor.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention. Hereinafter, the gate oxide film adjacent to the semiconductor substrate of the E ² PROM is referred to as E ² ox, the gate oxide film of the MOS transistor in the logic section is referred to as Lox, and the oxide film used as the dielectric film of the DRAM memory cell capacitor is referred to as Cox. I do.

In the logic / memory hybrid type semiconductor device of the present invention, an E ² PROM region, a logic transistor region including a MOS transistor, and a DRAM memory cell capacitor region are formed on a silicon substrate 1.

FIG. 1 schematically shows a cross-sectional shape of an element constituting each of these regions. M shown here
The OS transistor is not limited to a transistor constituting the logic unit, but may be a switching MOS transistor for charging and discharging a memory cell capacitor of a DRAM.

The logic-memory mixed type semiconductor device of the present invention shown in FIG. 1 is a conventional LOCOS (Local Oxidatio).
n of Silicon), and an element isolation region 2 formed using
In the first oxide film 3 formed on the surface of the silicon substrate 1, that is, in the logic transistor region, the first oxide film 3 is patterned in the gate electrode formation region of the MOS transistor, and is made thinner than this Lox. and silicon second oxide film 5 covering the other regions of the substrate surface, i.e. E ² oxide film 5 of the second, respectively PRO
It has a structure having E ² ox in the M region and Cox in the memory cell capacitor region of the DRAM.

The electrode 6 of the memory cell capacitor of the DRAM
a, the gate electrode 6b of the MOS transistor and E ² PRO
The M gate electrode 6c is made of polycrystalline silicon, and is patterned at predetermined positions. When the gate electrode 6c becomes a floating gate of the E ² PROM,
A control gate electrode is further formed on the gate electrode 6c with a third oxide film interposed therebetween. However, since these are not related to the present invention, the description is omitted.

Reference numerals 10 and 11 denote source / drain diffusion layers of a MOS transistor in which a dopant is ion-implanted through the oxide film 5 from the openings 8 and 9 from which polycrystalline silicon has been removed using the gate electrode 6b and the like as a mask. Source·
A drain electrode (not shown) is opened to the second oxide film 5 and connected to the source / drain diffusion layers 10 and 11.

[0014] In the conventional one in which the logic part and the E ² PROM are mounted together, and in the case in which the logic part and the DRAM are mounted together, as described above, the first oxide film 3 and the second oxide film are formed.
Without distinguishing them from each other, these two films are mounted together as one oxide film.

Therefore, the structure of the conventional semiconductor device in which the two devices are mixed is directly extended and the logic portion and the E ² PROM are
And a DRAM, the first oxide film 3 and the second oxide film 5 become one common oxide film, which simplifies the structure. insulating film thickness of Cox memory cell capacitor, E ² PR
The thickness and MO of the gate insulating film E ² ox adjacent to the OM substrate
Of the thicknesses of the gate insulating film Lox of the S transistor, the required performance, yield and reliability are unified to the thickest worst design value, so that the capacitor insulating film must be thicker than necessary. Become.

As is well known, in order to increase the integration density of a DRAM, it is necessary to minimize the area occupied by a memory cell capacitor while maintaining a constant capacitance value. That is, the thickness of the insulating film Cox of the memory cell capacitor must be as small as possible. Therefore, in the extension of the prior art, what becomes one common oxide film is replaced with the first oxide film 3 and the second oxide film 5 as described above.
By optimizing each of them, the thickness of the oxide film Cox of the memory cell capacitor is adjusted to the thickness E ² ox of the gate oxide film adjacent to the substrate of the E ² PROM and the thickness of the gate oxide film Lox of the MOS transistor. It can be adjusted to the smaller of thickness and thickness.

In the example shown in FIG. 1, the thickness of the oxide film Cox of the memory cell capacitor is made equal to the thickness E ² ox of the gate oxide film adjacent to the substrate of the E ² PROM. E ² PR
The electric field intensity much larger than the oxide film Cox of the memory cell capacitor of the DRAM is applied to the gate oxide film E ² ox adjacent to the OM substrate at the time of writing and reading. It can be used as an oxide film Cox of the capacitor.

As a modification of the first embodiment, in designing a semiconductor device, the thickness Lox of the gate oxide film of the MOSFET is made smaller than the thickness Cox of the gate oxide film adjacent to the substrate of the E ² PROM. In this case, the thickness of the oxide film Cox of the memory cell capacitor of the DRAM is made equal to the thickness Lox of the gate oxide film of the MOSFET.

That is, in FIG. 1, the thickness of the oxide film 5 under the gate electrode 6c of the E ² PROM and the thickness of the oxide film 3 under the gate electrode 6b of the MOS transistor may be interchanged. Oxide film 5 under electrode 6a of the capacitor
Is made equal to the thickness of the oxide film below the gate electrode of the MOS transistor which has been made thinner.

An electric field is concentrated on the drain side of the gate oxide film Lox of the MOS transistor, but only a uniform electric field is applied to the oxide film Cox of the memory cell capacitor of the DRAM. If the thickness is equal to the thickness Lox, sufficient reliability can be obtained.

Next, a method of manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 2 (a), an element isolation region 2 made of thick SiO ₂ thermal oxide film using a conventional LOCOS method on the silicon substrate 1. Next, as shown in FIG. 2B, a uniform first thermal oxide film 3 made of SiO ₂ is formed by thermally oxidizing the surface of the silicon substrate again. Subsequently, a resist film 4 is formed in a pattern in the gate electrode formation region of the MOS transistor by using normal lithography, and is subjected to normal active ion etching (hereinafter referred to as RIE;
The surface of the silicon substrate 1 is exposed by removing the thermal oxide film 3 other than the gate electrode formation region using Reactive Ion Etching).

Next, as shown in FIG.
Is removed, and the exposed surface of the silicon substrate 1 is thermally oxidized again to uniformly form a second thermal oxide film 5 made of SiO ₂ thinner than the gate oxide film 3 previously formed. . At this time, the thickness of the gate oxide film 3 of the MOS transistor patterned earlier also slightly increases, but its influence is small because the thinner second thermal oxide film 5 has a higher growth rate.

Next, as shown in FIG.
Polycrystalline silicon 6 for electrodes and wirings is deposited on the surface of the silicon substrate 1 using a D (Chemical Vapor Deposition) method, and E ² P is formed using a normal lithography method.
The resist film 7 is patterned in regions that become the gate electrode of the ROM, the gate electrode of the MOS transistor, and the electrode of the memory cell capacitor of the DRAM. At this time, the wiring connecting these electrodes is also partially formed of the polycrystalline silicon, and thus the patterning includes a part of these wiring patterns.

Using the resist film patterned as described above as an etching mask, the respective electrode portions and the like made of polycrystal are formed as shown in FIG. Openings 8, 9 for forming source / drain regions of the MOS transistor are also formed at this time. The second oxide film 5 formed earlier remains without being etched if the etching selectivity in the RIE method is made sufficiently large, and serves to protect the silicon substrate surface in the next step.

Next, as shown in FIG.
Is removed, and an n-type dopant such as As is ion-implanted and subjected to active heat treatment, thereby forming the source / drain diffusion layers 10 and 11 of the MOS transistor. At this time, damage to the surface of the silicon substrate during ion implantation is protected by the second oxide film 5. Also, polycrystalline silicon 6a,
The dopants simultaneously implanted into 6b and 6c have the effect of increasing the conductivity of these electrodes and the like. Subsequently, the oxide film 5 in the openings 8 and 9 was removed, and source / drain electrodes were connected to the diffusion layers 10 and 11 to complete a semiconductor device.

In this manner, the semiconductor device according to the first embodiment shown in FIG. 1 can be manufactured. Also, the E ² PR described as a modification of the first embodiment
If it is desirable to make the thickness of the gate oxide film Lox of the MOS transistor smaller than the thickness of the gate oxide film E ² ox adjacent to the OM substrate, the thickness of the oxide film Cox of the memory cell capacitor of the DRAM is reduced. The thickness is set equal to the thickness of the gate oxide film Lox of the MOSFET.

In this case, in the method of manufacturing a semiconductor device according to the second embodiment, the E ² PROM
The oxide film 5 below the gate electrode 6c is deposited thicker as a first insulating film, and the gate oxide film of the MOS transistor and the oxide film of the memory cell capacitor are later deposited thinly as a common second oxide film. Good.

The present invention is not limited to the above embodiment. For example, in the first and second embodiments, the first, although the second oxide film has been described for the case of a thermally oxidized film of silicon made of SiO _2, not necessarily limited to SiO ₂ . For example, Si
Other insulating films such as N, SiON, and ONO can be used for the same purpose. Further, as the polycrystalline silicon film, conductive polycrystalline silicon into which impurities are introduced by a CVD method may be used. Others without departing from the gist of the present invention,
Various modifications can be made.

[0029]

As described above, according to the semiconductor device of the present invention, for example, the gate length of the MOS transistor is 0.6 μm.
Logic using microfabrication technology of about m, E ² PRO
In a semiconductor device composed of an LSI incorporating both M and DRAM, the occupied area of the memory cell capacitor of the DRAM is made sufficiently small, so that a 1 gigabit DRAM which has been impossible in the past can be integrated on one chip. became.

[Brief description of the drawings]

FIG. 1 shows an E ² -PROM, a logic transistor, and a DR.
FIG. 2 is a cross-sectional view of a semiconductor device of the present invention in which an AM capacitor is mounted on one chip.

FIG. 2 shows an E ² -PROM, a logic transistor, and a DR.
Sectional drawing which shows the manufacturing method of the semiconductor device of this invention which mounted the capacitor | condenser of AM on 1 chip.

FIG. 3 shows an E ² -PROM, a logic transistor, and a DR.
Sectional drawing which shows the continuation of the manufacturing method of the semiconductor device of this invention which mounted the capacitor | condenser of AM on one chip.

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Thick thermal oxide film for element isolation using LOCOS method 3 ... First oxide film 4 ... Resist film 5 ... Second oxide film 6 ... Polycrystalline silicon film 6a ... DRAM 6b: Gate electrode of MOS transistor 6c: Gate electrode of E ² PROM 7: Resist film 8: Source region of MOS transistor 9: Drain region of MOS transistor 10: Source diffusion layer 11: Drain diffusion layer

Claims (3)

[Claims] 1. A semiconductor device in which a logic unit including a MOS transistor and a memory unit are mounted on the same chip, wherein the memory unit is a rewritable part including a dynamic random access memory including a memory cell capacitor. A portion comprising a non-volatile memory, wherein the thickness of the dielectric insulating film of the memory cell capacitor is equal to the thickness of the gate insulating film of the MOS transistor and the thickness of the gate insulating film adjacent to the semiconductor substrate of the non-volatile memory A semiconductor device, which is equal to the smaller of the thicknesses. 2. A step of forming a first insulating film on a semiconductor substrate on which an element isolation region is formed, and a step of patterning a resist film in a gate electrode forming region of a MOS transistor on the first insulating film. Removing the first insulating film other than the gate electrode forming region of the MOS transistor covered with the resist film by etching the first insulating film using the resist film as a mask; Forming a second insulating film thinner than the first insulating film in a region where the first insulating film is removed and the semiconductor substrate is exposed; As a dielectric film of a memory cell capacitor of a random access memory and a gate insulating film adjacent to a semiconductor substrate of a rewritable nonvolatile memory, a dynamic random A memory unit including access memory and rewritable nonvolatile memory,
A method of manufacturing a semiconductor device, wherein a logic part including the MOS transistor is mixedly mounted on the same chip. 3. A step of forming a first insulating film on a semiconductor substrate on which an element isolation region is formed, and a resist film on a gate electrode forming region of the rewritable nonvolatile memory on the first insulating film. Patterning the resist film, and etching the first insulating film using the resist film as a mask, thereby forming the second region other than the gate electrode forming region of the rewritable nonvolatile memory covered with the resist film. Removing the first insulating film; and forming a second insulating film thinner than the first insulating film in a region where the first insulating film is removed and the semiconductor substrate is exposed. The second insulating film is formed of a dielectric insulating film of a memory cell capacitor of a dynamic random access memory, and a MOS.
A method of manufacturing a semiconductor device, wherein a memory unit including a dynamic random access memory and a rewritable nonvolatile memory as a gate insulating film of a transistor, and a logic unit including the MOS transistor are mounted on the same chip. .