JPH1187618A - Inductor for semiconductor device and method of manufacturing the same - Google Patents

Inductor for semiconductor device and method of manufacturing the same

Info

Publication number
JPH1187618A
JPH1187618A JP9267823A JP26782397A JPH1187618A JP H1187618 A JPH1187618 A JP H1187618A JP 9267823 A JP9267823 A JP 9267823A JP 26782397 A JP26782397 A JP 26782397A JP H1187618 A JPH1187618 A JP H1187618A
Authority
JP
Japan
Prior art keywords
insulating film
wiring
inductor
coil
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9267823A
Other languages
Japanese (ja)
Other versions
JP3733219B2 (en
Inventor
Kenichi Ishimaru
賢一 石丸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New Japan Radio Co Ltd
Original Assignee
New Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New Japan Radio Co Ltd filed Critical New Japan Radio Co Ltd
Priority to JP26782397A priority Critical patent/JP3733219B2/en
Publication of JPH1187618A publication Critical patent/JPH1187618A/en
Application granted granted Critical
Publication of JP3733219B2 publication Critical patent/JP3733219B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide an inductor having advantage of meander type, without particularly having lowered Q for the large number of turns in a coil, while having a high integration efficiency. SOLUTION: An inductor for semiconductor device comprising a thin film wiring formed on insulation films 4 and 5 on the semiconductor substrate is formed, so that the insulation films 4 and 5 are correspondingly formed by plural projecting sections 8 and recess sections 9 alternately parallel to each other as in the teeth of a comb, the difference in height between the sections 8 and the sections 9 is made thicker than at least the thickness of the wiring, and a bevel step 7 is constituted forwardly tapered. A meander coil is formed by the wiring along the section 8 and the section 9 with the wiring being folded back at the bevel step 7.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、高周波用ICの内
部に、受動素子の一つとして設けられるはインダクタに
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inductor provided as one of passive elements inside a high frequency IC.

【0002】[0002]

【従来の技術】従来、高周波用IC内部に作り込まれる
インダクタとして、スパイラル型のものとメアンダ型の
ものが広く用いられている。
2. Description of the Related Art Conventionally, spiral type inductors and meander type inductors have been widely used as inductors built in high frequency ICs.

【0003】図2(a)は、スパイラル型インダクタの
平面図、同(b)はその断面図、図3(a)は、メアン
ダ型インダクタの平面図、同(b)はその断面図を示
す。
FIG. 2A is a plan view of a spiral inductor, FIG. 2B is a sectional view thereof, FIG. 3A is a plan view of a meander inductor, and FIG. 2B is a sectional view thereof. .

【0004】スパイラル型インダクタは、通常図2に示
すように、2層構造で形成されている。半導体基板6上
に設けられた絶縁膜5上に引出し配線2が形成され、こ
れらを被って第2層の絶縁膜4が設けられ、その上に金
属薄膜配線よりなる渦巻き状のコイルが形成され、同コ
イルの中心端は絶縁膜4に開けられたビアホール(vi
ahole)3を介して引出し配線2に接続されてい
る。
A spiral type inductor is usually formed in a two-layer structure as shown in FIG. A lead wiring 2 is formed on an insulating film 5 provided on a semiconductor substrate 6, and a second-layer insulating film 4 is provided over the lead wiring 2, and a spiral coil made of a metal thin-film wiring is formed thereon. The center end of the coil is a via hole (vi) formed in the insulating film 4.
(ahole) 3 and connected to the extraction wiring 2.

【0005】一方、メアンダ型インダクタは、図3に示
すように単層構造で、絶縁膜5上にに形成されたつづら
折れ状の配線1でコイル部を構成している。
On the other hand, the meander-type inductor has a single-layer structure, as shown in FIG. 3, and has a coiled portion formed by winding wires 1 formed on an insulating film 5.

【0006】[0006]

【発明が解決しようとする課題】図2及び図3に示した
ような従来のインダクタでは、巻数を多くしようとする
と、占有面積と共に、配線の長さ(従って抵抗の大き
さ)が大きく増大し、面積効率がよく、またQ特性のよ
いインダクタを作ることが困難となるという問題があっ
た。
In the conventional inductors as shown in FIGS. 2 and 3, when the number of turns is increased, the occupied area and the length of the wiring (therefore, the resistance) are greatly increased. In addition, there is a problem that it is difficult to produce an inductor having good area efficiency and good Q characteristics.

【0007】 因みに、図2に示したスパイラル型イン
ダクタについては、コイルのピッチをs、最小のコイル
の辺の長さをL1 、巻数をnとすれば、コイル部の配線
長さA1 及び占有面積S1 は、それぞれ以下のようとな
る。 A1 =4n・L1 +2(2n−1)n・s S1 ={L1 +2(n−1)s}2
In the spiral inductor shown in FIG. 2, if the pitch of the coil is s, the length of the minimum coil side is L 1, and the number of turns is n, the wiring length A 1 and the occupied area of the coil portion S1 is as follows. A1 = 4nL1 + 2 (2n-1) ns S1 = {L1 + 2 (n-1) s} 2

【0008】上式が示すように巻数が多くなると、配線
長さ及び占有面積は共に巻数nの2乗に比例して増加す
ることとなるので、上述の問題が顕著となる。
As shown in the above equation, when the number of turns increases, both the wiring length and the occupied area increase in proportion to the square of the number of turns n, so that the above-mentioned problem becomes significant.

【0009】一方、図3に示したメアンダ型インダクタ
については、素辺の長さをL2 、ピッチをs、巻数をn
とすると、配線長さA2 及び占有面積S2 は、以下のよ
うになり、 A2 =2n・L2 +2n・s S2 =2n・L2 ・s 配線長さ及び占有面積は共に巻数nに比例して増加する
ので、上述の面積効率やQ特性については、巻数を大き
くすることによる問題はない。
On the other hand, in the meander type inductor shown in FIG. 3, the length of the element side is L2, the pitch is s, and the number of turns is n.
Then, the wiring length A2 and the occupied area S2 are as follows: A2 = 2n · L2 + 2n · s S2 = 2n · L2 · s Both the wiring length and the occupied area increase in proportion to the number of turns n. Therefore, there is no problem in increasing the number of turns in the area efficiency and the Q characteristic described above.

【0010】しかし、メアンダ型のインダクにおいて
は、隣接導体を流れる電流が互いに逆方向となるため、
隣接導体間の相互インダクタンスが自己インダクタンス
に対して負に働き、導体間の間隔(配線の間隔)を狭く
するほど、インダクタンス値が低減されるという、メア
ンダ型インダクタ固有の特性があり、それが実装密度を
上げる上での制約になっている。
However, in the meander-type inductor, the currents flowing through the adjacent conductors are in opposite directions.
Mutual inductance between adjacent conductors has a negative effect on self-inductance, and as the distance between conductors (interval between wires) is reduced, the inductance value is reduced. This is a constraint on increasing the density.

【0011】本発明は、上記問題点を解消した半導体装
置用インダクタを提供しようとするものである。
An object of the present invention is to provide an inductor for a semiconductor device which has solved the above problems.

【0012】[0012]

【課題を解決するための手段】半導体基板上の絶縁膜上
に設けられ、薄膜状の配線で構成される半導体装置用イ
ンダクタにおいて、前記絶縁膜を櫛歯状に交互に平行す
る複数個の凸状部および凹状部を有するように段差をつ
けた形状に形成し、前記凸状部及び凹状部に沿って形成
した配線部分及び前記段差部分に形成した折り返し配線
部分によりメアンダ型のコイルを構成した。
According to the present invention, there is provided an inductor for a semiconductor device provided on an insulating film on a semiconductor substrate and formed of thin-film wiring. A meandering coil formed by forming a stepped shape having a convex portion and a concave portion, and a wiring portion formed along the convex portion and the concave portion and a folded wiring portion formed at the step portion. .

【0013】上記のように絶縁膜を段差を有するように
形成し、その凸状部及び凹状部に沿った配線を主要部分
としてメアンダ型のコイルを構成することにより、隣接
導体間の間隔を実質的に大きくすることができ、上述の
導体間隔の狭小によるインダクタンス値の低減の問題が
緩和されるので、メアンダ型のコイルでありながら実装
密度を上げることが可能となる。
As described above, the insulating film is formed so as to have a step, and the meander-type coil is formed by using the wirings along the convex and concave portions as main parts, thereby substantially reducing the distance between adjacent conductors. Since the problem of reduction in inductance value due to the narrowing of the conductor spacing described above is alleviated, it is possible to increase the mounting density while using a meander type coil.

【0014】上記半導体装置用インダクタは、半導体基
板上の所定範囲一面に第1絶縁膜を堆積する工程、該第
1絶縁膜上に第2絶縁膜を堆積し、該第2絶縁膜を選択
エッチングにより複数個の凸状部を、その段差部分が順
テーパー状になるように形成する工程、及び前記第1絶
縁膜、第2絶縁膜の上面に配線材料を堆積し、エッチン
グにより、又は配線材料の直接描写によりコイル部を形
成する工程を含む一連の工程により製作できる。
In the semiconductor device inductor, a step of depositing a first insulating film over a predetermined area on a semiconductor substrate, depositing a second insulating film on the first insulating film, and selectively etching the second insulating film. Forming a plurality of convex portions such that the step portions thereof have a forward tapered shape, and depositing a wiring material on the upper surfaces of the first insulating film and the second insulating film, and etching or forming the wiring material. Can be manufactured by a series of steps including a step of forming a coil portion by direct depiction of the coil section.

【0015】[0015]

【発明の実施の形態】図1は、本発明の半導体装置用イ
ンダクタの説明図であり、(a)はその平面図、(b)
はその断面図である。以下、Si等の半導体基板上に設
けた一実施例につき、本発明のインダクタの構造、及び
その製作手順を説明する。
1A and 1B are explanatory views of an inductor for a semiconductor device according to the present invention, wherein FIG. 1A is a plan view thereof, and FIG.
Is a sectional view thereof. Hereinafter, the structure of the inductor of the present invention and the manufacturing procedure thereof will be described for one embodiment provided on a semiconductor substrate such as Si.

【0016】先ず半導体基板6上に、CVD等により例
えばSiO2 等の絶縁膜5を形成させるが、この絶縁膜
5は下地絶縁膜として他の素子の形成にも利用されるも
のである。
First, an insulating film 5 made of, for example, SiO2 is formed on a semiconductor substrate 6 by CVD or the like. This insulating film 5 is also used as a base insulating film for forming other elements.

【0017】次に、絶縁膜5の上面にCVD等によりS
iO2 等の絶縁膜4を堆積させ、同絶縁膜の選択エッチ
ングにより櫛歯状に交互に平行する複数個の凸状部8を
形成する。この工程により底面に絶縁膜5の面をもつ凹
状部が形成される。段差部7は次工程で行う配線を確実
にするために、順テーパーをもつように形成する必要が
あり、ドライエッチング等により行うが、ウエットエッ
チングで行う場合は、アンダーカットを防ぐため、絶縁
膜の材質とエッチング液の組成との調節が必要である。
Next, S is formed on the upper surface of the insulating film 5 by CVD or the like.
An insulating film 4 of iO2 or the like is deposited, and a plurality of convex portions 8 which are alternately parallel in a comb shape are formed by selective etching of the insulating film. By this step, a concave portion having the surface of the insulating film 5 is formed on the bottom surface. The step portion 7 needs to be formed to have a forward taper in order to ensure the wiring to be performed in the next step. The step portion 7 is formed by dry etching or the like. It is necessary to adjust the material and the composition of the etching solution.

【0018】また、絶縁膜4としてポリイミドを用いる
こともできる。この場合は、スピンコートにより膜を形
成し、同様にエッチングにより凸状部を形成するが、素
材の性質から段差部は順テーパー状となる。
Also, polyimide can be used as the insulating film 4. In this case, a film is formed by spin coating, and a convex portion is similarly formed by etching, but the step portion has a forward tapered shape due to the nature of the material.

【0019】次に、上記により構成した段差つきの絶縁
膜上に、スパッタ、蒸着等によりAl、Au等の金属薄
膜を被着させ、選択箇所を残してエッチングすることに
より、平行する凸状部8、凹状部9に沿って延び、段差
部7で折り返すメアンダ型の薄膜コイルが形成される。
上記薄膜コイルの形成は、FIB装置等を用い配線材料
を直接描画し、被着させる方法によっても可能である。
Next, a metal thin film of Al, Au, or the like is deposited on the stepped insulating film by sputtering, vapor deposition, or the like, and is etched while leaving selected portions, thereby forming the parallel convex portions 8. A meander-type thin-film coil extending along the concave portion 9 and folding back at the step portion 7 is formed.
The above-mentioned thin film coil can be formed by a method in which a wiring material is directly drawn using a FIB apparatus or the like and applied.

【0020】上記のように構成することにより、配線構
造が立体的となるので、同一実装密度に対し、従来のも
のに比べ、実質的に配線間隔が広いインダクタを実現す
ることができる。
With the above configuration, since the wiring structure becomes three-dimensional, it is possible to realize an inductor having a wiring space substantially wider than that of the conventional one for the same mounting density.

【0021】[0021]

【発明の効果】以上説明したように、本発明の半導体装
置用インダクタは、絶縁膜を櫛歯状に交互に平行する複
数個の凸状部および凹状部を有するように段差をつけた
形状に形成し、前記凸状部および凹状部に沿った配線及
び前記段差部での折り返し配線によりメアンダ型のコイ
ルを構成したので、配線間隔を実質的に大きくすること
ができ、メアンダ型の弱点である配線間隔の狭小に伴う
インダクタンス値の低減の問題が緩和される。
As described above, the inductor for a semiconductor device according to the present invention has a shape in which an insulating film is stepped so as to have a plurality of convex portions and concave portions which are alternately parallel in a comb shape. The meander-type coil was formed by forming the wiring along the convex and concave portions and the folded wiring at the step, so that the wiring interval could be substantially increased, which is a weak point of the meander type. The problem of a reduction in the inductance value due to the narrowing of the wiring interval is alleviated.

【0022】このため、巻数が大きい場合に特別にQの
低下がないメアンダ型の利点をもちながら、実装効率の
よいメアンダ型のインダクタを実現することができる。
Therefore, it is possible to realize a meander-type inductor having good mounting efficiency while having the advantage of the meander-type in which Q is not particularly reduced when the number of turns is large.

【0023】また、本発明の特徴である上記の段差を有
する絶縁膜は、半導体基板上の所定範囲一面に第1絶縁
膜を堆積する工程、該第1絶縁膜上に、第2絶縁膜を堆
積し、該第2絶縁膜を選択エッチングする工程を用いる
ことにより容易に形成することができる。
Further, the insulating film having the above-mentioned steps, which is a feature of the present invention, is a step of depositing a first insulating film over a predetermined area on a semiconductor substrate, and forming a second insulating film on the first insulating film. It can be easily formed by using a process of depositing and selectively etching the second insulating film.

【0024】また、本発明のインダクタは、ビアホール
による配線接続等を含む複雑な2層配線を必要とぜず、
比較的簡易な一層配線で製作できる利点をもっている。
Further, the inductor of the present invention does not require complicated two-layer wiring including wiring connection by via holes, etc.
It has the advantage that it can be manufactured with relatively simple single-layer wiring.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置用インダクタの一実施例の
説明図であり、(a)はその平面図、(b)はその断面
図である。
FIGS. 1A and 1B are explanatory views of one embodiment of an inductor for a semiconductor device according to the present invention, wherein FIG. 1A is a plan view and FIG.

【図2】従来のスパイラル型半導体装置用インダクタの
説明図であり、(a)はその平面図、(b)はその断面
図である。
FIGS. 2A and 2B are explanatory diagrams of a conventional inductor for a spiral type semiconductor device, wherein FIG. 2A is a plan view and FIG.

【図3】従来のメアンダ型半導体装置用インダクタの説
明図であり、(a)はその平面図、(b)はその断面図
である。
3A and 3B are explanatory diagrams of a conventional meander-type semiconductor device inductor, in which FIG. 3A is a plan view and FIG. 3B is a cross-sectional view thereof.

【符号の説明】[Explanation of symbols]

1 コイル部配線 2 引出し配線 3 ビアホール 4、5 絶縁膜 6 半導体基板 7 段差部 8 凸状部 9 凹状部 DESCRIPTION OF SYMBOLS 1 Coil part wiring 2 Lead-out wiring 3 Via hole 4, 5 Insulating film 6 Semiconductor substrate 7 Step part 8 Convex part 9 Concave part

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上の絶縁膜上に設けられ、薄
膜状の配線で構成される半導体装置用インダクタにおい
て、前記絶縁膜を櫛歯状に交互に平行する複数個の凸状
部および凹状部を有するように段差をつけた形状に形成
し、前記凸状部及び凹状部に沿って形成した配線部分及
び前記段差部分に形成した折り返し配線部分によりメア
ンダ型のコイルを構成したことを特徴とする半導体装置
用インダクタ。
1. A semiconductor device inductor provided on an insulating film on a semiconductor substrate and comprising thin-film wiring, wherein said insulating film has a plurality of convex portions and concave portions which are alternately parallel in a comb shape. Formed in a shape with a step so as to have a portion, and a meander type coil is configured by a wiring portion formed along the convex portion and the concave portion and a folded wiring portion formed in the step portion. For semiconductor devices.
【請求項2】 半導体基板上の絶縁膜上に設けられ、薄
膜状の配線で構成される半導体装置用インダクタの製造
方法において、前記半導体基板上の所定範囲一面に第1
絶縁膜を堆積する工程、該第1絶縁膜上に第2絶縁膜を
堆積し、該第2絶縁膜を選択エッチングにより複数個の
凸状部を、その段差部分が順テーパー状になるように形
成する工程、及び前記第1絶縁膜、第2絶縁膜の上面に
配線材料を堆積し、エッチングにより、又は配線材料の
直接描写によりコイル部を形成する工程、を含むことを
特徴とする半導体装置用インダクタの製造方法。
2. A method for manufacturing an inductor for a semiconductor device, which is provided on an insulating film on a semiconductor substrate and includes thin-film wirings, wherein a first area over a predetermined area on the semiconductor substrate is provided.
Depositing an insulating film, depositing a second insulating film on the first insulating film, and selectively etching the second insulating film so that a plurality of convex portions are formed so that the steps become forward tapered. Forming a coil portion by depositing a wiring material on an upper surface of the first insulating film and the second insulating film and etching or directly drawing the wiring material. Of manufacturing inductors for automobiles.
JP26782397A 1997-09-12 1997-09-12 Inductor for semiconductor device and manufacturing method thereof Expired - Fee Related JP3733219B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26782397A JP3733219B2 (en) 1997-09-12 1997-09-12 Inductor for semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26782397A JP3733219B2 (en) 1997-09-12 1997-09-12 Inductor for semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH1187618A true JPH1187618A (en) 1999-03-30
JP3733219B2 JP3733219B2 (en) 2006-01-11

Family

ID=17450113

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26782397A Expired - Fee Related JP3733219B2 (en) 1997-09-12 1997-09-12 Inductor for semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP3733219B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002324962A (en) * 2001-02-21 2002-11-08 Toppan Printing Co Ltd Inductor built-in printed wiring board and its manufacturing method
JP2004327941A (en) * 2003-04-28 2004-11-18 Nec Electronics Corp Semiconductor device
JPWO2005024949A1 (en) * 2003-08-28 2006-11-16 株式会社日立製作所 Semiconductor device and manufacturing method thereof
US8109612B2 (en) 2005-08-29 2012-02-07 Fujifilm Corporation Wiring substrate, method of manufacturing wiring substrate, and liquid droplet ejection head

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002324962A (en) * 2001-02-21 2002-11-08 Toppan Printing Co Ltd Inductor built-in printed wiring board and its manufacturing method
JP2004327941A (en) * 2003-04-28 2004-11-18 Nec Electronics Corp Semiconductor device
JP4519418B2 (en) * 2003-04-28 2010-08-04 ルネサスエレクトロニクス株式会社 Semiconductor device
JPWO2005024949A1 (en) * 2003-08-28 2006-11-16 株式会社日立製作所 Semiconductor device and manufacturing method thereof
JP4497093B2 (en) * 2003-08-28 2010-07-07 株式会社日立製作所 Semiconductor device and manufacturing method thereof
US8109612B2 (en) 2005-08-29 2012-02-07 Fujifilm Corporation Wiring substrate, method of manufacturing wiring substrate, and liquid droplet ejection head

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