JPH1185832A - Circuit conversion method, circuit design supporting device and record medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a circuit which reduces operation processing quantity that is needed for simulation execution even for a circuit which has much signal operation execution quantity by deciding a data operating part which is executed after control condition that is related to an operation result of the data operating part. SOLUTION: A control condition data operation relation extracting part 10 specifies control conditioning parts and a data operating part in a simulation mode 100 and seeks the correspondence relation of each control conditioning part and the data operating part. A condition execution model deciding part 20 decides a description part that is continuously executed when a specific control condition is established, based on the correspondence relation of the control conditioning part and the data operating part which has been extracted by the part 10. A condition execution model integrating part 30 integrates a partial model that is decided by the part 20 to the data operating part, which corresponds to a control condition and outputs circuit description (simulation model) 101, whose operation execution quantity is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a design support apparatus for supporting digital circuit design, and more particularly, to a circuit conversion method for converting a simulation model into a simpler model for speeding up a logic simulation, and a circuit conversion method using the same. The present invention relates to a design support device.

[0002]

2. Description of the Related Art In the design of computer systems and LSIs, it is indispensable to verify a designed circuit by logic simulation and to find defects in design logic at an early stage in order to shorten the development period.

On the other hand, the time required for logic simulation is proportional to the size of a circuit to be verified. Therefore, the time required for logic simulation has been increasing with the recent increase in the degree of integration of LSIs. At present, the execution speed of a logic simulator is, for example, only about several clocks / sec for a circuit having a scale of 100K gates. Therefore, in a large-scale LSI, it is difficult to perform design verification by simulation using a test vector having a sufficient length. In particular, LSI
Considering the case where a defect occurs after manufacturing, the cost increases extremely during the period required for development, such as modification and re-verification of the design logic. For these reasons, designers have further desired to realize a high-speed logic simulator.

[0004] The logic simulator is usually realized by software. A circuit verified by a logic simulator implemented by software is often expressed using a language suitable for executing software. For example, it is a high-level language represented by C language and assembly language. In recent years, a large number of logic simulators having a circuit described in a hardware description language (HDL) such as VHDL or Verilog-HDL as an input have appeared. Most of these logic simulators convert an input circuit into a corresponding circuit description written in C language or assembly language and execute it. The conversion method to computer language is optimized or the description after conversion is optimized. The speeding up of the simulation has been achieved by the development.

However, the speedup by the logic simulator described above is based solely on the HDL processing method, and does not reduce the amount of calculation itself required to execute the circuit simulation.

A system design using HDL is usually described in RTL (register transfer level) on the premise of logic synthesis. When a circuit is described in RTL, various arithmetic functions in the circuit are often realized by a state transition using a clock as an operation unit (for example, represented as a transition between processes). In this case, the circuit describes, for example, a plurality of processes and signals, variables, and the like that are transferred between the plurality of processes. In the state transition, the state and the execution operation in the next clock are determined by the current state and the control condition at that time, and signals and the like are frequently exchanged between a plurality of states. Each operation is executed in parallel, and a large number of signals are used for storing intermediate operation results.

On the other hand, in the case of a behavioral description (behavioral description) not premised on logic synthesis, a circuit is described so as to obtain an output result for an input signal in a procedural manner. For this reason,
Each operation is executed serially, and the number of signals used for storing intermediate operation results is small. Further, since there is usually no accuracy up to the operation in clock units, the amount of signal operation is smaller than when the circuit is described in RTL.

[0008] This means that the circuit described in RTL is
This means that the amount of signal operation is much larger than that of a circuit at an operation level that does not assume logic synthesis, which means that it takes a lot of time to execute a simulation.

[0009]

As described above, as described above,
A circuit described in RTL, particularly using state transition, requires a much larger amount of signal operation than a circuit of an operation level that does not assume logic synthesis. On the other hand, the speedup by the conventional logic simulator is based on a device in the HDL processing method, and does not reduce the calculation amount itself of the circuit description as described above. Therefore, there is a problem that it takes a lot of time to execute a simulation of a circuit described in RTL.

The present invention has been made in view of the above problems, and has been made in consideration of the above-described problems.
Circuit description method using L and the state transition) so as to reduce the amount of signal operation, and reduce the time required for operation verification (simulation execution), and a design support method using the circuit conversion method. It is intended to provide a device.

[0011]

According to a first aspect of the present invention, there is provided a circuit conversion method for extracting a correspondence between a control condition and a data operation unit from a description of an input circuit, and calculating an operation result of the data operation unit. By determining a data operation unit to be executed subsequent to the control condition related to the above, and integrating the control condition and the data operation unit based on the determination result, for example, the signal operation execution amount described in RTL is large. As for the circuit, it is possible to obtain a circuit in which the amount of arithmetic processing required for executing the simulation is reduced.

Preferably, when integrating the control condition and the data operation unit, a redundant circuit description (control condition, signal assignment statement, and variable assignment statement) included in the data operation unit is deleted, so that the simulation is performed. In this case, it is possible to eliminate a waste of machine cycles spent for decoding unnecessary instruction sentences, and thus it is possible to obtain a circuit with a further reduced signal operation amount.

A circuit design support device according to the present invention (claim 3)
Determining, from the input circuit description, an extraction unit for extracting a correspondence between the control condition and the data operation unit, and a data operation unit to be executed following the control condition related to the operation result of the data operation unit. And integrating means for integrating the control condition and the data arithmetic unit based on the result of the determination. For example, even for a circuit with a large signal arithmetic execution amount described in RTL, the simulation execution is required. A circuit with a reduced amount of arithmetic processing can be obtained.

Further, the circuit design support apparatus of the present invention is characterized in that an extracting means for extracting a correspondence between a control condition and a data operation unit from an input circuit description, and an operation result of the data operation unit. Determining a data operation unit to be executed subsequent to the control condition related to the control unit, and executing an operation of the integrated circuit by the integration unit integrating the control condition and the data operation unit based on the determination result. For example, a circuit with a reduced amount of computation required for executing a simulation can be obtained even for a circuit with a large amount of signal computation executed in RTL. High-speed logic simulation becomes possible.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a circuit design support apparatus (circuit conversion apparatus) 1 using a circuit conversion method according to a first embodiment.
Is a schematic diagram showing an example of the configuration of the circuit. The description of a circuit to be verified for operation (hereinafter, the description of the circuit may be referred to as a simulation model) 100 to the correspondence between a control condition part and a data operation part. And a condition execution model determining unit 20 for determining a partial model to be executed following a specific control condition
And a condition execution model integration unit 30 that integrates the determined partial model into a data operation unit corresponding to the control condition.

According to the circuit design support apparatus according to the first embodiment, the circuit description is converted by the RTL, particularly for a circuit described using state transitions, so that the signal calculation amount is reduced. This makes it possible to reduce the time required for executing the simulation. In other words, a high-speed logic simulation can be performed by using a circuit description with a reduced signal operation amount as an input to the logic simulator.

Hereinafter, the circuit design support apparatus 1 according to the present embodiment will be described in more detail. The control condition data calculation relationship extraction unit 10 receives the simulation model 1
The control condition part and the data calculation part in 00 are specified, and the correspondence between each control condition part and the data calculation part is obtained. Here, the control condition part in the simulation model refers to, for example, a description part for condition determination of an if statement or a case statement, and the data operation part refers to a description part for actually executing signal substitution execution. Further, the correspondence between the control condition unit and the data calculation unit refers to, for example, associating a data calculation unit executed according to the result of the condition determination of the control condition unit.

The condition execution model judging section 20 is configured to execute the following processing when a specific control condition is established based on the correspondence between the control condition section and the data operation section extracted by the control condition data operation relation extracting section 10. Determine the description part to be executed.

The condition execution model integration unit 30 integrates the partial model determined by the condition execution model determination unit 20 into a data calculation unit corresponding to a control condition, and describes a circuit description (simulation model) with a reduced calculation execution amount. ) 101 is output.

Next, the circuit conversion method according to this embodiment will be specifically described using a simple simulation model. FIG. 2 illustrates a circuit to be verified in VHDL as an example of a simulation model input to the circuit design support device of FIG. p1, p20, p
Four processes of 70 and p2 (event processing execution unit)
Consists of This circuit represents a part of the operation of a simple vending machine. It is assumed that a user inputs three types of coins of 10 yen, 50 yen, and 100 yen and purchases a product of 30 yen. .

This circuit is described using state transitions. Signals in_10, in_50, and in_100 are used to input a coin of 10, 50, and 100 yen, respectively, and to input a signal c.
current_state represents a state corresponding to the amount of money put into the vending machine. Input amount (current_
When the “state” reaches 30 yen, the signal “enough_money” indicating that the product can be purchased is “1”.
And the signal over_ corresponds to the surplus amount at that time.
10 to over_90 are set to “1”. In FIG. 2, in each of the processes p1, p20, p70, and p2, signals enough_money, in_10, in_50,
A change in the values of in_100 and over_10 to over_90 occurs, and a process is subsequently performed from a certain process to another process to cause a state transition.

Although omitted in FIG. 2, it is assumed that the updated amount of money (next_state) is reset as the current amount of money every clock. Here, the VHDL description is used as the input circuit, but it may be represented by a circuit diagram or a netlist.

The control condition data operation relation extracting unit 10 obtains the correspondence between the control condition unit and the data operation unit from the description of FIG. FIG. 3 shows the result of determining the control condition part and the data calculation part in the description of FIG. [1] ~
[10] is a control condition part, and (a) to (j) are data calculation parts.

FIG. 4 shows the relationship between each control condition section and the data calculation section. In FIG. 4, the corresponding control condition units [1] to [10] and the data operation units (a) to (j) are connected by straight lines. For example, the control condition unit [1] corresponds to the data operation unit (a).

Next, the condition execution model determination unit 20 determines a partial model in the circuit executed following the appropriate control condition (for example, a data operation unit executed following the appropriate control condition).

First, the control condition data calculation relation extraction unit 10
From the correspondence between the control condition part and the data calculation part obtained in
The dependency between each control condition part and the data calculation part is obtained. Here, for example, of the control condition units [8] to [10] corresponding to each state of the state transition, attention is paid to [9] and [10].

In the data operation unit (i) corresponding to the control condition unit [9], the signal operation is substituted into the signal "enough_money". On the other hand, in the process p1, the signal eno
having high_mony in the sensitivity signal, e
It is driven by the event (change in value) of now_money. Similarly, the signal o in the data operation unit (i)
Since the assignment is made to the ver_20, the signal over_2
The process p20 having 0 as the sensitivity signal is driven. Therefore, the process p1 and the process p20 are executed following the execution of the data operation unit (i).

FIG. 5 shows the dependencies determined by the condition execution model determination unit 20. As shown in FIG. 5, the partial models executed when the control condition indicated by the control condition section [9] is satisfied are determined to be the process p1 and the process p20 (201 in FIG. 5). Similarly, the partial models executed under the control conditions indicated by the control condition section [10] are determined to be the process p1 and the process p70 (202 in FIG. 5).

The condition execution model integration unit 30 integrates the partial model determined by the condition execution model determination unit 20 into a data operation unit corresponding to the control condition unit. Here, the integration can be realized, for example, by the following procedure. (Procedure 1) A partial model to be executed following the data operation unit is fetched after the data operation unit. (Procedure 2) A signal used for passing a value between the data operation unit and the partial model is replaced with a variable.

The reason why the signal is replaced with the variable in the procedure 2 is to adjust the timing as a result of the signal operation being executed in a separate process by the integration and being executed in the same process. Further, by replacing the signal with a variable, for example, the amount of information transferred from one process to another process at the time of state transition can be reduced.

FIG. 6 is a VHDL description as a result of applying the integration to FIG. Since the data operation units corresponding to the control conditions [9] and [10] are (i) and (j), respectively, first, a partial model including processes p1 and p20,
The partial models composed of the processes p1 and p70 are arranged after (i) and (j), respectively.

Next, signals used for propagation of values between processes, ie, "enough_mode" and "over_2"
Replace 0 and over_70 with variables. In this way, the two partial models are integrated into the process p2 to obtain FIG.

In this example, for the sake of simplicity, a case where there is no dependency between the processes constituting the integrated partial models is dealt with. However, if there is a dependency, the process is performed according to the dependency between those processes. Leveling is performed, and processes are arranged in order of level.

In this example, for simplicity, a description that does not include a hierarchy is used as an input circuit. However, if the input circuit includes a hierarchy, the circuit is developed in advance into a flat description without a hierarchy, What is necessary is just to integrate partial models.

As described above, in the circuit description obtained by integrating the partial models executed following the appropriate control conditions, the circuit description has a serial structure, and the amount of operation required for the simulation is reduced. . Further, among the signals in the integrated partial model, those whose values are passed from the integrated data processing unit are replaced with variables, so that the signal processing operation is replaced with the variable operation, and the processing can be performed at higher speed. .

Therefore, according to the present embodiment, it is possible to obtain a circuit in which the amount of arithmetic processing required for executing a simulation is reduced even for a circuit in which the amount of signal arithmetic execution described in RTL is large. (Second Embodiment) Using the circuit conversion method described in the first embodiment, an input circuit is converted into a circuit description (simulation model) with a reduced amount of arithmetic processing,
A circuit design support device that executes a logic simulation will be described.

FIG. 7 schematically shows a configuration example of a circuit design support apparatus according to the second embodiment. The circuit design support apparatus (circuit conversion apparatus) 1 of the first embodiment shown in FIG. The provided control condition data operation relation extraction unit 10, condition execution model determination unit 20, and condition execution model integration unit 30 further include a logic simulation execution unit 90 for executing a logic simulation based on a given circuit description. ing. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description will be omitted.

As the logic simulation execution section 90, a known one is used. The circuit description to be subjected to the logic simulation is converted into a circuit description with a small signal operation amount by the control condition data calculation relation extracting unit 10, the condition execution model determination unit 20, and the condition execution model integration unit 30, and the converted circuit description is input. As the logic simulation execution unit 9
The logic simulation is executed by using 0.

As described above, by providing the circuit conversion device 1 for reducing the amount of execution of the circuit description in the preceding stage of the well-known logic simulation execution unit 90, it is possible to realize a logic simulation device for executing a logic simulation at high speed. . Third Embodiment FIG. 8 is a circuit design support apparatus (circuit conversion apparatus) 2 using a circuit conversion method according to a third embodiment.
Is a schematic diagram showing an example of the configuration, and extracts correspondences between control conditions and data calculation units from an input circuit description (hereinafter, a circuit description may be called a simulation model) 100 to be verified. The control condition data calculation relation extraction unit 10 performs a condition execution model determination unit 20 that determines a partial model to be executed following a specific control condition, and integrates the determined partial model into a data calculation unit corresponding to the control condition. And a redundant control condition deleting unit 40 for deleting redundant control conditions or redundant signal assignment statements or redundant variable assignment statements from the integrated partial model.
Is provided.

According to this embodiment, even for a circuit described in RTL, the time required for executing a simulation can be reduced by converting the circuit description so as to reduce the signal operation amount. . That is, after the circuit description is converted so that the signal operation amount is reduced, the signal operation amount of the circuit can be further reduced.

Hereinafter, the circuit design support apparatus 2 according to the present embodiment will be described in more detail. In FIG. 8, a control condition data calculation relation extraction unit 10, a condition execution model determination unit 2
0 and the condition execution model integration unit 30 are the same as in the first embodiment.

The control condition data calculation relationship extracting unit 10 specifies the control condition unit and the data calculation unit in the input circuit 100, and obtains the correspondence between each control condition unit and the data calculation unit. Here, the control condition part is, for example, an if statement or cas
The condition determination portion and the data operation portion of the e-statement indicate a portion that actually performs signal substitution execution.

Based on the correspondence between the control condition part and the data calculation part extracted by the control condition data calculation relation extraction means 10, the condition execution model determination part 20 continues when a specific control condition is satisfied. Determine the part to be executed.

The condition execution model integration unit 30 integrates the partial model determined by the condition execution model determination unit 20 into a data operation unit corresponding to the control condition. The redundant control condition deletion unit 40 deletes a redundant control condition or a data operation unit corresponding to the control condition included in the partial model integrated by the condition execution model integration unit 30.

Next, the circuit conversion method according to this embodiment will be specifically described using a simple simulation model. The VHDL description of FIG. 2 is used again as the input circuit 100. Here, the VHDL description is used as the input circuit, but it may be represented by a circuit diagram or a netlist.

The processing executed by the condition execution model integrating unit 30 from the control condition data operation relation extracting unit 10 is the first process.
This is the same as the description in the embodiment. As a result, as in the first embodiment, a VHDL description as shown in FIG. 6 is obtained.

In FIG. 6, the integrated partial model includes redundant control conditions and a data operation unit. FIG. 9 shows this redundant description portion surrounded by a solid line. FIG. 10 shows the VHDL description of FIG. 9 in correspondence between the control condition part and the data operation part. The portion surrounded by hatching is the redundant description portion in FIG. As is clear from FIG. 9, the redundant description part is a statement that is meaningless in the execution of processing, and deleting such a redundant description part is spent for decoding the useless statement. This is effective for reducing waste of machine cycles.

The redundancy control condition deletion unit 40 is provided in the VHD of FIG.
The redundant description in the L description is deleted. The method of detecting a redundant description portion can be realized, for example, by detecting that a constant substitution is performed on a signal or a variable used in a control condition immediately before the control condition.

FIG. 11 shows the result of deleting the redundant description. In this way, redundant control conditions or redundant signal assignment statements can be deleted. Here, the variable values of over_20 and over_70 are stored in the process p2.
Given the case where it is not referenced in the rest of
Assignment statements to r_20 and over_70 are also redundant and can be deleted. FIG. 12 shows this redundant description surrounded by a solid line. Therefore, the description shown in FIG. 13 is obtained by deleting the redundant description from the VHDL description of FIG. 6 by the redundant control condition deletion unit 40. In this way, redundant variable assignment statements can be deleted.

As described above, a redundant control condition or redundant signal assignment statement or redundant variable assignment statement is obtained from a circuit description obtained by integrating partial models executed following appropriate control conditions. By removing
Further, a circuit with a reduced amount of signal operation can be obtained.

Therefore, according to the present embodiment, it is possible to obtain a circuit description with a reduced amount of calculation processing required for executing a simulation even for a circuit description described in RTL with a large signal calculation execution amount. (Fourth Embodiment) Using the circuit conversion method described in the third embodiment, an input circuit is converted into a circuit description (simulation model) with a reduced amount of arithmetic processing,
A circuit design support device that executes a logic simulation will be described.

FIG. 14 schematically shows an example of the configuration of a circuit design support apparatus according to the fourth embodiment.
The control condition data operation relation extraction unit 10, the condition execution model determination unit 20, the condition execution model integration unit 30, and the redundant control condition deletion unit 40 included in the circuit design support device (circuit conversion device) 2 according to And a logic simulation execution unit 90 for executing a logic simulation based on the given circuit description. The same parts as those in FIG. 8 are denoted by the same reference numerals, and detailed description will be omitted.

As the logic simulation execution unit 90, a known one is used. The circuit description 100 to be subjected to the logic simulation is converted into a circuit description with a small signal operation amount by the control condition data operation relation extraction unit 10, the condition execution model determination unit 20, the condition execution model integration unit 30, and the redundant control condition deletion unit 40. Then, the logic simulation is executed by the logic simulation executing unit 90 using the converted circuit description as an input.

As described above, by providing the circuit conversion device 2 for reducing the amount of execution of the circuit description in the preceding stage of the well-known logic simulation execution unit 90, a logic simulation device that executes a logic simulation at high speed can be realized. .

It should be noted that the present invention is not limited to the configuration described in each of the embodiments described above, and can be implemented as appropriate or in any combination. In addition, the methods described in the above embodiments, or the methods obtained by combining them arbitrarily or arbitrarily, include magnetic disks (floppy disks, hard disks, etc.), optical disks (CD-ROM, DVDs, etc.), and stored in a recording medium such as a semiconductor memory for distribution. That is, the program can be stored in a computer-readable storage medium as a program to be controlled by the computer, and the computer can read the program from the storage medium and execute the program on the computer.

[0056]

As described above, according to the present invention, it is possible to convert an input circuit described in, for example, PTL, in particular, described in a state transition, into a circuit in which the amount of operation executed is reduced. The speed of the logic simulation can be increased.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a circuit design support apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a VHDL description of an input circuit.

FIG. 3 is a diagram illustrating an example of determination by a control condition unit and a data calculation unit;

FIG. 4 is a diagram showing a correspondence relationship between a control condition unit and a data calculation unit.

FIG. 5 is a diagram showing a partial model executed following a control condition.

FIG. 6 is a diagram showing a VHDL description of a circuit in which partial models are integrated.

FIG. 7 is a diagram showing a configuration of a circuit design support device according to a second embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a circuit design support device according to a third embodiment of the present invention.

FIG. 9 is a diagram showing a redundant description part in FIG. 6;

FIG. 10 is a diagram illustrating a correspondence relationship between a control condition unit and a data calculation unit corresponding to FIG. 9;

FIG. 11 is a view showing a VHDL description in which a redundant description part in FIG. 6 is deleted.

FIG. 12 is a diagram showing a redundant assignment statement in FIG. 9;

FIG. 13 is a view showing a VHDL description in which redundant assignment statements in FIG. 9 are deleted.

FIG. 14 is a diagram showing a configuration of a circuit design support device according to a fourth embodiment of the present invention.

[Explanation of symbols]

 1, 2 ... Circuit design support device (circuit conversion device) 10 ... Control condition data operation relation extracting unit 20 ... Conditional execution model determining unit 30 ... Conditional execution model integrating unit 40 ... Redundant control condition unit deleting unit 90 ... Logic simulation executing unit 100, 101: Simulation model (circuit description)

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masami Aihara 580-1, Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Semiconductor System Technology Center Co., Ltd. (72) Seiichi Nishio Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa No. 580 No. 1 Toshiba Semiconductor System Engineering Center

Claims (7)

[Claims] 1. A correspondence between a control condition and a data operation unit is extracted from an input description of a circuit, and a data operation unit to be executed following a control condition related to an operation result of the data operation unit is determined. And integrating the control condition and the data operation unit based on the determination result. 2. The circuit conversion method according to claim 1, wherein when the control condition and the data operation unit are integrated, a redundant circuit description included in the data operation unit is deleted. 3. An extracting means for extracting a correspondence between a control condition and a data operation unit from a description of an input circuit, and a data operation unit executed following the control condition relating to the operation result of the data operation unit. And an integrating means for integrating the control condition and the data operation unit based on the result of the determination. 4. Extraction means for extracting a correspondence between a control condition and a data operation unit from a description of an input circuit, and a data operation unit executed following the control condition related to the operation result of the data operation unit And an executing means for executing the operation of the circuit integrated by the integrating means, based on the result of the determination. Design support equipment. 5. The circuit design support apparatus according to claim 3, wherein when the control condition and the data operation unit are integrated, a redundant circuit description included in the data operation unit is deleted. 6. A machine-readable recording medium on which a program for converting an input circuit description is recorded, wherein a correspondence between a control condition and a data operation unit is extracted from the input circuit description. Extracting means; and integrating means for judging a data operation unit to be executed following a control condition related to the operation result of the data operation unit, and integrating the control condition and the data operation unit based on the judgment result. A recording medium on which a program to be executed is recorded. 7. A machine-readable recording medium that records a program for executing an operation of the circuit by converting an input description of the circuit, and includes a control condition and a control condition based on the input circuit description. Extracting means for extracting the correspondence of the data operation unit; determining a data operation unit to be executed following a control condition relating to the operation result of the data operation unit; and determining the control condition and the data operation based on the determination result. A recording medium storing a program for executing: an integrating means for integrating the units; and an executing means for executing the operation of the circuit integrated by the integrating means.