JPH1185677A - Bus interface unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate an instruction code or processing time with processing for masking an excessive data part after reading the data of bit width narrower than that of a general-purpose register by an instruction for performing code expansion from a peripheral I/O. SOLUTION: When reading 16-bit data on an external memory through an external data bus 60 as 32-bit data, the 1st and 0th bits of an address are detected by an address decoder 49. Thus, the data on an external data bus are stored in the loworder 16 bits of a read buffer in a first bus cycle, and the data outputted by a high-order bit setting circuit are stored in the high-order 16 bits of the read buffer in a second bus cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bus interface unit, and more particularly to a bus interface unit for storing data in a register having a bit width larger than the bit width of an external bus.

[0002]

2. Description of the Related Art In recent years, microprocessors have been connected to various peripheral devices in order to diversify their functions. Therefore, the bit width of the general-purpose register in the microprocessor may be different from the bit width of the external bus.

In order to unify such a difference in bit width, data is stored in a general-purpose register of a microprocessor. A code that extends to the data length of the general-purpose register using the most significant bit of the read data as a code bit is used. There is an extension and a zero extension that extends a higher-order bit of the read data to “0” to the bit width of the general-purpose register.

[0004] Sign extension and zero extension will be described by taking as an example a case where 16-bit data is read from a peripheral I / O and stored in a 32-bit general-purpose register in a microprocessor.

First, the sign extension will be described.

The most significant bit of 16-bit data composed of bits 0 to 15 is bit 15, which is a sign bit representing the sign of the data. In the case of sign extension, upper 16-bit data of a 32-bit general-purpose register is determined by the state of the sign bit.

The data whose code bit is "1", for example, the read peripheral I / O data is 8000H (H is h
Represents an exadecimal [hex] representation. ), The sign bit is the upper one of the 32-bit general-purpose register.
Expanded to 6 bits, FFFF8000 in general-purpose register
H is stored. Assuming that data with a sign bit of “0”, for example, 7000H, is read, 00007000H is stored in the general-purpose register.

In the case of zero extension, regardless of the sign bit,
"0" is extended to the upper 16 bits of the general-purpose register. For example, if A000H is read, 0000A0
00H is stored in the general-purpose register.

In a microprocessor employing the RISC architecture, the number of instructions is limited in order to minimize the number of instructions. For this reason, many microprocessors are provided with only a sign extension for data read instructions.

If a microprocessor having only a read instruction for sign extension reads 16-bit data whose sign bit is "1" in a 32-bit general-purpose register, the upper 16 bits of the 32-bit data stored are It becomes “1”. Therefore, in processing such as comparison with immediate data, it is necessary to set the upper 16 bits to “0” before performing data processing.

Conventionally, a method has been adopted in which the upper 16 bits of 32-bit data stored in a general-purpose register are set to "0" (hereinafter, masked to "0"). This type of bus interface unit (hereinafter, referred to as BIU) performs processing as shown in the first conventional example.

FIG. 7 is a block diagram showing a microprocessor system having only the instruction for sign extension shown as the first conventional example. 599 is a microprocessor, 10
Is a CPU, 20 is a 32-bit general-purpose register group, and 530
Is BIU, 80 is A / D converter circuit section, 89 is 16
Bit A / D converters, 81 to 84 are 16-bit A / D conversion result registers, 32 is a 32-bit internal bus, 60 is a 16-bit external data bus, and 70 is 32
External address bus for bits. The CPU 10
The IU 530 is connected to the internal bus 32.

The BIU 530 includes a data input unit 540 shown in FIG.

In FIG. 1, reference numeral 42 denotes an input control unit;
A 2-bit read buffer 544 has an external address
Bits 1 (hereinafter referred to as A1 signal) and 43 of the bus are read signals (hereinafter referred to as RD signals).

The function of the data input unit 540 will be described. The 16-bit data on the external data bus 60 is output from the input control circuit 42 to the read buffer 41 when the RD signal 43 is “1”. A1 signal 44 is "0"
, The output of the input control circuit 42 is stored in the lower 16 bits of the read buffer 41. Conversely, when the A1 signal 44 is "1", the output of the input control circuit 42 is stored in the upper 16 bits of the read buffer 41.

The input control circuit 42 outputs the contents of the external data bus 60 to the read buffer 41 when the RD signal 43 is "1". When the RD signal 43 is "0", the output of the input control circuit 42 has high impedance.

Hereinafter, data having a 4-byte (32-bit) structure is called a word, and data having a 2-byte (16-bit) structure is called a halfword. 8, 92 is a half word access signal, 93 is a word access signal,
94 is a second cycle signal, both of which are BIU530
From the control circuit (not shown) to the address output circuit 6
00 is output. Also, the address output circuit 600
Processes the address calculated by the CPU 10 from the internal bus 32 and outputs the processed address to the external address bus 70.

When a halfword access instruction is executed by the microprocessor, a halfword access signal 9 is output.
2 becomes "1", indicating that it is a halfword access. Similarly, when the word access instruction is executed, the word access signal 93 becomes "1", indicating that the access is the word access. When the second cycle signal 94 is "1"
Indicates that it is the second cycle.

The data input section 540 includes an address output circuit 600 shown in FIG. Address output circuit 6
00 will be described.

In FIG. 9, 602 and 604 are 2-input AND circuits, 601 is a 2-input NOR circuit, 603 is an inverter, 605 is a 2-input OR circuit, and 716 is bit 0 of the internal bus 32 (hereinafter, O_A0 signal). , 717 are bit 1 of the internal bus 32 (hereinafter, O_A1 signal).

The connection of the address output circuit 600 will be described. The NOR circuit 601 receives the halfword access signal 9
2 and the word access signal 93 are NORed, and the result is output to one input of an AND circuit 602. The AND circuit 602 outputs the O_A0 signal 716 and NO
The logical product of the output of the R circuit 601 is obtained, and the result is output as bit 0 of the external address bus 70. Inverter 603 outputs the negation of word access signal 93 to one input of AND circuit 604. AND circuit 60
4 takes the logical product of the output of the inverter 603 and the O_A1 signal 717, and outputs the result to one input of the OR circuit 605. OR circuit 605 is AND circuit 604
Of the external address bus 70, that is, A
Output as one signal 44.

Next, the function of the address output circuit 600 will be described.

First, when the halfword access signal 92 is "1", the address output circuit 600 outputs the result of masking bit 0 of the internal bus 32 to "0" to the external address bus 70.

When the word access signal 93 is "1", the address output circuit 600 outputs the result of masking bit 0 and bit 1 of the 32-bit address to "0" to the external address bus 70.

When both the halfword access signal 92 and the word access signal 93 are "0", the address output circuit 600 outputs the 32-bit address generated by the CPU 10 to the external address bus 70 as it is. . When the second cycle signal 94 is "1", the bit 1 of the external address bus 70 is "1" regardless of the state of the O_A1 signal 716.

Next, the operation of storing the contents of the A / D conversion result register in the general-purpose register group will be described with reference to FIGS.

The result of the A / D conversion by the A / D converter 89 is controlled by the control in the A / D converter circuit section 80.
It is stored in the D conversion result register 81. The addresses of the 16-bit A / D conversion result registers 81 to 84 are F
Word boundaries from FFFF390H to FFFFF39CH, that is, FFFFF390H, FFFFF394
H, FFFFF398H and FFFFF39CH. However, when an address that is not assigned to the A / D conversion result register is read, indefinite data is read.

First, the case where the CPU 10 reads the A / D conversion result register 81 by half word access will be described. Since the access is a halfword access, the halfword access signal 92 becomes "1". At this time, the word access signal 93 is "0". The address output circuit 600 connects the external address bus 70 to the FFFFF390
H is output.

The RD signal 43 becomes "1" and the A1 signal 44 becomes "0", and the data on the external data bus 60 is stored in the lower 16 bits of the read buffer 41. From the read buffer 41 via the internal data bus 32,
The lower 16 bits of the read buffer 41 are output to the CPU 10. In the CPU 10, the 15th bit of the internal data bus 32 is sign-extended to the upper 16 bits and stored in a general-purpose register.

Next, the CPU 10 executes A by word access.
The case where the / D conversion register 81 is read will be described.

Since the external data bus 60 has a width of 16 bits, the bus bus is used to read out 32-bit data.
The cycle is started twice. In the first bus cycle, 16-bit data is read from FFFFF390H, and in the second bus cycle, 16-bit data is read from FFFFF392H. At this time, the second cycle signal 94 becomes "0" in the first bus cycle and "1" in the second bus cycle. Therefore, in the first bus cycle, A1
The signal 44 outputs "0" and the A1 signal 44 outputs "1" in the second bus cycle.

Since word access is used, the word access signal 93 is "1" and the half word access signal 93 is "1".
The access signal 92 is “0”.

In the first bus cycle, the A1 signal becomes "0", the RD signal 43 becomes "1", and the external data
The read buffer 41 stores 16-bit data from the FFFFF 390H from the bus 60 in the lower 16 bits. In the second bus cycle, the second cycle signal 94
Becomes "1", so that the A1 signal 44 becomes "1". Subsequently, the RD signal 43 becomes “1” and the FFFFF 39
Undefined data of 16 bits from 2H is stored in the upper 16 bits of the read buffer 41. Read buffer 4
The CPU 10 inputs the contents of the read buffer 41 from 1 through the internal data bus 32. CPU 10
Data whose upper 16 bits are undefined are stored in a general-purpose register.

As described above, 1 is stored in the 32-bit general-purpose register.
When storing 6-bit data, unnecessary indefinite data is stored in the upper 16 bits. Therefore, processing for masking the upper 16 bits by software is required.

The processing for reading data from the peripheral I / O and masking includes the following processing.

Instruction (1): 16 bits from peripheral I / O
The data is read and stored in the general-purpose register A.

Instruction (2): The result of taking the logical product of 0000FFFFH and the contents of general-purpose register A is applied to general-purpose register A
Perform the process of storing in.

As described above, every time 16-bit data is read from the peripheral I / O, the processing performed by the instruction (2) is required.

A second conventional example is disclosed in Japanese Patent Laid-Open No. 2-116938.
As disclosed in Japanese Unexamined Patent Application Publication No. H10-171, "variable word length memory device", a function for converting 8-bit data into 32-bit data is provided. A memory for holding data to be processed, an address conversion circuit for changing the address assignment of the microprocessor to the memory to freely change the data width of the memory as viewed from the microprocessor, and a bit width by the address conversion circuit A code extension circuit for selectively performing code length processing of data in response to the change processing is provided.

FIG. 10 shows the configuration of the second conventional example. In the figure, an 8-bit bidirectional buffer 606 for inputting / outputting data between a memory and a microprocessor, and when a sign extension signal from a control circuit (not shown) is "0", the ground voltage is taken in. 0 ". When the sign extension signal from the control circuit is" 1 ", the most significant bit of the data read from the memory, that is, the sign bit, is taken in, and the data selector 6 which outputs it.
07 and a unidirectional buffer 608 for supplying "0" or "1" output from the data selector 607 to the microprocessor as upper 24 bits of data.

When 8-bit data is read from the memory when the sign extension signal is "0", the 8-bit data is fetched by the bidirectional buffer 608 and sent to the microprocessor as the lower 8 bits of 32-bit data. Supply. Further, based on “0” output from the data selector, the unidirectional buffer 608 outputs “0” to the microprocessor as the upper 24 bits of the 32-bit data.

When 8-bit data is read from the memory when the sign extension signal is "1", the 8-bit data is fetched by the bidirectional buffer 608 and is sent to the microprocessor as lower 8 bits of 32-bit data. Supply. Also, based on the most significant bit output from the data selector, the unidirectional buffer 608 outputs
The sign bit is extended to 32 bits as the upper 24 bits of the 2-bit data and output to the microprocessor.

[0043]

In the first conventional example, the instruction code for masking the upper 16 bits of the general-purpose register and the processing time are overhead.

The reason is that 16-bit peripheral I / O is set to 1
Regardless of whether data is read out of 6 bits or 32 bits, the upper 16 bits are stored in a 32-bit general-purpose register as data containing extra data.

In the second conventional example, the data in the memory is sign-extended by the sign extension circuit or "0" is output to the data portion to be added. Eliminate software overhead for conversion.

However, in a microprocessor in which the bit width of the external data bus 60 is 16 bits and the bit width of the general-purpose register is 32 bits, the external data bus 60 is used. Thus, 32-bit data is read in two bus cycles. In such a case, the configuration of the second conventional example converts only 8-bit data externally into 32-bit data, so that only the data width is converted by adding upper bits. Therefore, it is not possible to cope with reading 32-bit data.

An object of the present invention is to solve the above problems,
By outputting “0” to the upper 16 bits of the read buffer, 16-bit data from a specific address is read out of the word buffer.
When read by access, 16 is not sign-extended
A bus interface unit capable of storing bit data in a general-purpose register.

[0048]

In order to solve the above-mentioned problems, a bus interface unit of the present invention comprises:
A data bus is connected to a first data bus having a first bit width and a second data bus having a second bit width smaller than the first data bus and having a second bit width. A read circuit for reading, a detection circuit for detecting an address of the data to be read, a transfer circuit for storing the read data in a buffer and transferring the read data to the first data bus; When detecting that the address is a predetermined address, the reading means stores the data read in the first cycle in a corresponding lower bit of the buffer,
In a second cycle, a predetermined value is stored in a corresponding upper bit of the buffer.

With such a configuration, data processing can be performed on the data on the second data bus in advance, so that the data read on the first data bus is stored in a general-purpose register, and then the data is processed by software. There is no need to perform processing, and it is possible to prevent an increase in processing time and instruction codes.

[0050]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As described above, in the first conventional example,
Regardless of the address of the read data, the A1 signal 44
Is "1", the value of the external data bus 60 is stored in the upper 16 bits of the read buffer 41.
However, in the present embodiment, 1
When 6-bit data is read by word access, “0” is stored in the upper 16 bits of the read buffer 41 when the value of the A1 signal 44 is “1”.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a microprocessor system according to one embodiment of the present invention.

In FIG. 1, 99 is a microprocessor, 10 is a CPU, 20 is a 32-bit general-purpose register group, 30 is a BIU, 89 is a 16-bit A / D converter, 80 is an A / D converter circuit, and 81 to 84. Is a 16-bit A / D conversion result register, 32 is a 32-bit internal bus, 60 is a 16-bit external data bus,
70 is a 32-bit external address bus. CPU
Reference numeral 10 is connected to the BIU 30 via an internal bus 32.

BIU 30 is connected to data input unit 4 shown in FIG.
0 is provided instead of the data input unit 540 of FIG.
The data input unit 40 will now be described.

In FIG. 2, reference numeral 42 denotes an input control unit;
A 2-bit read buffer, 44 is an A1 signal which is bit 1 of the external address bus, 43 is an RD signal, 45,
47 is a 2-input AND circuit, 46 is an inverter, 49
Is an address decoder, 48 is a zero extension designation number, 100 is an upper bit setting circuit, 92 is a halfword access signal, 93 is a word access signal, 94 is a second cycle signal, 321 is a 32-bit internal address bus, 32
2 is a 32-bit internal data bus.

The input control circuit 42 reads data on the external data bus 60 when its input is "1".
Output to the buffer 41. When the input is “0”, the input control circuit 41 outputs high impedance.

The A1 signal 44 is output to the read buffer 41 and the AND circuit 47. When the A1 signal 44 is "0", the output of the input control circuit 42 is read.
The data is stored in the lower 16 bits of the buffer 41. Conversely, A
When the 1 signal 44 is “1”, the output of the input control circuit 42 is stored in the upper 16 bits of the read buffer 41.

When the address decoder 49 inputs an address to be read with zero extension among 16-bit data set at a word boundary, the zero extension designation signal 48
Is "1".

The AND circuit 45 takes the logical product of the RD signal 43 and the output of the inverter 46, and outputs the result to the input of the input control circuit 42.

The AND circuit 47 takes the logical product of the A1 signal 44 and the zero extension designation signal 48, and outputs the result to the upper bit setting circuit 100 and the inverter 46.

The inverter 46 inverts the logic of the output of the AND circuit 47 and outputs the result to one input of the AND circuit 45.

The input of the upper bit setting circuit 100 is "1".
, 0000H is output to the read buffer 41. When the input is “0”, the output of the upper bit setting circuit 100 is high impedance.

The data input section 40 has an address output circuit 60
0, but the same as the address output circuit 600 of FIG. The address output circuit 600 will be described.

In FIG. 9, 602 and 604 are 2-input AND circuits, 601 is a 2-input NOR circuit, 603 is an inverter, 605 is a 2-input OR circuit, and 716 is bit 0 of the internal bus 32 (hereinafter, O_A0 signal). , 717 are bit 1 of the internal bus 32 (hereinafter, O_A1 signal).

The connection of the address output circuit 600 will be described. The NOR circuit 601 receives the halfword access signal 9
2 and the word access signal 93 are NORed, and the result is output to one input of an AND circuit 602. The AND circuit 602 outputs the O_A0 signal 716 and NO
The logical product of the output of the R circuit 601 is obtained, and the result is output as bit 0 of the external address bus 70. Inverter 603 outputs the negation of word access signal 93 to one input of AND circuit 604. AND circuit 60
4 takes the logical product of the output of the inverter 603 and the O_A1 signal 717, and outputs the result to one input of the OR circuit 605. OR circuit 605 is AND circuit 604
Of the external address bus 70, that is, A
Output as one signal 44.

Next, the function of the address output circuit 600 will be described.

When the halfword access signal 92 is "1"
, The address output circuit 600 outputs the result of masking bit 0 of the internal address bus 321 to “0” to the external address bus 70.

When the word access signal 93 is "1", the address output circuit 600 outputs the result obtained by masking bit 0 and bit 1 of the 32-bit address to "0" to the external address bus 70.

When both the half word access signal 92 and the word access signal 93 are "0", the address output circuit 600 outputs the 32-bit address generated by the CPU 10 to the external address bus 70 as it is. .

When the second cycle signal 94 is "1", the bit 1 of the external address bus 70 becomes "1" regardless of the state of the O_A1 signal 716.

Referring to FIG. 2, a description will be given of reading the A / D conversion result register 81. It is assumed that the FFFFF390H is output to the external address bus 70 under the control of the BIU 30 and the data of the A / D conversion register 81 is output to the external data bus 60.

First, a case where the A / D conversion result register is read by halfword access will be described.

In the read cycle, the half word access signal 92 becomes "1". Further, the address decoder 49 becomes valid and the zero extension designation signal 48 becomes "1", A1
The signal 44 becomes "0", and the output of the AND circuit 47 becomes "0". Therefore, the upper bit setting circuit 100 is invalid. At this time, the output of the AND circuit 47 is inverted to “1”. Further, since the RD signal 43 becomes “1”, the output of the AND circuit 45 becomes “1”. Therefore, the data on the external data bus 60 is stored in the lower 16 bits of the read buffer 41. The lower 16 bits of the read buffer 41 are output from the read buffer 41 to the CPU 10 via the internal data bus. CP
In U10, the 15th bit of the internal data bus 322 is sign-extended to the upper 16 bits and stored in the designated general-purpose register of the general-purpose register group 20.

Next, the case where the A / D conversion result register is read by word access will be described with reference to FIGS.

Since the external data bus 60 has a width of 16 bits, the bus bus is used to read out 32-bit data.
The cycle is started twice. As in the first conventional example, the A1 signal 542 is "0" in the first bus cycle, and the A1 signal 44 is "1" in the second bus cycle.

In FIG. 3, the first bus cycle is a period of T1 and T2. The second bus cycle is a T1S and T2S period. Although not shown in FIG. 2, each function is performed by a clock signal (CLK in FIG. 3).
).

During the period T1, the address output circuit 600 outputs FFFFF390H to the external address bus 70. At the same time, the address decoder 49 becomes valid, the zero extension designation signal 48 becomes "1", the A1 signal 44 becomes "0", and the output of the AND circuit 47 becomes "0". Therefore, the upper bit setting circuit 100 is invalid, and the output of the input control circuit 42 is stored in the read buffer 41.
At this time, the output of the inverter 46 becomes "1". Further, since the RD signal 43 becomes “1” in the T2 period,
The output of the D circuit 45 becomes "1". Therefore, the data on the external data bus 60 is stored in the lower 16 bits of the read buffer 41.

The address decoder 4 continues during the T1S period.
9 becomes valid, and the zero extension designation signal 48 becomes "1". In the T1S and T2S periods, the second cycle signal 94 becomes "1" and the A1 signal 44 becomes "1". Therefore, the output of the AND circuit 47 becomes “1”. For this reason,
The upper bit setting circuit 100 is valid, and 0000H is output to the read buffer 41. On the other hand, the output of the inverter 46 becomes "0". Therefore, in the T2S period, R
Even if the D signal 43 becomes "1", the output of the AND circuit 45 becomes "0" and the output of the input control circuit 42 becomes high impedance. Therefore, 0000H is stored in the upper 16 bits of the read buffer 41.

Subsequently, the contents of the read buffer 41 are output from the read buffer 41 to the CPU 10 via the internal data bus 32. The CPU 10 stores the data whose upper 16 bits are “0” in the designated general-purpose register of the general-purpose register group 20.

The case where an address that is not zero-extended is input to the address decoder 49 of FIG. 2 will also be described.
This is the case where the zero extension designation signal 48 is “0”.

The case of reading by halfword access is the same as in the first embodiment. The case where the A / D conversion result register is read by word access will be described with reference to FIGS.

During the period T1, the address output circuit 600 outputs an address to the external address bus 70 which does not designate zero extension. At the same time, the address decoder 49 becomes invalid, the zero extension designation signal 48 becomes "0", the A1 signal 44 becomes "0", and the output of the AND circuit 47 becomes "0". Therefore, the upper bit setting circuit 100 is invalid. At this time, the output of the inverter 46 becomes "1".
Further, since the RD signal 43 becomes “1” in the T2 period, A
The output of the ND circuit 45 becomes "1". Therefore, the data on the external data bus 60 is stored in the lower 16 bits of the read buffer 41.

The address decoder 4 continues during the T1S period.
9 becomes invalid, and the zero extension designation signal 48 becomes “0”. In the T1S and T2S periods, the second cycle signal 94 becomes "1" and the A1 signal 44 becomes "1". Therefore, the output of the AND circuit 47 becomes “0”. The upper bit setting circuit 100 is invalid. On the other hand, the output of the inverter 46 becomes "1". Therefore, when the RD signal 43 becomes “1” during the T2S period, the output of the AND circuit 45 becomes “1”.
Becomes Therefore, input control circuit 42 outputs the contents of external data bus 60.

Subsequently, the contents of the read buffer 41 are output from the read buffer 41 to the CPU 10 via the internal data bus 32. The CPU 10 stores the 32-bit data output to the external data bus twice in a designated general-purpose register in the general-purpose register group 20.

In the first embodiment, the A / D conversion register 81
Addresses ~ 84 were located on word boundaries.
However, there are cases where it is desired to arrange the address of the A / D conversion register on a halfword boundary. The second embodiment addresses such a case.

In the first embodiment, a designated 32-bit
A BIU that outputs an address obtained by masking bit 1 and bit 0 of the address to 0 to the external address bus 70. Therefore, word access can use only addresses on word boundaries.

In the second embodiment, an address obtained by masking only bit 0 of a designated 32-bit address can be output to an external address bus so that data on a halfword boundary can be accessed by word access. In the first cycle at the time of access, the data of the external data bus 60 is stored in the lower 16 bits of the read buffer.

Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

This embodiment has a configuration in which the data input unit 40 of the first embodiment in FIG. Therefore, only the data input unit 140 will be described, and the description of the first embodiment and the same configuration as the first embodiment will be omitted.

FIG. 4 shows a data input unit 140 according to the second embodiment.
Is shown. In FIG. 4, 41 is a 32-bit read buffer, 42 is an input control circuit, 48 is a zero extension designation signal,
49 is an address decoder, and 100 is an upper bit setting circuit, which is the same as in the first embodiment.

146 and 151 are inverters, 14
5, 147 and 152 are 2-input AND circuits, 153 is 2
An input OR circuit 700 is an address output circuit.

The connection in the data input section 140 will be described.

The inverter 151 inverts the zero extension designating signal 48 and outputs the inverted signal to one input of the AND circuit 152. The AND circuit 152 is connected to the A1 signal 144 and the inverter 1
The logical product of the outputs of the outputs of the OR circuit 51 is obtained.
3 to one input. The OR circuit 153 calculates the logical sum of the output of the AND circuit 152 and the output of the AND circuit 147, and outputs the result to the read buffer 41.

AND circuit 147 calculates the logical product of zero extension designating signal 48 and second cycle signal 94, and outputs the result to the inputs of inverter 146, upper bit setting circuit 100, and OR circuit 153, respectively. Inverter 146
Outputs the inverted output of the AND circuit 147 to one input of the AND circuit 145. The AND circuit 145 calculates the logical product of the output of the inverter 146 and the RD signal 43, and outputs the result to the input control circuit 42.

FIG. 5 shows the configuration of the address output circuit 700 of FIG.

In FIG. 5, 602 and 723 are two-input A's.
ND circuit, 601 is a NOR circuit, 721 is an inverter,
722 is a NAND circuit, and 724 is an OR circuit. The connection in the address output circuit 700 will be described.

The NOR circuit 601 performs a NOR operation on the half word access signal 92 and the word access signal 93, and outputs the result to one input of the AND circuit 602. The AND circuit 602 outputs the O_A0 signal 716
And the output of the NOR circuit 601 and outputs the result as bit 0 of the external address bus 70.

Inverter 721 outputs negation of zero extension designation signal 48 to one input of NAND circuit 722. NAND circuit 722 performs a NAND operation on the output of inverter 721 and word access signal 93, and outputs the result to one input of AND circuit 723.
The AND circuit 723 outputs the output of the NAND circuit 722 and O_A
1 signal 717 and the result is ORed with an OR circuit 7
24 to one output. OR circuit 724 is A
The output of the ND circuit 723 is ORed with the second cycle signal 94, and the result is output as the bit 1 of the external address bus 70, that is, the A1 signal 144.

Next, the function of the address output circuit 700 will be described.

When the half word access signal 92 is "1"
, The address output circuit 710 outputs the result of masking bit 0 of the internal bus to “0” to the external address bus 70. The relationship between word access signal 93 and bit 1 of external address bus 70 is as follows:
According to 8, it is determined as follows. Bit 1 of external address bus 70 when zero extension signal 48 is "0"
Is as follows.

When word access signal 93 is "0", address output circuit 700 outputs the result of masking bit 0 and bit 1 of internal address bus 321 to "0" to external address bus 70. I do.

When word access signal 93 is "1", address output circuit 700 outputs the result of masking bit 0 and bit 1 of internal address bus 321 to "0", respectively, to external address bus 70. I do. Also,
When the second cycle signal 94 is "1", the bit 1 of the external address bus 70 becomes "1" regardless of the state of the O_A1 signal 717.

When the zero extension designation signal 48 is "1", bit 1 of the external address bus 70 is as follows.

When the second cycle signal 94 is "0", O
_A1 signal 717 is at the same level as external address bus 7
Output to bit 1 of 0. When the second cycle signal 94 is "1", "1" is bit 1 of the external address bus.
Is output to

The case of reading the A / D conversion result register will be described with reference to FIGS. At this time, read A / D
The address of the conversion register is FFFFF392H, which is on a halfword boundary.

First, the readout of the A / D conversion register by halfword access is the same as that in the first embodiment, and a description thereof will be omitted.

The case where the A / D conversion register is read by word access will be described.

The bus cycle is 2 as in the first embodiment.
Will be invoked twice.

In FIG. 6, the first bus cycle is a period of T1 and T2. The second bus cycle is a T1S and T2S period. Although not shown in FIG. 4, each function is performed by a clock signal (CLK in FIG. 6).
).

During the period T1, the address output circuit 700 outputs FFFFF392H to the external address bus 70. At the same time, the address decoder 49 becomes valid and the zero extension designation signal 48 becomes "1". Since the output of the inverter 151 is "0", the output of the AND circuit 152 is also "0". At this time, the A1 signal 144 becomes "1" at the same level as the O_A1 signal 717. Since the second cycle signal is "0" during the periods T1 and T2, the output of the AND circuit 147 becomes "0". Therefore, the upper bit setting circuit 100 is invalid during the periods T1 and T2. T1,
Since the output of the inverter 146 becomes “1” during the T2 period, when the RD signal 43 becomes “1” during the T2 period, AND
The output of the circuit 145 becomes "1". Therefore, the data on the external data bus 60 is stored in the lower 16 bits of the read buffer 41.

The address decoder 4 continues during the T1S period.
9 becomes valid, and the zero extension designation signal 48 becomes "1". In the T1S and T2S periods, the second cycle signal 94 becomes “1” and the A1 signal 144 becomes “1”. At this time, the output of the AND circuit 147 becomes “1”, and the output of the OR circuit 153 also becomes “1”. Since the upper bit setting circuit 100 is valid, 0000H is output to the read buffer 41. On the other hand, during the periods T1S and T2S, the output of the inverter 146 is "0", and the input control circuit 42 outputs high impedance. At this time, the output of the inverter 146 becomes "0". Therefore, even if the RD signal 43 becomes “1” during the T2S period, A
The output of the ND circuit 145 becomes “0”. Therefore, input control circuit 42 does not output the contents of external data bus 60. Instead, 0000H is read buffer 41
Is stored in the upper 16 bits.

A case where an address which is not zero-extended is input to the address decoder 49 of FIG. 4 will be described. This is the case where the zero extension designation number 48 is “0”.

The readout by half word access is the same as in the first embodiment.

During the period T1, an address which does not designate zero extension is output from the address output circuit 600 to the external address bus 70. At the same time, the address decoder 49 becomes invalid, the zero extension designation signal 48 becomes "0", and the inverter 151 becomes "1". The A1 signal 44 becomes “0”, and the output of the AND circuit 147 becomes “0”. The output of the inverter 151 is 1, but the A1 signal 144 is "0".
Therefore, the output of the AND circuit 152 becomes “0”.
Therefore, the output of the OR circuit 153 is “0”. Further, since the output of the AND circuit 147 is “0”, the upper bit setting circuit 100 is invalid. Inverter 146
Is “1”, the RD signal 43 becomes “1” during the T2 period.
, The output of the AND circuit 145 becomes “1”. Therefore, the data on the external data bus 60 is stored in the lower 16 bits of the read buffer 41.

The address decoder 4 continues during the T1S period.
9 becomes invalid, and the zero extension designation signal 48 becomes “0”. In the T1S and T2S periods, the second cycle signal 94 becomes "1" and the A1 signal 44 becomes "1". Therefore, the AND circuit 152 becomes “1”, and the OR circuit 15
The output of No. 3 is "1". Also, since the output of the AND circuit 147 is “0”, the upper bit setting circuit 100 is invalid. On the other hand, the output of inverter 146 becomes "1", and input control circuit 42 outputs the contents of external data bus 60. Therefore, when the RD signal 43 becomes “1” during the T2S period, the output of the AND circuit 45 becomes “1”. Therefore, input control circuit 42 outputs the contents of external data bus 60.

Subsequently, the contents of the read buffer 41 are output from the read buffer 41 to the CPU 10 via the internal data bus 32. The CPU 10 stores the 32-bit data output to the external data bus twice in a designated general-purpose register in the general-purpose register group 20.

[0116]

The effects of the first embodiment of the present invention will be described. In the first embodiment of the present invention, when an address having data to be zero-extended is on a word boundary,
When data is read by word access, whether to store the contents of the external data bus in the read buffer is determined according to the state of the bit 1 of the external address. This eliminates the need for conventional software processing after storing data in general-purpose registers.
Processing time and instruction codes of a microprocessor or the like can be reduced.

The effect of the second embodiment of the present invention will be described. According to the second embodiment of the present invention, if an address having data to be zero-extended is on a halfword boundary, if data is read by word access, the read buffer is read according to the state of bit 1 of the external address. Whether to store the contents of the external data bus is determined. For this reason, peripheral I / Os can be efficiently arranged in addresses. Further, similarly to the first embodiment, after storing the data in the general-purpose register, the software processing conventionally performed becomes unnecessary, and the processing time of the microprocessor or the like and the instruction code can be reduced.

Although the present invention has been described with reference to the preferred embodiments, the present invention is not necessarily limited to the above embodiments. For example, a configuration in which zero extension is performed only in the case of halfword access has been described. However, a configuration in which zero extension is performed in the case of byte access is also possible.

According to the present invention, a microprocessor having only a sign extension instruction stores data at a specific address in a general-purpose register having a bit width larger than that of an external data bus by using an address decoder and an upper bit setting circuit. At this time, zero-extended data can be obtained.

Further, since the software used in the related art is not used to obtain the zero-extended data, the instruction code and the processing time can be reduced. Therefore, the present invention can be applied to an information processing apparatus such as a microprocessor that emphasizes suppression of increase in instruction codes.

[Brief description of the drawings]

FIG. 1 is a diagram showing a system configuration of a microprocessor according to one embodiment of the present invention.

FIG. 2 is a diagram showing details of a data input unit in the first embodiment shown in FIG. 1;

FIG. 3 is a timing chart of a data input unit in the first embodiment.

FIG. 4 is a diagram showing details of a data input unit in the second embodiment shown in FIG. 1;

FIG. 5 is a diagram showing details of an address output circuit in the second embodiment shown in FIG. 4;

FIG. 6 is a timing chart of a data input unit in the second embodiment shown in FIG.

FIG. 7 is a diagram showing a system configuration of a microprocessor according to a first conventional example.

FIG. 8 is a diagram showing details of a data input unit in the first conventional example shown in FIG. 7;

FIG. 9 is a diagram showing details of an address output circuit in FIGS. 8 and 2;

FIG. 10 is a diagram showing a configuration of a second conventional example.

[Explanation of symbols]

 10 CPU 20 General-purpose register 30 Bus interface unit 41 Read buffer 42 Input control circuit 49 Address decoder 60 External data bus 70 External address bus 100 Upper bit setting circuit 321 Internal address bus 322 Internal data bus 600 Address output circuit

Claims (3)

[Claims] 1. A first data bus having a first bit width and a second data bus having a second bit width smaller than the first bit width are connected to the first data bus. A bus for transmitting the data of the second data bus;
An interface unit, connected to the second data bus, for outputting data on the second data bus in response to a first control signal; and zero-extending in response to a second control signal. A setting circuit for outputting data for the input control circuit, the setting circuit, and the data from the input control circuit and the setting circuit in response to a third control signal connected to the first data bus. A bus interface unit comprising a buffer for receiving the data and outputting the data to the first data bus. 2. The method according to claim 1, wherein the first control signal and the third control signal are activated when the data of the second data bus is taken as data having a second bit width. Is deactivated, the data of the second data bus is taken into the lower second bit width portion of the read buffer and output to the first data bus, In the case of incorporating the data of the second data bus as data having a first bit width, the first control signal is activated, the third control signal is activated, and the second control signal is deactivated. The data of the second data bus is fetched into the lower second bit width portion of the read buffer, and then the first control signal is activated to activate a third control signal, and Two By activating a control signal, the data for the zero extension from the setting circuit is output to the upper part of the read buffer except the lower part of the second bit width part, and the data is output to the first data bus. 2. The bus interface unit according to claim 1, wherein the bus interface unit outputs the data having the first bit width zero-extended. 3. A first data bus having a first bit width and a second data bus having a smaller bit width than the first data bus.
A read circuit connected to a second data bus having a bit width of, and reading data from the second data bus; a detection circuit for detecting an address of the read data; and storing the read data in a buffer. A transfer circuit that transfers the read data to the first data bus, and when the detection means detects that the address of the data to be read is a predetermined address, the read means reads the data read in a first cycle. A bus interface unit storing in a corresponding lower bit of a buffer and storing a predetermined value in a corresponding upper bit of the buffer in a second cycle.