JPH118537A - Waveform-shaping circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically maintain a duty ratio at 50% and to reduce the influence from noises. SOLUTION: The maximum output value of a reception circuit IC1, with which a sine wave voltage is defined as a negative input, and the voltage value of a prescribed negative voltage power source VR are divided by a voltage- dividing circuit and this voltage divided output is fed back to the positive input of the IC1, so that a comaprator circuit can be constituted. The voltage-dividing circuit is composed of a resistor R2 connected between the output of the circuit IC1 and a voltage-dividing point and a resistor R3 connected between the voltage dividing point and the prescribed negative voltage power source VR, so that the resistance value of the resistor R3 corresponding to the resistance value of the resistor R2 can become double the voltage value of the prescribed negative voltage power source, corresponding to the maximum output value of the circuit IC1. Since the sine wave voltage is compared with the positive and negative threshold values of the equal absolute value and a binary waveform is outputted, even if some noise voltage is superimposed on the input sine wave, no chattering occurs in the sine wave output so that troubles do not occur, even when this circuit is used for a digital processing circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform shaping circuit, and more particularly, to a waveform shaping circuit which receives a sine wave and outputs a waveform having a duty ratio of 1/2.

[0002]

2. Description of the Related Art A terminal device used for satellite communication has various functions. The main functions of this device include an elastic buffer function for absorbing clock jitter, a multiplexing / demultiplexing function for multiplexing / demultiplexing a meeting line signal, a scrambler function for scrambling digital data, and a bit error in a line. And a modulation / demodulation function for performing four-phase modulation.

In an elastic buffer section or a demultiplexing section of a terminal device, a waveform shaping circuit is used as an oscillation circuit for generating a read clock. In this terminal device, since the data transmission rate can be changed in a wide range, the oscillation circuit must be able to output a clock with a wide range of frequencies. Therefore, a direct digital synthesizer (DD) is included in the oscillation circuit.
S) is used. Since the output signal of the DDS is output as a sine wave, it is necessary to convert the sine wave into a rectangular wave using a waveform shaping circuit.

Here, a conventional waveform shaping circuit is shown in FIG. The conventional waveform shaping circuit shown in FIG.
The circuit includes a well-known non-inverting addition circuit including a balanced signal receiving circuit IC1 using an operational amplifier, a variable resistor R4, and a resistor R1. The feedback section of the non-inverting addition circuit is provided with an amplitude limiting circuit 1 receiving the output signal S4 of the receiving circuit IC1 and an integrating circuit 2 receiving the output signal S5. The input clock S1 from the sine wave oscillation circuit OSC is applied to the inverting input terminal of the receiving circuit IC1 via the capacitor C1.

In such a configuration, the sine wave oscillation circuit OS
Only the DC component of the input clock S1 from C is removed by the capacitor C1 having a sufficiently low impedance with respect to the frequency of the clock S1, and a new DC bias is applied via the resistor R4 to thereby invert the input signal of the balanced signal receiving circuit IC1. It becomes signal S2. The output signal S4 of the receiving circuit IC1 becomes the input signal of the amplitude limiting circuit 1, and the amplitude limiting circuit 1 absorbs the fluctuation of the power supply voltage and the fluctuation of the amplitude of the voltage VS4 due to the frequency of the input signal and the like, and becomes the output signal S5. . The output signal S5 having a constant amplitude is input to the integration circuit 2.
As a result, the integrated output signal S6 becomes an output voltage proportional to the duty ratio of the signal S5.

The output signal S6 is divided by resistors R4 and R1 to provide a bias voltage to the input signal S2. The duty ratio is maintained at 50% by adjusting the variable resistor R4 and appropriately selecting the voltage division ratio.

Here, the amplitude limiting circuit 1 operates as shown in FIG. That is, the peak value of the voltage VS4 of the output signal S4 of the receiving circuit IC1 is V0 as shown in FIG. 7A, but the peak value becomes V0 'due to fluctuations in the power supply voltage and the like. This is shown in FIG.
When the output signal S4 of the peak value V0 'is input to the amplitude limiting circuit 1, the amplitude is limited, and the voltage VS5 of the output signal S5 of the amplitude limiting circuit 1 becomes V as shown in FIG.
L.

Japanese Patent Application Laid-Open Nos. 2-141018 and 3-85915 disclose a method of automatically maintaining a duty ratio of 50% when converting a sine wave input signal into a rectangular wave. Has been stated. In both publications, the output duty ratio is automatically set to 5
In order to maintain 0%, a limiter circuit or a clamp circuit for converting an output signal into a rectangular wave, an integrating circuit for integrating the rectangular wave output signal, and a feedback circuit for feeding back the integrated output to the input side are provided. I have.

In the prior art described in these publications, it was necessary to adjust the threshold voltage of a circuit for converting a sine wave into a rectangular wave with a variable resistor in order to make the duty ratio of the output signal 50%. Therefore, the duty ratio of the output signal has changed due to a change in the resistance value due to a temperature change or the like, or a change in the amplitude of the input sine wave.

For this reason, in these publications, the amplitude of an input signal is limited by a limiter circuit or a clamp circuit and converted into a rectangular wave having a constant amplitude to absorb a fluctuation in the amplitude. It is converted into a DC voltage proportional to the duty ratio by an integrating circuit. Then, this voltage is fed back to the bias circuit on the input side to maintain the duty ratio of the output signal at 50%.

[0011]

When the circuit configuration of FIG. 3 and the circuit configuration of the prior art described in the official gazette are applied to actual products, there are the following problems. That is, in an actual product, an analog circuit and a digital circuit are often mixed, and the noise of the digital circuit may be mixed into the sine wave output of the oscillator. When the noise voltage is superimposed on the sine wave input signal, the operation of the limiter circuit is as shown in FIG. For this reason, in a circuit for converting a sine wave input signal into a rectangular wave, if noise is superimposed near the threshold value of the sine wave input signal, as shown in FIG.
A chattering waveform is generated in the square wave output. Therefore, when this is used as a drive clock for the digital processing circuit, there is a drawback that processing is inconvenient.

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and has as its object to automatically maintain a duty ratio of 50% and to reduce the influence of noise. Is to provide a circuit.

[0013]

A waveform shaping circuit according to the present invention is a waveform shaping circuit for receiving a sine wave voltage as input and outputting a binary waveform corresponding to a result of comparison between the voltage value and a predetermined threshold value. The sine wave voltage is compared with positive and negative thresholds having the same absolute value. When the value of the sine wave voltage is larger than one of the positive and negative thresholds, the first voltage value is output, and when the value is smaller than the other, the second voltage is output. And a comparison circuit that outputs a voltage value of

The comparison circuit includes an operational amplifier having the sine wave voltage as a negative input, and a voltage dividing circuit for dividing a maximum output value of the operational amplifier and a predetermined negative voltage. The divided voltage output is fed back to the positive input of the operational amplifier.

The voltage dividing circuit is connected between a first resistor connected between the output of the operational amplifier and a voltage dividing point, and connected between the voltage dividing point and the predetermined negative voltage power supply. The second
Wherein the resistance value of the second resistor with respect to the resistance value of the first resistor is twice the voltage value of the predetermined negative voltage power supply with respect to the maximum output value.

In short, in this circuit, another feedback circuit is provided in addition to the feedback circuit originally provided in the non-inverting amplifier circuit.
Since the sine wave is converted into a rectangular wave with a hysteresis characteristic, a configuration resistant to noise can be realized.

[0017]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a waveform shaping circuit according to the present invention. 3, the same parts as those in FIG. 3 are denoted by the same reference numerals, and detailed description of those parts will be omitted. In FIG. 1, the waveform shaping circuit according to the present embodiment inputs an output signal S4 of a receiving circuit IC1 as an operational amplifier to a voltage dividing circuit including resistors R2 and R3, and outputs the divided output to a reference input of the receiving circuit IC1. In this configuration, feedback is made to the non-inverting input terminal, which is a terminal. That is, in the circuit of FIG. 3, since the non-inverting input terminal, which is the reference input terminal, is fixed at the ground level, the voltage value of the signal S3 is always zero. On the other hand, in the circuit of FIG. 1 according to the present embodiment, the voltage value of the non-inverting input terminal which is the reference input terminal is changed.

In FIG. 1, the voltage VS4 of the output signal S4 is applied to one end of one resistor R2 constituting a voltage dividing circuit, and -VR as a negative reference voltage source is applied to one end of the other resistor R3. Is applied. Then, the voltage value VS3 of the divided voltage output signal S3 from the voltage dividing points of the resistors R2 and R3 constituting the voltage dividing circuit is applied to a non-inverting input terminal which is a reference input terminal of the receiving circuit IC1.

In such a configuration, the sine wave oscillation circuit OS
Only the DC component of the input clock S1 from C is removed by the capacitor C1 having a sufficiently low impedance with respect to the frequency of the clock S1, and a new DC bias is applied via the resistor R4 to thereby invert the input signal of the balanced signal receiving circuit IC1. It becomes signal S2. The output signal S4 of the receiving circuit IC1 becomes the input signal of the amplitude limiting circuit 1, and the amplitude limiting circuit 1 absorbs the fluctuation of the power supply voltage and the fluctuation of the amplitude of the voltage VS4 due to the frequency of the input signal and the like, and becomes the output signal S5. . The output signal S5 having a constant amplitude is input to the integration circuit 2.
As a result, the integrated output signal S6 becomes an output voltage proportional to the duty ratio of the signal S5.

At this time, assuming that the voltage of S5 is VS5, the voltage VS6 of the signal S6 is expressed by the following equation.

[0022]

(Equation 1) Here, in the equation, T indicates the cycle of the voltage VS5.

Output signal S6 is divided by resistors R4 and R1 to provide a bias voltage to input signal S2. The duty ratio is maintained at 50% by appropriately selecting the partial pressure ratio.

On the other hand, the non-inverted input signal S3 is
This is a signal obtained by dividing the voltage between the output signal S4 of C1 and the negative reference voltage source -VR by the resistors R2 and R3. At this time, assuming that the voltage value of the output signal S4 of the receiving circuit IC1 is VS4, the voltage value VS3 of the signal S3 is represented by the following equation.

VS3 = {r3 / (r2 + r3)} VS4- {r2 / (r2 + r3)} Vr where r2 is the resistance value of the resistor R2, r3 is the resistance value of the resistor R3, and Vr is the voltage of the voltage source VR. Value. As a result, the voltage VS4 of the output signal S4 of the receiving circuit IC1 becomes the voltage VS2 of the inverted input signal and the voltage VS2 of the non-inverted input signal.
3 gives the following:

[0026] Here, V0 is the peak value of the output signal of the circuit IC1.

In general, the condition of VS2 = VS3 is not considered because it only exists excessively. The operation in each state of the expression is as follows. (1) When VS2> VS3 VS4 = 0 according to the equation, and VS3 ′ = − {r2 / (r2 + r3)} Vr. Therefore, in this state, VS2 is equal to V in the equation.
As long as the output voltage VS4 does not become smaller than S3 ', the output voltage VS4 becomes 0.
Does not change from V0 to V0. (2) When VS2 <VS3 From the formula, VS4 = V0, and from the formula, VS3 ″ = {r3 / (r2 + r3)} V0−r2 / (r2 + r3) Vr. VS3 ″ = {r2 / (r2 + r3)} Vr... Therefore, according to the formula and the formula, r3 / r2 = 2Vr / V0... Therefore, r2 and r3 are set so as to satisfy the expression.
In this state, as long as VS2 does not become larger than VS3 ″ in the equation, the output voltage VS4 becomes 0.
Does not change from V0 to V0.

These are shown in FIG. 2 as shown in FIG. That is, for a sine wave input as shown in FIG. 7A, the positive threshold value is VS3 ″ and the negative threshold value is VS3 ′, and a rectangular wave as shown in FIG. Square wave is 0
It is a rectangle that takes one of two values, [V] and V0 [V]. In other words, the above-mentioned operations (1) and (2) have a hysteresis characteristic with respect to the input signal, so that a malfunction does not easily occur even if the input signal has some noise.

In short, the present circuit is a waveform shaping circuit which receives a sine wave voltage as input and outputs a binary waveform corresponding to the result of comparison between the voltage value and a predetermined threshold value. This is compared with the positive and negative thresholds. Then, when the value of the sine wave voltage is larger than one of the positive and negative threshold values, the first voltage value is output, and when the value is smaller than the other, the second voltage value is output.

Further, the comparison circuit includes an operational amplifier having a sine wave voltage as a negative input, and a voltage dividing circuit for dividing a maximum output value of the operational amplifier and a predetermined negative voltage. In this configuration, the pressure output is fed back to the positive input of the operational amplifier.

Further, the voltage dividing circuit includes a first resistor connected between the output of the operational amplifier and the voltage dividing point, and a second resistor connected between the voltage dividing point and the predetermined negative voltage power supply. And the resistor. Then, as in the equation, the resistance value of the second resistor with respect to the resistance value of the first resistor is 2 times the voltage value of the predetermined negative voltage power supply with respect to the maximum output value.
It is doubled.

By adopting such a configuration, even if the input sine wave is overlaid with some noise voltage, no chattering occurs in the rectangular wave output, so that even if this is used in the digital processing circuit, a problem occurs. There is no.

Although the waveform shaping circuit used in the terminal device of the satellite communication has been described above, it is apparent that the present invention can be widely applied to a case where it is desired to maintain the pulse duty ratio at 50%.

The present invention can take the following aspects in connection with the description of the claims.

(1) The sine wave voltage is input to the operational amplifier via the DC blocking capacitor, further comprising a DC blocking capacitor for cutting a DC component of the sine wave voltage. 4. The waveform shaping circuit according to 2 or 3.

(2) The feedback circuit to the negative input of the operational amplifier further includes an amplitude limiting circuit for limiting the amplitude of the amplifier, and an integrating circuit for integrating the limited output. The waveform shaping circuit according to any one of claims 1 to 3.

[0037]

As described above, according to the present invention, another feedback circuit is provided in addition to the feedback circuit originally provided in the non-inverting amplifier circuit, and has a hysteresis characteristic when converting a sine wave into a rectangular wave. By doing so, a configuration resistant to noise can be realized, and there is an effect that no problem occurs even when used in a digital processing circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a waveform shaping circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing input and output waveforms of the waveform shaping circuit of FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of a conventional waveform shaping circuit.

FIG. 4 is a waveform chart showing an operation of the amplitude limiting circuit in FIG.

FIG. 5 is a diagram showing input and output waveforms of a conventional waveform shaping circuit.

[Description of Signs] 1 Amplitude limiting circuit 2 Integrating circuit IC1 Balanced signal receiving circuit R1 to R4 Resistor C1 Capacitor

Claims (3)

[Claims] 1. A waveform shaping circuit for receiving a sine wave voltage as input and outputting a binary waveform corresponding to a comparison result between the voltage value and a predetermined threshold value, wherein the sine wave voltage has a positive and negative threshold value having an equal absolute value. A comparison circuit that outputs a first voltage value when the value of the sine wave voltage is larger than one of the positive and negative threshold values and outputs a second voltage value when the value is smaller than the other. Characteristic waveform shaping circuit. The comparison circuit includes an operational amplifier having the sine wave voltage as a negative input, and a voltage divider for dividing a maximum output value of the operational amplifier and a predetermined negative voltage. 2. The waveform shaping circuit according to claim 1, wherein the divided output is fed back to a positive input of the operational amplifier. 3. The voltage dividing circuit is connected between a first resistor connected between an output of the operational amplifier and a voltage dividing point, and between the voltage dividing point and the predetermined negative voltage power supply. A second resistor having a resistance value of the second resistor with respect to a resistance value of the first resistor being twice a voltage value of a predetermined negative voltage power supply with respect to the maximum output value. Claim 2
Waveform shaping circuit as described.