JPH118533A - Voltage-controlled oscillation circuit - Google Patents

Voltage-controlled oscillation circuit

Info

Publication number
JPH118533A
JPH118533A JP9161678A JP16167897A JPH118533A JP H118533 A JPH118533 A JP H118533A JP 9161678 A JP9161678 A JP 9161678A JP 16167897 A JP16167897 A JP 16167897A JP H118533 A JPH118533 A JP H118533A
Authority
JP
Japan
Prior art keywords
phase
phase conversion
conversion circuits
variations
conversion circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP9161678A
Other languages
Japanese (ja)
Inventor
Hiroyuki Totsuka
弘之 戸塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP9161678A priority Critical patent/JPH118533A/en
Publication of JPH118533A publication Critical patent/JPH118533A/en
Withdrawn legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PROBLEM TO BE SOLVED: To suppress the generation of noise due to power source variations by providing 2-phase/1-phase conversion circuits which operate mutually so that power source variations generated by the 2-phase/1-phase conversion circuits cancel each other. SOLUTION: When V1 is applied to an input terminal Vin, a waveform of frequency f(X) is outputted as a differential output from a ring oscillator 101 and inputted to the 2-phase/1-phase conversion circuits 102 and 103. At output terminals OutA and OutB of the 2-phase/1-phase conversion circuits 102 and 103, mutually inverted signals appear, since signals applied to input terminals A and XA of the 2-phase/1-phase converting circuits 102 and 103 are exactly opposite to each other. In this case, variations ΔV generated due to the variations of a source voltage caused by the operation of the 2-phase/1- phase conversion circuits 102 and 103 are equal in quantity and opposite in direction since the 2-phase/1-phase conversion circuits 102 and 103 have symmetrical circuit constitution. Further, the timing also becomes the same. Therefore, the variations ΔV result in canceling each other.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、クロックジェネレ
ータとして用いるPLLの電圧制御発振回路に関するも
のである。
[0001] 1. Field of the Invention [0002] The present invention relates to a voltage controlled oscillation circuit of a PLL used as a clock generator.

【0002】[0002]

【従来の技術】従来のPLLでは、構成が簡単な単出力
型リングオシレータを用いて電圧制御発振回路を構成す
ることがある。また、十分な出力振幅を得るために差動
出力型リングオシレータを用いる場合があるが、消費電
流が大きくなる。更にPLLをクロックジェネレータと
して用いる場合には、いずれの方式も採ることが出来る
が、電圧制御発振回路の動作が出力波形に影響を及ぼさ
ないことが求められる。
2. Description of the Related Art In a conventional PLL, a voltage controlled oscillation circuit may be formed using a single-output type ring oscillator having a simple structure. Although a differential output type ring oscillator may be used to obtain a sufficient output amplitude, current consumption increases. Further, when a PLL is used as a clock generator, any method can be adopted, but it is required that the operation of the voltage controlled oscillation circuit does not affect the output waveform.

【0003】[0003]

【発明が解決しようとする課題】しかし実際は、十分な
出力振幅を得るために差動出力型リングオシレータを用
いる場合が多く、前記差動出力型リングオシレータと組
み合わせて使用する2相/1相変換回路の動作時に出力
負荷に流出入する電流のため、電源ライン上に過渡的な
電源変動が生じ、これがノイズとなってPLLの出力信
号に影響を与える。結果としてこれがPLLのクロック
出力信号にジッターを生じさせる原因となっている。
However, in practice, a differential output type ring oscillator is often used to obtain a sufficient output amplitude, and a two-phase / one-phase converter used in combination with the differential output type ring oscillator is often used. Due to the current flowing into and out of the output load during the operation of the circuit, a transient power supply fluctuation occurs on the power supply line, which becomes noise and affects the output signal of the PLL. As a result, this causes jitter in the clock output signal of the PLL.

【0004】[0004]

【課題を解決するための手段】そこで本発明は、前述の
課題を解決するために2相/1相変換回路で生じる電源
変動を、その変化分を打ち消すように互いに動作する複
数の2相/1相変換回路を設ける構成とすることで解決
する。
SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention solves the above-mentioned problem by using a plurality of two-phase / one-phase converters operating mutually to cancel a power supply fluctuation generated in a two-phase / one-phase conversion circuit. The problem is solved by providing a one-phase conversion circuit.

【0005】[0005]

【発明の実施の形態】以下、本発明の実施形態を図面に
基づいて説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0006】(実施例1)図1は、請求項1記載の発明
に係る電圧制御発振回路の実施例を示す図である。図1
に示すようにリングオシレータ101の2つの出力Xお
よびXXは、2相/1相変換回路102および2相/1
相変換回路103の入力X、入力XAにそれぞれ接続さ
れる。図2はリングオシレータ101の内部構成を示す
図である。201は電圧を電流に変換するV/I変換回
路であり、202の可変電流源を制御する。また、20
3は1種の差動入力型オペアンプであり3段の直列接続
で自励発振し、電源電流を可変電流源202で変化させ
ることにより、発振周波数が変化するものである。ま
た、図3は2相/1相変換回路102の内部構成を示す
図、図4は2相/1相変換回路103の内部構成を示す
図である。2相/1相変換回路102と2相/1相変換
回路103は、お互いにVDD或いはVSSに対して対
称な回路構成とする。
(Embodiment 1) FIG. 1 is a diagram showing an embodiment of a voltage controlled oscillation circuit according to the first aspect of the present invention. FIG.
As shown in the figure, two outputs X and XX of the ring oscillator 101 are connected to a two-phase / one-phase conversion circuit 102 and a two-phase / 1-
The input X and the input XA of the phase conversion circuit 103 are respectively connected. FIG. 2 is a diagram showing the internal configuration of the ring oscillator 101. A V / I conversion circuit 201 converts a voltage into a current, and controls a variable current source 202. Also, 20
Reference numeral 3 denotes one type of differential input type operational amplifier, which self-oscillates in a three-stage series connection, and changes the oscillation frequency by changing the power supply current by the variable current source 202. 3 is a diagram showing an internal configuration of the two-phase / one-phase conversion circuit 102, and FIG. 4 is a diagram showing an internal configuration of the two-phase / one-phase conversion circuit 103. The two-phase / one-phase conversion circuit 102 and the two-phase / one-phase conversion circuit 103 have mutually symmetric circuit configurations with respect to VDD or VSS.

【0007】そして図6は本発明の電圧制御発振回路が
搭載されるクロックジェネレータ向けPLLの構成を示
す図である。図6において601は水晶振動子、602
は水晶発振回路、603は位相比較回路、604は低域
フィルター、605は電圧制御発振回路、606はプロ
グラマブルディバイダである。
FIG. 6 is a diagram showing a configuration of a PLL for a clock generator on which the voltage controlled oscillation circuit of the present invention is mounted. In FIG. 6, reference numeral 601 denotes a quartz oscillator;
Is a crystal oscillation circuit, 603 is a phase comparison circuit, 604 is a low-pass filter, 605 is a voltage controlled oscillation circuit, and 606 is a programmable divider.

【0008】従来は、図7のように差動型リングオシレ
ータ101と2相/1相変換回路702を組み合わせて
電圧制御発振回路を構成する。ここで2相/1相変換回
路702の内部構成は図3と同じである。この時、入力
端Vinの電圧Vinと出力端Outにおける出力周波
数f(X)は図8に示す関係となる。例えば電圧Vin
がV1の時の出力端Outにおける周波数はf(1)と
なる。この時の各部の波形を示したものが図9である。
図9において波形Aおよび波形XAは図7における2相
/1相変換回路702の入力端AおよびXAのもの、波
形Outは図7における2相/1相変換回路702の出
力端Outのもの、波形IAは図3における出力端Ou
tA側の電流源流れる電流の波形である。そして波形V
DDはこの電圧制御発振器の電源電圧の変動を示すもの
である。
Conventionally, as shown in FIG. 7, a differential ring oscillator 101 and a two-phase / one-phase conversion circuit 702 are combined to form a voltage-controlled oscillation circuit. Here, the internal configuration of the two-phase / one-phase conversion circuit 702 is the same as that in FIG. At this time, the voltage Vin at the input terminal Vin and the output frequency f (X) at the output terminal Out have the relationship shown in FIG. For example, the voltage Vin
Is V1, the frequency at the output terminal Out is f (1). FIG. 9 shows the waveform of each part at this time.
9, the waveform A and the waveform XA are those of the input terminals A and XA of the two-phase / one-phase conversion circuit 702 in FIG. 7, the waveform Out is that of the output terminal Out of the two-phase / one-phase conversion circuit 702 in FIG. The waveform IA corresponds to the output terminal Ou in FIG.
It is a waveform of the current flowing through the current source on the tA side. And the waveform V
DD indicates the fluctuation of the power supply voltage of the voltage controlled oscillator.

【0009】ところで従来の回路では、この電流IAに
よって生じる電源電圧の変動がPLLの出力特性、特に
ジッターに大きく影響していた。すなわち電圧制御発振
回路の動作による電源電圧の変動がノイズとなり、これ
が他の回路に影響を与え、ジッターを悪化させていた。
In the conventional circuit, the fluctuation of the power supply voltage caused by the current IA greatly affects the output characteristics of the PLL, particularly, the jitter. That is, the fluctuation of the power supply voltage due to the operation of the voltage-controlled oscillation circuit becomes noise, which affects other circuits and deteriorates the jitter.

【0010】そこで本発明は、これらの影響を低減する
ために図1のような回路構成とするものである。
Therefore, the present invention has a circuit configuration as shown in FIG. 1 in order to reduce these effects.

【0011】図1の構成において入力端VinにV1を
加えるとf(X)の周波数を持つ波形がリングオシレー
タから差動出力として出力され、2相/1相変換回路1
02と2相/1相変換回路103に入力される。この時
の各部の波形を示すものが図5である。図5において波
形Xおよび波形XXは図1におけるリングオシレータ1
01の出力端XおよびXXのもの、波形OutAは図1
における2相/1相変換回路102の出力端OutAの
もの、波形OutBは図1における2相/1相変換回路
103の出力端OutBのもの、波形IAは図3におけ
る出力端OutA側の電流源に流れる電流の波形、波形
IBは図4における出力端OutB側の電流源に流れる
電流の波形である。そして波形VDDAは2相/1相変
換回路102の動作により生じる電源電圧の変動、波形
VDDBは2相/1相変換回路103の動作により生じ
る電源電圧の変動であり、波形VDDはVDDAとVD
DBの和の電源電圧の変動を示すものである。OutA
とOutBは、2相/1相変換回路102と2相/1相
変換回路103の各々の入力端AおよびXAに入る信号
がちょうど反対となるため、お互いに反転の信号とな
る。この場合のVDDAおよびVDDBに生じる変化分
ΔVは、2相/1相変換回路102と2相/1相変換回
路103がVDDおよびVSSに対して対称な回路構成
であるため、VDDA、VDDBにおいてもその大きさ
は等しくなり、方向が互いに反対となる。また、タイミ
ングも同時期となる。よって結果として変化分のΔVは
VDDにおいて打ち消される事となる。
When V1 is applied to the input terminal Vin in the configuration of FIG. 1, a waveform having a frequency of f (X) is output as a differential output from the ring oscillator, and the two-phase / one-phase conversion circuit 1
02 and two-phase / one-phase conversion circuit 103. FIG. 5 shows the waveform of each part at this time. In FIG. 5, waveform X and waveform XX correspond to ring oscillator 1 in FIG.
01, the output terminals X and XX of FIG.
, The waveform OutB of FIG. 1 corresponds to the output terminal OutB of the two-phase / one-phase conversion circuit 103, and the waveform IA corresponds to the output terminal OutA of FIG. IB is a waveform of a current flowing through the current source on the output end OutB side in FIG. The waveform VDDA is the fluctuation of the power supply voltage caused by the operation of the two-phase / one-phase conversion circuit 102, the waveform VDDB is the fluctuation of the power supply voltage generated by the operation of the two-phase / one-phase conversion circuit 103, and the waveform VDD is the VDDA and VDD.
It shows the fluctuation of the power supply voltage of the sum of DB. OutA
And OutB are signals that are opposite to each other since the signals input to the input terminals A and XA of the two-phase / one-phase conversion circuit 102 and the two-phase / one-phase conversion circuit 103 are just opposite. In this case, the change ΔV generated in VDDA and VDDB is also generated in VDDA and VDDB because the two-phase / one-phase conversion circuit 102 and the two-phase / one-phase conversion circuit 103 have a symmetrical circuit configuration with respect to VDD and VSS. Their magnitudes are equal and their directions are opposite to each other. The timing is also the same. Therefore, as a result, the change ΔV is canceled at VDD.

【0012】[0012]

【発明の効果】以上説明したように本発明によれば、電
圧制御発振回路に複数の2相/1相変換回路を設け、各
々が発生する電源変動を打ち消すような2相/1相変換
回路の構成とすることで、電圧制御発振回路としては電
源変動を発生しないためノイズとはならず、前記電圧制
御発振回路が搭載されたPLLにおいてもジッターに影
響を及ぼさない。
As described above, according to the present invention, a plurality of two-phase / one-phase conversion circuits are provided in a voltage-controlled oscillation circuit, and a two-phase / one-phase conversion circuit that cancels out power supply fluctuations generated by each of the two-phase / one-phase conversion circuits. With the configuration described above, the voltage-controlled oscillation circuit does not generate power supply fluctuations, so that noise does not occur, and the PLL having the voltage-controlled oscillation circuit does not affect jitter.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を示す構成図。FIG. 1 is a configuration diagram showing one embodiment of the present invention.

【図2】図1におけるリングオシレータの内部構成図。FIG. 2 is an internal configuration diagram of a ring oscillator in FIG. 1;

【図3】図1における2相/1相変換回路の内部構成
図。
FIG. 3 is an internal configuration diagram of a two-phase / one-phase conversion circuit in FIG. 1;

【図4】図1における2相/1相変換回路の内部構成
図。
FIG. 4 is an internal configuration diagram of a two-phase / one-phase conversion circuit in FIG. 1;

【図5】図1における各部動作波形を説明するための
図。
FIG. 5 is a diagram for explaining operation waveforms of respective units in FIG. 1;

【図6】本発明の電圧制御発振回路が利用されるPLL
の構成図。
FIG. 6 shows a PLL in which the voltage controlled oscillation circuit of the present invention is used.
FIG.

【図7】従来の電圧制御発振回路を示す構成図。FIG. 7 is a configuration diagram showing a conventional voltage controlled oscillation circuit.

【図8】電圧制御発振回路の入出力特性を示す図。FIG. 8 is a diagram showing input / output characteristics of a voltage controlled oscillation circuit.

【図9】従来の電圧制御発振回路における各部の動作波
形を示す図。
FIG. 9 is a diagram showing operation waveforms of various parts in a conventional voltage controlled oscillation circuit.

【符号の説明】[Explanation of symbols]

101:リングオシレータ 102:2相/1相変換回路 103:2相/1相変換回路 201:V/I変換回路 202:可変電流源 203:差動入力型オペアンプ 601:水晶振動子 602:水晶発振回路 603:位相比較回路 604:低域フィルター 605:電圧制御発振回路 606:プログラマブルディバイダ 702:2相/1相変換回路 101: Ring oscillator 102: 2-phase / 1-phase conversion circuit 103: 2-phase / 1-phase conversion circuit 201: V / I conversion circuit 202: Variable current source 203: Differential input type operational amplifier 601: Crystal oscillator 602: Crystal oscillation Circuit 603: Phase comparison circuit 604: Low-pass filter 605: Voltage controlled oscillation circuit 606: Programmable divider 702: 2 phase / 1 phase conversion circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】差動出力型のリングオシレータと、前記リ
ングオシレータの差動出力を同相に変換する2相/1相
変換回路で構成する電圧制御発振回路において、正電源
電位および負電源電位に対して対称の回路構成とする前
記2相/1相変換回路を1対以上有し、発振動作で生じ
る電源変動を抑えることを特徴とする電圧制御発振回
路。
1. A voltage controlled oscillation circuit comprising a differential output type ring oscillator and a two-phase / single-phase conversion circuit for converting a differential output of the ring oscillator into an in-phase signal. A voltage-controlled oscillation circuit comprising one or more pairs of the two-phase / one-phase conversion circuit having a symmetrical circuit configuration to suppress power supply fluctuation caused by an oscillation operation.
JP9161678A 1997-06-18 1997-06-18 Voltage-controlled oscillation circuit Withdrawn JPH118533A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9161678A JPH118533A (en) 1997-06-18 1997-06-18 Voltage-controlled oscillation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9161678A JPH118533A (en) 1997-06-18 1997-06-18 Voltage-controlled oscillation circuit

Publications (1)

Publication Number Publication Date
JPH118533A true JPH118533A (en) 1999-01-12

Family

ID=15739771

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9161678A Withdrawn JPH118533A (en) 1997-06-18 1997-06-18 Voltage-controlled oscillation circuit

Country Status (1)

Country Link
JP (1) JPH118533A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003026129A1 (en) * 2001-09-12 2003-03-27 Thine Electronics, Inc. Semiconductor integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003026129A1 (en) * 2001-09-12 2003-03-27 Thine Electronics, Inc. Semiconductor integrated circuit
US7129795B2 (en) 2001-09-12 2006-10-31 Thine Electronics, Inc. Semiconductor integrated circuit with wiring arrangement for N-stage amplifying

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