JPH1185305A - Integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the test period and to improve the productivity by eliminating the need for a holding test even when a low-speed mode is set, by setting the signal hold period of a dynamic circuit to the time of one original oscillation clock width even when a system clock is set slow. SOLUTION: System clocks CKO 30 to CK2 32 are connected to the control signal for a dynamic holding operation and CK3 33 is connected to the control signal for a static operation. A data signal 24 is set to '1'. Then, CK1: 31 is inputted to a static latch 35 in timing of '1' and a system clock switching signal 27 becomes '1' to select the operation of a slow system clock. Consequently, CK0 to CK2 output '1' in order with the cycle width of one original oscillation clock in order and operate, but when CK3 reaches timing of '1', CK3 33 holds the timing of '1' until a 4th frequency-divided signal 12 rises. Thus, the dynamic circuit is supplied with the short-cycle pulses to operate and the need for a holding test using slow cycle pulses is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an integrated circuit device, and more particularly to an integrated circuit device having a low-speed operation mode and a high-speed operation mode.

[0002]

2. Description of the Related Art Conventionally, in order to reduce the size of a device,
Integrated circuit devices are frequently used. Here, a conventional integrated circuit device will be described with reference to the drawings.

FIG. 8 shows a circuit diagram of a conventional integrated circuit device. As shown in FIG. 8, this conventional integrated circuit device receives an oscillation circuit 51 that outputs a primary clock signal 52 as a signal of a fixed frequency, and a primary clock signal 52 that is output by the oscillation circuit 51, and generates an inverted primary circuit. Clock signal 5
4 and an inverter clock signal 52
And a first frequency divider circuit 55 that receives the inverted primary clock signal 54, outputs a first frequency-divided signal 56, and is initialized by a reset signal 64.

Further, a first frequency-divided signal 56 is input and a second
A second frequency divider circuit 57 that outputs a frequency-divided signal 58 and is initialized by a reset signal 64, and a second frequency-divided signal 58 that is input, outputs a third frequency-divided signal 60, and is initialized by the reset signal 64 A third frequency dividing circuit 59 and a third frequency divided signal 60
Is input, the fourth frequency-divided signal 62 is output, and the reset signal 6
4 and a static latch 66 to which a reset signal 64, a system clock CK1: 90 output from the inverter 86, and a data signal 65 are input.

[0005] Further, it has an inverter 67 which receives the output of the static latch 66 and outputs a system clock switching signal 68, and an inverter 69 which receives the system clock switching signal 68 and outputs an inverted system clock switching signal 70.

Further, a first frequency-divided signal 56 and an inverted system clock switching signal 70 are input, and a two-input NAND 73
, A third frequency-divided signal 60 and a system clock switching signal 68, and a two-input NAND
A two-input NAND 72 that outputs to ND 73 and a two-input NA
A two-input NAND 73 receives the outputs of the ND 71 and the two-input NAND 72 and outputs a first selected frequency-divided signal 74.

Further, an inverter 7 which receives a first selected frequency-divided signal 74 and outputs an inverted first selected frequency-divided signal 76 is provided.
5, a first selection frequency division signal 74 and an inverted first selection frequency division signal 76, a second selection frequency division signal 78 is output, and a second selection frequency division circuit 77 initialized by the reset signal 64
And an inverter 79 that receives the second selected frequency-divided signal 78 and outputs an inverted second selected frequency-divided signal 80.

[0008] Further, a first selected frequency-divided signal 74 and a second selected frequency-divided signal 78 are input and output to an inverter 85.
An input NAND 81, an inverter 85 which receives an output of the two-input NAND 81 as input, and outputs a system clock CK0: 89, and an inverted first selection frequency-divided signal 76 and a second selection frequency-divided signal 78, which are output to an inverter 86. A two-input NAND 82, an inverter 86 which receives an output of the two-input NAND 82 as input, and outputs a system clock CK1: 90, receives a first selected frequency-divided signal 74 and an inverted second selected frequency-divided signal 80, and outputs the same to an inverter 87 A two-input NAND 83, an output of the two-input NAND 83, an inverter 87 that outputs a system clock CK 2: 91, an inverted first selection frequency-divided signal 76 and an inverted second selection frequency-divided signal 80, and an inverter 88 Output to 2
It comprises an input NAND 84 and an inverter 88 which receives an output of the two-input NAND 84 and outputs a system clock CK3: 92.

Then, the system clocks CK0: 89,
CK1: 90, CK2: 91 and CK3: 92 are arbitrarily connected so that they can be used as control signals for dynamic holding operation and static holding operation of other peripheral circuits.

The above-described oscillation circuit 51 continues to output a clock having a certain period. Further, each of the frequency dividing circuits 55, 57,
59 and 61 are “1” indicating that the reset signal 64 is ON.
In the case of, a clock with a cycle twice as long as the input clock is
The divided signals 56, 58, 60 and 62 are output.

When the reset signal 64 is "0" indicating OFF, the oscillation circuit 51 is initialized,
"1" is output as each of the frequency-divided signals 56, 58, 60 and 62.

The static latch 66 shown in FIG.
Is initialized when the reset signal 64 is “0” indicating OFF, holds “1”, and outputs it.

When the reset signal 64 is "1" and the system clock CK1: 90 output from the inverter 87 is "1", the static latch 66 captures and holds the inversion of the data signal 65, Output.

When the system clock CK1: 90 output from the inverter 86 is "0", no data is taken in, and the previously held value is kept held.

Since the system clock switching signal 68 is "1" and is inverted by the inverter 69, the inverted system clock switching signal 70
Is "0", the two-input NAND 71 outputs "1" regardless of the value of the first frequency-divided signal 56.

The two-input NAND 72 inverts and outputs the third frequency-divided signal 60. As a result, two-input NAN
The output of D73, that is, the first selected divided signal 74 is the same as the third divided signal 60.

When the system clock switching signal 68 is "0" and the inverted system clock switching signal 70 is "1", the two-input NAND 71 inverts and outputs the first frequency-divided signal 56.

The two-input NAND 72 outputs "1" regardless of the value of the third frequency-divided signal 60. As a result, the output of the two-input NAND 73, that is, the first selected divided signal 74 becomes the same as the first divided signal 56.

The second selection frequency dividing circuit 77 outputs the reset signal 6
When 4 is “1”, a clock having a cycle twice as long as the first selected divided signal 74 is output to the second selected divided signal 78. When the reset signal 64 is “0”, it is initialized and outputs “1” to the second selected frequency-divided signal 78.

On the other hand, when the reset signal 64 becomes "0", each of the frequency-divided signals 56, 58, 60, 62 and 78
Is output as “1”.

At this time, the static latch 66 is also initialized and outputs "1". Therefore, the system clock switching signal 68 becomes “0”, and the first selected frequency-divided signal 74 becomes
The first divided signal 56 is obtained. However, here, the data signal 65 is set to “0”.

By the above operation, the first selected divided signal 74
Is “1”, and the second selected frequency-divided signal 78 is “1”.
If so, the two-input NAND 81 outputs a signal having a value of “0”, and the system clock CK0: 89 is output as “1”.

Similarly, when the inverted first selection frequency-divided signal 76 is "0" and the second selection frequency-divided signal 78 is "1", the two-input NAND 82 outputs "1". , The system clock CK1: 90 becomes “0”.

When the first selected frequency-divided signal 74 is "1" and the inverted second selected frequency-divided signal 80 is "0",
The two-input NAND 83 outputs “1”, and therefore, the system clock CK2: 91 becomes “0” due to the presence of the inverter 87.

When the inverted first selected frequency-divided signal 76 is "0" and the inverted second selected frequency-divided signal 80 is "0", the two-input NAND 84 outputs "1".
The system clock CK3: 92 becomes “0” due to the presence of the inverter 88.

When the reset signal 64 becomes "1", each of the frequency dividing circuits 5 is supplied by the primary clock 52 and the first selected frequency dividing signal 74 supplied from the oscillation circuit 51.
5, 57, 59, 61 and 77 generate clocks having a period twice as long as the input clocks by dividing the frequency-divided signals 56, 58, 6
Output as 0, 62 and 78.

Next, the signal timing of the integrated circuit device shown in FIG. 8 will be described with reference to FIG. FIG.
FIG. 8 shows a timing chart of the system clock shown in FIG. As shown in FIG. 9, when the timing of the primary clock is 1, the first selected frequency-divided signal 74 and the second selected frequency-divided signal 78 become “1” and the two-input NAND 8
1 are all input to the system clock CK0:
89 is output as "1". At this time, the other clocks CK1, CK2, and CK3 are output as "0".

Similarly, when the timing of the primary clock is timing 2, the inverted first selection frequency-divided signal 76 and the second selection frequency-divided signal 78 are "1", and "1" is input to the two-input NAND 82. , The system clock CK1: 90 is output as “1”. At this time, the other system clocks CK0, CK2, and CK3 are "0".
Is output as

Similarly, when the timing of the primary clock is timing 3, the first selected frequency-divided signal 74 and the inverted second frequency-divided signal 80 are "1", and all "1" is input to the two-input NAND 83. The system clock CK2: 91 is output as "1". At this time, the other system clocks CK0, CK1, and CK3 are “0”.
Is output as

Similarly, when the timing of the primary clock is timing 4, the inverted first selection frequency-divided signal 76 and the inverted second
The frequency-divided signal 80 is “1”, all “1” is input to the two-input NAND 84, and the system clock CK3: 92 is output as “1”. At this time, the other system clocks CK0, CK1, and CK2 are "0".
Is output as

Next, the operation at timing 1 described above will be described in more detail. In the case of the timing 1, each system clock CK0 to CK3 operates by sequentially outputting “1” within the width of one primary clock, but by changing the value of the system clock switching signal 68, Thus, a slower system clock operation can be selected.

The selection is made by setting the data signal 65 to "1". With this selection, the system clock CK1: 90 is taken into the static latch 66 at the timing of “1”, and the system clock switching signal 68 becomes “1”.

Therefore, when the system clock switching signal 68 changes to "1", CK0 to CK3 sequentially output "1" according to the width of the cycle of the four primary clocks and operate.

As described above, in the conventional integrated circuit device shown in FIG. 8, the system clocks CK0 to CK at equal intervals are provided.
3, the dynamic signal holding operation and the static signal holding operation of the other peripheral circuits are controlled. Therefore, if the system clock is set to be slow, the signal holding period of the dynamic circuit is correspondingly lengthened.

However, in the case of an integrated circuit, even if the system clock is set to be slow, it is necessary to provide a certain margin in order to guarantee the operation, and to perform the test by operating the system clock later than the settable system clock.

For this reason, in the conventional integrated circuit device, all the built-in functions must be operated at a low speed and the signal holding characteristics of the dynamic circuit must be tested. There was a problem that it was difficult to shorten.

Here, as an invention for solving the above-mentioned problem in the prior art, there is a "single-chip microcomputer" disclosed in Japanese Patent Application Laid-Open No. 6-96239. This single-chip microcomputer will be described below.

First, in order to solve the problems in the prior art, as a means for extending the operating frequency of the dynamic circuit to a low-speed range, there is an improvement in signal holding characteristics by increasing a capacitance value. Also lead to an increase,
Considering the cost, this is not a realistic solution.

Therefore, the invention disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 6-96329 produces a latch fetch signal asynchronous with the system clock, and the signal is latched before the signal in the dynamic holding state can no longer hold the value. It is a technology that we try to incorporate into

[0040]

However, the invention disclosed in the above-mentioned publication suppresses an increase in chip size and enables the operating frequency to be extended to a low-speed range. Since the analog circuit is used instead of the logic operation, the delay value of the delay circuit depends on the manufacturing conditions.
It may become larger than expected and cause a malfunction.

Therefore, it is not possible to omit the test of the signal holding characteristic of the dynamic circuit in which the system clock is slowed down when such a circuit is added.

In the case of a product that must be shipped in the tens of thousands per month as in the current production situation, the chip size is reduced as compared to the case where a single 6-inch wafer can take several thousands at a time. The reduction of the test time required to test each product has a greater contribution in terms of overall cost.

Therefore, it is more demanded to improve the signal holding characteristics of the dynamic circuit in consideration of the test time of the product than to improve the signal holding characteristics of the dynamic circuit in consideration of the chip size.

As described above, in order to test the holding characteristics of the dynamic circuit in both the conventional example and the known example, there is a problem that the test must be performed at a speed lower than the minimum settable system clock operating speed.

Therefore, this test takes time,
There is a problem that it is difficult to shorten the test time.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide an integrated circuit device capable of improving productivity and reducing test time.

[0047]

According to the first aspect of the present invention,
A system comprising: an oscillation circuit that supplies a primary clock; a first timing given by the fixed primary clock number; and a second timing given by the primary clock number that changes based on the setting of the cycle of the system clock. A time base for generating a clock and a control signal for controlling a dynamic holding operation are given as first timing given by the fixed number of primary clocks, and a control signal for controlling a static holding operation is A dynamic holding circuit provided as a second timing provided by the number of primary clocks that changes based on the setting of the cycle of the system clock.

According to a second aspect of the present invention, a first oscillation circuit (1) for outputting a primary clock signal and a primary clock signal (2) output from the first oscillation circuit are input, and an inverted primary clock is input. A first inverter (3) that outputs a signal (4), the primary clock signal, the inverted primary clock signal, and a reset signal (23) are input, and a first frequency-divided signal (6) is output. A first frequency dividing circuit (5), a second frequency dividing circuit (7) to which the first frequency divided signal and the reset signal are input and output a second frequency divided signal (8);
A third frequency divider circuit (9) that receives a frequency-divided signal and the reset signal and outputs a third frequency-divided signal (10);
A fourth frequency divider circuit (11) receives the frequency-divided signal and the reset signal and outputs a fourth frequency-divided signal (12).

Further, the second inverter (1) which receives the first frequency-divided signal and outputs an inverted first frequency-divided signal (15).
4) a third inverter (16) that receives the second frequency-divided signal and outputs an inverted second frequency-divided signal (17); the second frequency-divided signal; and a sixth inverter (28). And the inverted system clock switching signal (29) output from the first input terminal and the first 2
A first static latch (25) which receives an input NAND (34), the reset signal, the data signal (24), and the system clock CK1 (31) and outputs an output signal to the fifth inverter (26). ), A fifth inverter (26) receiving an output signal output from the first static latch and outputting a system clock switching signal (27), and a system clock switching output from the fifth inverter. And a sixth inverter (28) that receives the signal (27) and outputs an inverted system clock switching signal (29).

Further, the fourth frequency-divided signal (12) and the system clock switching signal output from the fifth inverter (26) are input, and a NAND operation is performed on the two input signals. 2 2-input NAND (35)
And a signal output from the first two-input NAND (34) and a signal output from the second two-input NAND (35), and the NAN of the two input signals is input.
A third operation for executing the D operation and outputting the selected frequency-divided signal (37)
, And an inverted first frequency-divided signal (15) output from the second inverter (14), and a fourth inverter (19) that outputs an inverted signal based on this signal. ) And an inverted first frequency-divided signal output from the second inverter (14), and a first delay circuit (1) that outputs a delay signal based on this signal.
8).

Further, the second frequency-divided signal (8), the inverted signal output from the fourth inverter (19),
The delay signal output from the first delay circuit (18) is input, and NOR of the two input signals is input.
A three-input NOR (20) for performing an operation;
The selected frequency-divided signal (3) output from the input NAND (36)
7), a second delay circuit (38) for outputting a delay signal based on this signal, and a selected frequency-divided signal output from the third two-input NAND (36). And a seventh inverter (39) that outputs an inverted signal based on

Further, the second delay circuit (38)
And the inverted signal output from the seventh inverter (39), and a second two-input NOR (4) for executing a NOR operation on these signals.
0), the reset signal (23) is input, an eighth inverter (41) that outputs an inverted reset signal (42) based on the reset signal, and the three-input NOR (2).
0) and the second three-input NOR (2
The signals output from 2) are input, and NO of these signals
A first two-input NOR (21) for performing an R operation, a signal output from the first two-input NOR (21), a signal output from the second two-input NOR (40),
It has an inverted reset signal (42) output from the eighth inverter (41) and a second three-input NOR (22) for executing a NOR operation on these signals.

Further, the first frequency-divided signal (6), the second frequency-divided signal (8), and the first two-input NOR (2
The system clock enable signal (43) output from 1) is input, and a first three-input NAND (44) that performs a NAND operation on these signals and the output from the second inverter (14). The inverted first frequency-divided signal (1
5), the second frequency-divided signal (8), and the system clock enable signal output from the first two-input NOR, and a second three-input NAND that performs a NAND operation on these signals (45), the first frequency-divided signal (6), the inverted second frequency-divided signal output from the third inverter (16), and the system clock enable output from the first two-input NOR. Signal and input,
A third three-input N for performing a NAND operation on these signals
AND (46).

Further, the first three-input NAND (4
4) is input and the system clock C
A ninth inverter (47) that outputs K0 (30);
A tenth inverter (48) that receives a signal output from the second three-input NAND (45) and outputs a system clock CK1 (31);
An eleventh inverter (49) that receives the signal output from the ND (46) and outputs the system clock CK2 (32), and outputs a system clock CK3 (33) that receives the system clock enable signal. 1
And two inverters (50).

According to a third aspect of the present invention, in the second aspect of the present invention, the first frequency dividing circuit (5), the second frequency dividing circuit (7), the third frequency dividing circuit (9), , The fourth frequency divider circuit (11) outputs the primary clock signal or
A C terminal to which a frequency-divided signal output from the previous frequency divider circuit is input, a CB terminal to which the inverted primary clock signal or the output signal is input, an R terminal to which the reset signal is input, And a 2CB terminal that outputs an output signal. The primary clock signal input from the C terminal or the frequency-divided signal output from the frequency divider circuit at the previous stage is input to the P side, A first transfer (311) for inputting an output signal input from the CB terminal to the N side.

Further, a reset signal input from the R terminal and an output signal output from the twenty-sixth inverter (313) are input, and NAN is added to the two input signals.
Eleventh 2-input NAND (301) for performing D operation
And the primary clock signal input from the C terminal or the frequency-divided signal output from the previous frequency divider is input to the N side, and the output signal input from the CB terminal is input to the P side, An output signal from the eleventh two-input NAND (301) is input, and the eleventh two-input NAND (301) is input.
26th inverter (313) for outputting an output signal to the inverter
And a twenty-third inverter (303) for receiving an output signal from the eleventh two-input NAND (301).

Further, the output signal input from the CB terminal is input to the P side, and the primary clock signal input from the C terminal or the frequency-divided signal output from the previous frequency divider is input to the N side. , The twenty-third inverter (30
A second transfer (315) to which a signal output from 3) is input, a 25th inverter (309) to which an output signal input from the 2CB terminal is input, and output an output signal based on the input signal; , The output signal input from the CB terminal is input to the N side, and the primary clock signal input from the C terminal or the frequency-divided signal output from the previous frequency divider circuit is input to the P-side, 2-input NA
The signal output from the ND (305) is input and the
And a twenty-seventh inverter (317) that outputs a signal to the two-input NAND.

Further, the reset signal and the twenty-seventh signal
And the signal output from the inverter (317) of the first input is input, and a first operation for performing a NAND operation on the two input signals is performed.
A two-input two-input NAND (305) and a twenty-fourth inverter (307) that receives a signal output from the twelfth two-input NAND and outputs a signal to the 2CB terminal.

According to a fourth aspect of the present invention, in the second or third aspect, the first static latch (25) outputs the reset signal and a signal output from a twenty-ninth inverter (405). And performs a NAND operation on these two signals.
D (407) and the thirteenth two-input NAND (40
7), the signal output from the twenty-eighth inverter (403) is input to the N side, and the signal output from the N side of the third transfer (401) is P
And a 29th inverter (405) for inputting an output signal to the third transfer (40).
A twenty-eighth inverter (403) connected to the N side of 1) and having an output connected to the P side of the third transfer;
A third transfer (401) has an output of the twenty-eighth inverter (403) connected to the P side and an input of the twenty-eighth inverter connected to the N side.

According to a fifth aspect of the present invention, in the first aspect of the present invention, the first delay circuit (18) and the second delay circuit (38) are provided.
A 30th inverter (501) to which the inverted first frequency-divided signal output from the second inverter (14) or the third two-input NAND (36) is input, and the 30th inverter A 31st inverter (505) to which a signal output from (501) is input;
A 32nd inverter (509) to which a signal output from the inverter (505) is input, and a 33rd inverter (513) to which a signal output from the 32nd inverter (509) is input and outputting a signal And

Further, the 30th inverter and the 31st inverter
, A first capacitor (503) connected in series with GND, a point between the 31st inverter and the 32nd inverter, and GND. Second capacitor (507) connected in series
And a third capacitor (511) connected in series between a point between the 32nd inverter and the 33rd inverter and GND.

According to a sixth aspect of the present invention, there is provided a second oscillation circuit (101) for outputting a primary clock signal (102), and a thirteenth inverter receiving the primary clock signal and outputting an inverted primary clock signal. 103), a first frequency dividing circuit (105) to which the primary clock signal, the inverted primary clock signal, and the reset signal are input and outputs a first frequency-divided signal and an output signal; Dividing circuit (10
5), the first frequency-divided signal (106), the output signal output from the first frequency-divider circuit, and the reset signal (114) are input, and the second frequency-divided signal (108) is output. A second frequency dividing circuit (107), the reset signal,
The second frequency-divided signal is input and the third frequency-divided signal (110)
And a third frequency dividing circuit (109) for outputting the same.

Further, a fourth frequency dividing circuit (111) which receives the reset signal and the third frequency divided signal and outputs a fourth frequency divided signal (112), the first frequency divided signal, The second frequency-divided signal is input, and a fourteenth two-input NAND (14
6) and a signal output from the fourteenth two-input NAND (146) are input, and a clock width control signal (148) is input.
A 34th inverter (147) that outputs a reset signal, a second static latch (116) that receives the reset signal and outputs a signal to a fourteenth inverter (117),
A signal output from the second static latch (116) is input and a system clock switching signal (118)
And a fourteenth inverter (117) for outputting the same.

Further, the third divided signal and the fourteenth
And a system clock switching signal (118) output from the inverter (117) of the second input NAN.
A fifth two-input NAND (122) that outputs a signal to D
A fifteenth inverter (119) that receives the system clock switching signal (120) and outputs an inverted system clock switching signal obtained by inverting this signal;
It has a fourth two-input NAND (121) that receives the frequency-divided signal and the inverted system clock switching signal and performs a NAND operation on the two input signals.

Further, the fourth two-input NAND (12
1) and the fifth two-input NAND
(122) and outputs a first selected frequency-divided signal (124).
23) and the first selected frequency-divided signal (124) is input,
Sixteenth inverter (125) that outputs the inverted signal
And a signal output from the sixth two-input NAND (123) and a signal output from the sixteenth inverter (125), and output a second selected frequency-divided signal (128). And a 2 selection frequency dividing circuit (127).

Further, the second selection frequency dividing circuit (127)
A seventeenth inverter (129) that receives the second selected frequency-divided signal output from the second input terminal and outputs an inverted second selected frequency-divided signal (130), the first selected frequency-divided signal, and the second selected frequency-divided signal. And the NAN of the two input signals
A seventh two-input NAND (131) for performing a D operation;
A first signal which receives a signal output from the seventh two-input NAND and outputs a system clock CK0 (139)
, The first selected frequency-divided signal, the second selected frequency-divided signal, and the clock control signal output from the thirty-fourth inverter. And a fourth three-input NAND (143) for performing a NAND operation.

Further, a signal output from the fourth three-input NAND is input, and a subsystem clock CKD0 is input.
Twenty-second inverter (144) that outputs (145)
And a signal output from the sixteenth inverter (125) and a second selection frequency-divided signal (128) output from the second selection frequency-dividing circuit. Eighth two-input NAND (1
32) and the signal output from the eighth two-input NAND (132), and the system clock CK1 (14
0) which outputs a 0th inverter.

Further, the seventeenth inverter (12
9) the inverted second selection frequency-divided signal output from
And a ninth two-input NAND (133) that receives the first selected frequency-divided signal output from the two-input NAND and executes a NAND operation on the two input signals;
A twentieth inverter (137) that receives a signal output from the input NAND and outputs a system clock CK2 (141), and an inverted second selection frequency-divided signal (130) output from the seventeenth inverter (129). ) And a signal output from the sixteenth inverter, and a tenth two-input NAND (134) for performing a NAND operation on the input two signals.

Further, the signal output from the tenth two-input NAND is input, and the system clock CK3 (1
42) and a twenty-first inverter (138) for outputting (42).

The invention according to claim 7 is the invention according to claim 6, wherein the first frequency divider (105), the second frequency divider (107), the third frequency divider (109), The fourth frequency dividing circuit (111) receives the C terminal to which the primary clock signal or the frequency-divided signal output from the preceding frequency dividing circuit is input, and the inverted primary clock signal or the output signal. A CB terminal, an R terminal to which the reset signal is input, a 2C terminal to output a divided signal, and a 2CB terminal to output an output signal,
A primary clock signal input from the C terminal, or
There is provided a first transfer (311) in which a frequency-divided signal output from the frequency divider circuit of the preceding stage is input to the P side, and an output signal input from the CB terminal is input to the N side.

Further, the reset signal input from the R terminal and the output signal output from the twenty-sixth inverter (313) are input, and an eleventh two-input NAND which executes a NAND operation on these two input signals. (301), the primary clock signal input from the C terminal or the frequency-divided signal output from the frequency divider at the previous stage is input to the N side,
An output signal input from the CB terminal is input to the P side, an output signal from the eleventh two-input NAND (301) is input, and an output signal is output to the eleventh two-input NAND (301). 26 inverters (313).

Further, the eleventh two-input NAND (3
01) and the 23rd inverter (303) for inputting the output signal from the CB terminal.
, And the primary clock signal input from the C terminal or the frequency-divided signal output from the preceding frequency divider is input to the N-side, and the signal output from the twenty-third inverter (303) is The input second transfer (31
5), a second output signal is input from the 2CB terminal, and an output signal is output based on the input signal.
5 inverters (309).

Further, the output signal input from the CB terminal is input to the N side, and the primary clock signal input from the C terminal or the divided signal output from the preceding frequency divider is input to the P side. , A twelfth two-input NAND (30
5) is input and the twelfth two-input N
A twenty-seventh inverter that outputs a signal to the AND (317)
, The reset signal, and the 27th inverter (3
17), and a twelfth two-input NAND that performs a NAND operation on the two input signals
(305) and a twenty-fourth inverter (307) that receives a signal output from the twelfth two-input NAND and outputs a signal to the 2CB terminal.

According to an eighth aspect of the present invention, in the first or second aspect of the present invention, the second static latch (116) outputs the reset signal and a signal output from a twenty-ninth inverter (405). And enter these two
Thirteenth two-input NA for performing NAND operation of two signals
ND (407) and the thirteenth two-input NAND (40
7) is inputted, the signal outputted from the 28th inverter (403) is inputted to the N side, the signal outputted from the N side of the third transfer (401) is inputted to the P side, and the output is outputted. 29th inverter for outputting a signal (405)
A twenty-eighth inverter (403) having an input connected to the N-side of the third transfer (401) and an output connected to the P-side of the third transfer, and the twenty-eighth inverter (403). Is connected to the P side, and the second
And a third transfer (401) in which the input of the eight inverters is connected to the N side.

[0075]

Next, an embodiment of an integrated circuit device according to the present invention will be described with reference to the drawings. FIG.
1 shows a circuit diagram of a first embodiment of the integrated circuit device according to the present invention.

As shown in FIG. 1, this integrated circuit device has an oscillation circuit 1, an inverter clock 3 which receives a primary clock signal 2 output from the oscillation circuit 1 and outputs an inverted primary clock signal 4, A first frequency divider circuit that receives the signal 2 and the inverted primary clock signal 4 as input, outputs a first frequency-divided signal 6, and is initialized by a reset signal 23;

Further, the first frequency-divided signal 6 is input and the second
A second frequency divider circuit 7 that outputs a frequency-divided signal 8 and is initialized by a reset signal 23, and a second frequency-divided signal 8 that is input, outputs a third frequency-divided signal 10, and is initialized by the reset signal 23 The third frequency dividing circuit 9 and the third frequency dividing signal 10 are input, the fourth frequency dividing signal 12 is output, and the reset signal 23
And a fourth frequency dividing circuit 11 initialized by

Further, an inverter 14 which receives the first frequency-divided signal 6 and outputs an inverted first frequency-divided signal 15, and an inverter which receives the second frequency-divided signal 8 and outputs an inverted second frequency-divided signal 17 16 and the inverted first frequency-divided signal 15 as inputs,
A delay circuit 18 that outputs to a three-input NOR 20, an inverted first frequency-divided signal 15 as an input, an inverter 19 that outputs to a three-input NOR 20, an output of the delay circuit 18 and the inverter 19, and a second frequency-divided signal 8 as an input , And a three-input NOR20 for outputting to a two-input NOR21 of the RS latch.

Further, a static latch 25 to which a reset signal 23, a system clock CK1: 31, and a data signal 24 are inputted, an inverter 26 to which an output of the static latch 25 is inputted and a system clock switching signal 27 is outputted, And an inverter 28 that receives the clock switching signal 27 and outputs an inverted system clock switching signal 29.

Further, the second frequency-divided signal 8 and the inverted system clock switching signal 29 are input, the two-input NAND 34 for outputting to the two-input NAND 36, the fourth frequency-divided signal 12 and the system clock switching signal 27 are input, and Input NAN
D36, a two-input NAND 35 and a two-input NAN
D34 and a two-input NAND 36 which receives the outputs of the two-input NAND 35 and outputs a selected frequency-divided signal 37.

Further, the selected frequency-divided signal 37 is input, and 2
A delay circuit 38 for outputting to the input NOR 40, an inverter 39 which receives the selected frequency-divided signal 37 and outputs to the two-input NOR 40, a delay circuit 38 and an inverter 39
, And a two-input NOR 40 for outputting to the three-input NOR 22 of the RS latch.

Further, an inverter 41 which receives the reset signal 23 as an input and outputs an inverted reset signal 42, an output of the two-input NOR 40 and an output of the two-input NOR 21 of the RS latch, and an inverted reset signal 42 as inputs, and outputs the inverted signal of the RS latch. 3-input NOR of RS latch which outputs to input NOR21
22, 3-input NOR20 and 3-input NO of RS latch
It has a two-input NOR21 of an RS latch that receives the output of R22 and outputs a system clock enable signal 43.

Further, the first divided signal 6 and the second divided signal 8
And the system clock enable signal 43 as an input,
The three-input NAND 44 output to the inverter 47 and the output of the three-input NAND 44 are input to the system clock C.
An inverter 47 that outputs K0: 30, an inverted first frequency-divided signal 15, a second frequency-divided signal 8, and a system clock enable signal 43 are input and output to an inverter 48.
It has an input NAND 45 and an inverter 48 which receives the output of the three-input NAND 45 and outputs the system clock CK1: 31.

The three-input NAND 46 receives the first frequency-divided signal 6, the inverted second frequency-divided signal 17, and the system clock enable signal 43 and outputs the signal to the inverter 49.
And an inverter 49 receiving the output of the three-input NAND 46 and outputting the system clock CK2: 32, and an inverter 50 receiving the system clock enable signal 43 and outputting the system clock CK3: 33.

Here, in the above-described integrated circuit device,
System clocks CK0: 30, CK1: 31, and C
K2: 32 is connected to a control signal of a dynamic holding operation of another peripheral circuit, and a system clock CK3: 33 is connected to a control signal of a static holding operation of another peripheral circuit.

Next, each member constituting the first embodiment of the integrated circuit device according to the present invention shown in FIG. 1 will be described in more detail.

First, the oscillation circuit 1 keeps outputting a clock having a certain period. Each frequency dividing circuit 5, 7, 9 and 11
When the reset signal 23 is “1”, a clock having a cycle twice as long as the input clock is output as each of the divided signals 6, 8, 10 and 12.

When the reset signal 23 is "0", it is initialized and outputs "1" to each of the frequency-divided signals 6, 8, 10 and 12.

When the reset signal 23 is "0", the static latch 25 is initialized, holds "1", and outputs it.

When the reset signal 23 is "1" and the system clocks CK1: 31 are "1", the inverted data signal 24 is fetched, held, and output.

When the system clocks CK1: 31 are "0", the values held previously are output without taking in.

Next, when the system clock switching signal 27 is "1" and the inverted system clock switching signal 2
When 9 is “0”, the two-input NAND 34 outputs “1” regardless of the second frequency-divided signal 8.

The two-input NAND 35 outputs the fourth divided signal 12
Is output. As a result, the two-input NAND
36, that is, the selected frequency-divided signal 37 is the fourth frequency-divided signal 1
It becomes the same as 2.

Next, when the system clock switching signal 27 is "0" and the inverted system clock switching signal 2
When 9 is “1”, the two-input NAND 34 outputs an inverted version of the second frequency-divided signal 8.

The two-input NAND 35 outputs the fourth divided signal 12
Regardless of, "1" is output. As a result, two-input NA
The output of the ND 36, that is, the selected divided signal 37 is the same as the second divided signal 8.

The delay circuit 18, the inverter 19, and the three-input NOR 20 are a rising edge detection circuit of the inverted first frequency-divided signal 15, and normally output "0", but the second frequency-divided signal 8 is "0". In some cases, when the rising edge of the inverted first frequency-divided signal 15 is detected, the three-input NOR 20 outputs a pulse of “1” corresponding to the delay width of the delay circuit 18.

When the second frequency-divided signal 8 is "1", the three-input NOR 20 always outputs "0" even if the rising edge of the inverted first frequency-divided signal 15 is detected.

The delay circuit 38, the inverter 39, and the two-input NOR 40 are a rising edge detection circuit for the selected frequency-divided signal 37, and normally output "0". NOR4
0 outputs a pulse of “1” corresponding to the delay width of the delay circuit 38.

When the reset signal 23 is “0”, that is, when the inverted reset signal 42 is “1”, the RS latch composed of the two-input NOR 21 and the three-input NOR 22
The output of the OR 21, that is, the system clock enable signal 43 becomes "1".

When the reset signal 23 is “1”, that is, when the inverted reset signal 42 is “0”, when a “1” pulse is input from the three-input NOR 20 to the two-input NOR 21,
The output of the two-input NOR 21, that is, the system clock enable signal 43 becomes "0".

The pulse of "1" from the 2-input NOR 40 is
When input to the three-input NOR 22, the output of the two-input NOR 21, that is, the system clock enable signal 43 becomes “1”. When the reset signal 23 is “0”, each of the frequency-divided signals 6, 8, 10, and 12 becomes “1”.

In addition, when the reset signal 23 is "0", the static latch 25 is also initialized and outputs "1".
The system clock switching signal 27 becomes “0”, and the selected frequency-divided signal 37 becomes the second frequency-divided signal 8. The system clock enable signal 43 becomes "1". Here, the data signal 24 is set to “0”.

Thus, the first frequency-divided signal 6 is “1”, and the 3-input NAND 44 is “0” from “1” of the second frequency-divided signal 8.
And the system clock CK0: 30 becomes “1”.

Similarly, when the inverted first frequency-divided signal 15 is “0”, three inputs N from “1” of the second frequency-divided signal 8
AND45 outputs "1" and outputs the system clock CK.
1:31 becomes “0”. When the first frequency-divided signal 6 is “1”,
Since the inverted second frequency-divided signal 17 is “0”, three inputs N
AND 46 outputs “1” and outputs the system clock CK.
2:32 is “0”.

At this time, the system clock CK3: 33 from the inverter 50 to which "1" of the system clock enable signal 43 is input becomes "0".

By the reset signal 23 of “1”, each of the frequency dividers 5, 7, 9 and 11 generates a clock having a cycle twice as long as the input clock from the primary clock 2 supplied from the oscillation circuit 1. Output to the divided signals 6, 8, 10, and 12.

The timing of each signal of the integrated circuit device shown in FIG. 1 will be described below with reference to FIG.
FIG. 2 shows a timing chart of each signal shown in FIG. As shown in FIG. 2, at timing 1, the first frequency-divided signal 6, the second frequency-divided signal 8, and the system clock enable signal 43 are "1", and "1" is all inputted to the three-input NAND 44. The clock CK0: 30 becomes "1". Other system clocks CK1: 31, C
K2: 32 and CK3: 33 are "0".

Similarly, at timing 2, the inverted first frequency-divided signal 15, the second frequency-divided signal 8, and the system clock enable signal 43 are "1", and the 3-input NAND 45 is all "1".
Is input, and the system clock CK1: 31 becomes “1”. Other system clocks CK0: 30, CK2: 3
2, CK3: 33 is “0”.

At timing 3, the first divided signal 6, the inverted second divided signal 17, the system clock enable signal 4
3 is “1”, all “1” is input to the 3-input NAND 46, and the system clock CK2: 32 becomes “1”.
Other system clocks CK0: 30, CK1: 31, C
K3: 33 becomes "0".

At timing 4, the condition is that the second frequency-divided signal 8 is “0” and the inverted first frequency-divided signal 15 rises, and the three-input NOR 20 sequentially has “the width of the delay circuit 18,” Pulses of "0", "1" and "0" are generated.

As a result, the system clock enable signal 43 becomes "0", and the three-input NANDs 44, 45,
46, the respective system clocks CK0 to CK2 become “0”, and the inverter 50 makes the system clocks CK3: 33 become “1”.

Thereafter, at the rise of the second frequency-divided signal 8, that is, the selected frequency-divided signal 37, the two-input NOR 40 sequentially has "0", "1",
A "0" pulse is generated. As a result, the system clock enable signal 43 becomes "1" and the three-input NAN
D44, 45, and 46 input to the system clock CK
0:30 is “1”, CK1: 31 and CK2: 32 are “0”. The system clock CK3: 33 becomes “0” by the inverter 50 and returns to the timing 1.

At this time, each system clock CK0 to CK
3 operates by sequentially outputting “1” within the width of one primary clock cycle, but by changing the value of the system clock switching signal 27, it is possible to select a slower operation of the system clock.

For this, the data signal 24 is set to “1”. The system clock CK1: 31 is taken into the static latch 25 at the timing of "1", and the system clock switching signal 27 becomes "1". As a result, each of the system clocks CK0 to CK2 operates by sequentially outputting “1” within the width of one primary clock cycle. When the timing of CK3 becomes “1”, the fourth frequency-divided signal 12 rises. Until then, the timing of the system clock CK3: 33 is "1". That is, the system clock CK3: 3
3 has an interval of 13 primary clock widths.

Next, the first frequency divider 5, the second frequency divider 7, the third frequency divider 9, and the fourth frequency divider 1 shown in FIG.
1 will be described in more detail with reference to FIG. FIG. 3 shows a circuit diagram of the first frequency divider 5, the second frequency divider 7, the third frequency divider 9, and the fourth frequency divider 11 shown in FIG.

As shown in FIG. 3, each frequency divider shown in FIG. 1 includes a C terminal to which a primary clock signal or a frequency-divided signal output from a previous frequency divider is input, and an inverted primary clock. A CB terminal to which a signal or output signal is input, an R terminal to which a reset signal is input, a 2C terminal to output a frequency-divided signal, and a 2C terminal to output an output signal
B terminal.

Further, the primary clock signal input from the C terminal or the frequency-divided signal output from the previous frequency divider is input to the P side, and the output signal input from the CB terminal is the N signal.
, A reset signal input from the R terminal, and an output signal output from the inverter 313, a two-input NAND 301 that performs NAND operation on the two input signals, and an input from the C terminal. The input clock signal or the frequency-divided signal output from the previous-stage frequency divider circuit is input to the N side, the output signal input from the CB terminal is input to the P side, and the output signal from the two-input NAND 301 is input. And an inverter 313 that outputs an output signal to the two-input NAND 301.

Further, an inverter 303 for inputting an output signal from the two-input NAND 301, an output signal input from the CB terminal to the P side, and a primary clock signal input from the C terminal or a frequency divider circuit in the preceding stage. The output frequency-divided signal is input to the N side, the transfer 315 to which the signal output from the inverter 303 is input, and the inverter to which the output signal input from the 2CB terminal is input and which outputs an output signal based on the input signal. 309, the output signal input from the CB terminal is input to the N side, and the primary clock signal input from the C terminal or the frequency-divided signal output from the previous frequency divider circuit is input to the P side, and the two-input NAND
The signal output from 305 is input, and the two-input NAN
And an inverter 317 that outputs a signal to D305.

Here, the inverters 313 and 317 are both configured as clocked inverters.

Further, the reset signal and the inverter 31
7, a two-input NAND 305 for performing a NAND operation on the two input signals, and a signal output from the two-input NAND 305,
An inverter 307 that outputs a signal to the 2CB terminal.

Next, the static latch 25 included in the first embodiment of the integrated circuit device according to the present invention shown in FIG. 1 will be described with reference to FIG. FIG. 4 shows a circuit diagram of the static latch 25.

As shown in FIG. 4, the static latch 25 receives a reset signal and a signal output from the inverter 405, and outputs the NAN of these two signals.
Two-input NAND 407 for executing D operation, and two-input NA
The signal output from the ND 407 is input and the inverter 4
An inverter 405 that outputs the signal from the N-side to the N-side and outputs the signal from the N-side of the transfer 401 to the P-side and outputs an output signal;
The inverter 403 whose output is connected to the P side of the transfer, and the output of the inverter 403 is
And a transfer 401 whose input of the inverter 403 is connected to the N side.

Here, the above-mentioned inverter 405 is configured as a clocked inverter.

Next, the delay circuit 18 included in the first embodiment of the integrated circuit device according to the present invention shown in FIG.
The delay circuit 38 will be described with reference to FIG. FIG. 5 is a circuit diagram of the delay circuit 18 and the delay circuit 38 shown in FIG.

As shown in FIG. 5, this delay circuit includes an inverter 14 or an inverter 5 to which an inverted first frequency-divided signal output from a two-input NAND 36 is input.
01, the inverter 505 to which the signal output from the inverter 501 is input, the inverter 509 to which the signal output from the inverter 505 is input, and the inverter 50
9, an inverter 513 that receives and outputs a signal, a point between the inverter 501 and the inverter 505, a capacitor 503 connected in series between the inverter 513 and GND, and the inverter 505 and the inverter 509. , A capacitor 507 connected in series between GND, and a point between inverters 509 and 513, and a capacitor 5 connected in series between GND.
11 is provided.

Therefore, according to the first embodiment of the integrated circuit device of the present invention shown in FIG. 1, in a normal operation state, the static circuit is operated by giving a pulse having a long cycle to the static circuit in the low-speed operation mode. However, since the dynamic circuit is operated by applying short-period pulses, it is possible to eliminate the need for a dynamic retention test using slow-period clock pulses, thereby improving productivity and reducing test time. Can be.

Next, a second embodiment of the integrated circuit device according to the present invention will be described with reference to FIG. FIG. 6 shows a circuit diagram of a second embodiment of the integrated circuit device according to the present invention. As shown in FIG. 6, the integrated circuit device includes an oscillation circuit 101, a primary clock signal 102 output from the oscillation circuit 101, and an inverter 103 that receives the primary clock signal 102 and outputs an inverted primary clock signal 104.
And the primary clock signal 102 and the inverted primary clock signal 1
And a first frequency dividing circuit 105 that receives the signal 04, outputs a first frequency-divided signal 106, and initializes with a reset signal 114.

Further, the first frequency-divided signal 106 is input, and
A second frequency divider 107 that outputs a second frequency-divided signal 108 and initializes with a reset signal 114, a second frequency-divided signal 108 as input, outputs a third frequency-divided signal 110, and initializes with a reset signal 114 And a fourth frequency dividing circuit 111 which receives the third frequency dividing signal 110 as an input, outputs a fourth frequency dividing signal 112, and initializes with a reset signal 114.

Further, a static latch 116 to which a reset signal 114, a system clock CK1: 140, and a data signal 115 are input, and a static latch 11
6 as an input, and a system clock switching signal 118
, An inverter 119 which receives a system clock switching signal 118 as an input and outputs an inverted system clock switching signal 120, and a first frequency-divided signal 1
06 and the inverted system clock switching signal 120 are input, and the two-input NAND 1 is output to the two-input NAND 123.
21 and a two-input NAND 122 which receives a third frequency-divided signal 110 and a system clock switching signal 118 as input and outputs the same to a two-input NAND 123.

Further, the outputs of the two-input NAND 121 and the two-input NAND 122 are input, and the first selected frequency-divided signal 1
24, an inverter 125 which receives a first selected frequency-divided signal 124 and outputs an inverted first selected frequency-divided signal 126, and a first selected frequency-divided signal 12
4. A second selection / division circuit 127 that receives the inverted first selection / division signal 126, outputs a second selection / division signal 128, and initializes with the reset signal 114, and a second selection / division signal 12
8 and an inverter 129 that outputs an inverted second selection frequency-divided signal 130.

Further, the first selected frequency-divided signal 124 and the second
A two-input NAND 131 which receives the selected frequency-divided signal 128 as an input and outputs it to the inverter 135, and a two-input NAND 131
, And an inverter 135 that outputs the system clocks CK0 and 139, and an inverted first selected frequency-divided signal 1
26, a two-input NAND 132 that receives the second selected frequency-divided signal 128 and outputs the same to the inverter 136,
The output of the ND 132 is used as an input and the system clock CK
Inverter 136 that outputs 1: 140, two-input NAND 133 that receives first selected frequency-divided signal 124 and inverted second selected frequency-divided signal 130 and outputs to inverter 137
And

Further, an inverter 137 which receives an output of the two-input NAND 133 and outputs a system clock CK2: 141, an inverted first selection frequency-divided signal 126 and an inverted second selection frequency-divided signal 130, and receives an inverter 138
, A two-input NAND 134 and a two-input NAND 1
34 as an input and the system clock CK3: 14
And an inverter 138 that outputs the output signal 2.

Further, a two-input NAND 146 which receives the first frequency-divided signal 106 and the second frequency-divided signal 108 and outputs the same to the inverter 147, and an inverter which receives the output of the two-input NAND 146 and outputs the clock width control signal 148. 147, a first selected frequency-divided signal 124, a second selected frequency-divided signal 128, and a clock width control signal 148, and a three-input NAND 143 that outputs to the inverter 144
An inverter 144 receives the output of the input NAND 143 and outputs the subsystem clocks CKD0: 145.

Here, the subsystem clock CKD0:
145 is a dynamic holding operation of another peripheral circuit, and each system clock CK0: 139, CK1: 140, CK2:
141, CK3: 142 are arbitrarily connected to a control signal of a static holding operation of another peripheral circuit.

The oscillation circuit 101 keeps outputting a clock having a certain period.

Each frequency dividing circuit 105, 107, 109, 11
1 indicates that when the reset signal 114 is “1”, a clock having a cycle twice as long as the input clock is applied to each of the frequency-divided signals 106, 1
Output as 08, 110, 112. Reset signal 1
When 14 is “0”, initialization is performed, and “1” is set to each divided signal 1
Output as 06, 108, 110, 112.

When the reset signal 114 is "0", the static latch 116 is initialized and holds "1".
Output. When the reset signal 114 is “1” and the system clock CK1: 140 is “1”, the data signal 115
Captures, inverts, and outputs. When the system clock CK1: 140 is "0", it does not capture and outputs the previously held value.

The system clock switching signal 118 is "1" and the inverted system clock switching signal 120 is "0".
At this time, the two-input NAND 121 outputs “1” regardless of the first frequency-divided signal 106. 2-input NAND 122
Outputs an inverted version of the third frequency-divided signal 110. as a result,
The output of the two-input NAND 123, that is, the first selected frequency-divided signal 1
24 becomes the same as the third frequency-divided signal 110.

The system clock switching signal 118 is "0" and the inverted system clock switching signal 120 is "1".
At this time, the two-input NAND 121 outputs an inverted version of the first frequency-divided signal 106. The two-input NAND 122 outputs “1” regardless of the third frequency-divided signal 110. As a result, 2
The output of the input NAND 123, that is, the first selected divided signal 12
4 is the same as the first frequency-divided signal 106.

When the reset signal 114 is “1”, the second selection / divider circuit 127 outputs a clock having a cycle twice as long as the first selection / divider signal 124 to the second selection / divider signal 128.
When the reset signal 114 is “0”, it is initialized and “1”
To the second selected frequency-divided signal 128.

The two-input NAND 146 outputs the first divided signal 1
When both 06 and the second frequency-divided signal 108 are “1”, “0” is output to the inverter 147, and otherwise “1” is output. Inverter 147 that outputs clock width control signal 148 inverts and outputs the output from two-input NAND 146.

When the reset signal 114 is "0", each of the frequency-divided signals 106, 108, 110, 112 and 128 becomes "1". As a result, the clock width control signal 148 becomes "1". The static latch 116 is also initialized and "1"
Is output. System clock switching signal 118 is "0"
And the first selected divided signal 124 becomes the first divided signal 10
It becomes 6. Here, the data signal 115 is set to “0”.

Thus, the two-input NAND 131 outputs “0” from “1” of the clock width control signal 148, “1” of the first selected frequency-divided signal 124, and “1” of the second selected frequency-divided signal 128. The three-input NAND 143 outputs “0”, the system clock CK0: 139 becomes “1”, and the subsystem clock CKD0: 145 becomes “1”.

Similarly, the inverted first selection frequency-divided signal 126
, The two-input NAND 132 outputs "1", and the system clock CK1: 140 becomes "0".

Next, "1" of the first selected frequency-divided signal 124,
Two-input NAN from "0" of inverted second selection frequency-divided signal 130
D133 outputs “1” and the system clock CK2:
141 becomes "0".

From the “0” of the inverted first selection / divided signal 126 and “0” of the inverted second selected / divided signal 130, the two-input NAN
D134 outputs "1" and the system clock CK3:
142 becomes “0”.

When the reset signal 114 is “1”, the primary clock 102 supplied from the oscillation circuit 101 and the first clock
Each of the frequency dividing circuits 105, 10
7, 109, 111, and 127 generate clocks having a period twice as long as the input clock, by dividing the frequency-divided signals 106, 108,
Output as 110, 112, 128.

Next, the timing of each signal of the second embodiment of the integrated circuit device according to the present invention shown in FIG. 6 will be described with reference to FIG. FIG. 7 shows a timing chart of each signal of the integrated circuit device shown in FIG.

At timing 1 as shown in FIG.
The first selection frequency-divided signal 124 and the second selection frequency-divided signal 128 are “1”, all “1” are input to the two-input NAND 131, and the system clocks CK0: 139 become “1”.
Other system clocks CK1: 140, CK2: 14
1, CK3: 142 becomes “0”, and from the “1” of the clock width control signal 148, the 3-input NAND 143 becomes “0”.
Output. As a result, the subsystem clock CKD
0: 145 becomes “1”.

Similarly, at the timing 2, the inverted first selection division signal 126 and the second selection division signal 128 are “1”, and
All “1” s are input to the two-input NAND 132, the system clocks CK1: 140 become “1”, and the other system clocks CK0: 139, CK2: 141, CK3:
142 is "0". Also, the clock width control signal 14
8 from “0”, the subsystem clock CKD0: 14
5 is output as "0".

At timing 3, the first selected frequency-divided signal 12
4 and the inverted second frequency-divided signal 130 are “1” and the two-input NA
All “1” s are input to the ND 133, the system clocks CK2: 141 become “1”, and the other system clocks CK0: 139, CK1: 140, and CK3: 142 become “0”. Subsystem clocks CKD0: 145 become "0" from "0" of clock width control signal 148.

At timing 4, the inverted first selected frequency-divided signal 126 and the inverted second frequency-divided signal 130 are “1”, all “1” are input to the two-input NAND 134, and the system clock CK3: 142 is “1”. And the other system clocks CK0: 139, CK1: 140, CK2: 141
Becomes “0”. Subsystem clocks CKD0: 145 become "0" from "0" of clock width control signal 148.

The operation returns to timing 1 again. At this time, each of the system clocks CK0 to CK3 operates by sequentially outputting “1” within the width of the cycle of one primary clock. Action can be selected.

For this, the data signal 115 is set to “1”. The system clock CK1: 140 is taken into the static latch 116 at the timing of “1”, and the system clock switching signal 118 becomes “1”. As a result, the third frequency-divided signal 110 is selected, a system clock is generated based on the frequency-divided signal, and each of the system clocks CK0 to CK3 sequentially outputs “1” within the width of four primary clocks to operate. I do. However, the subsystem clocks CKD0: 145 output "1" of one primary clock width when CK0: 139 becomes "1", and output "0" at other system clock timings.

Here, the configuration of each of the frequency divider circuits 105, 107, 109, 111, and 127 included in the integrated circuit device shown in FIG. 6 is shown in FIG. 3, as in the first embodiment. Also, the configuration of the static latch 116 is
As in the first embodiment, since it is shown in FIG. 4, its description is omitted.

Therefore, according to the second embodiment of the integrated circuit device of the present invention shown in FIG. 6, the same effect as that of the integrated circuit device shown in FIG. 1 can be obtained.

[0157]

As is apparent from the above description, according to the present invention, even when the system clock is set to be slow, the signal holding period of the dynamic circuit is one primary clock width, which is the same as in the high-speed mode. It is not necessary to execute the retention test in the low-speed mode, and the test period can be shortened. Therefore, it is possible to provide an integrated circuit device that can improve the productivity and reduce the test time. .

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of an integrated circuit device according to the present invention.

FIG. 2 is a timing chart of each signal of the integrated circuit device shown in FIG.

FIG. 3 is a circuit diagram of a frequency divider provided in the integrated circuit device shown in FIGS. 1 and 6;

FIG. 4 is a circuit diagram of a static latch included in the integrated circuit device shown in FIGS. 1 and 6;

5 is a circuit diagram of a delay circuit included in the integrated circuit device shown in FIG.

FIG. 6 is a circuit diagram of a second embodiment of the integrated circuit device according to the present invention.

7 is a timing chart of each signal of the integrated circuit device shown in FIG.

FIG. 8 is a circuit diagram of a conventional integrated circuit device.

9 is a timing chart of each signal of the integrated circuit device shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Oscillation circuit 2 Primary clock signal 3 Inverter 4 Inverted primary clock signal 5 1st divider circuit 6 1st divider signal 7 2nd divider circuit 8 2nd divider signal 9 3rd divider circuit 10 3rd divider signal REFERENCE SIGNS LIST 11 fourth frequency dividing circuit 12 fourth frequency dividing signal 14 inverter 15 inverted first frequency dividing signal 16 inverter 17 inverted second frequency dividing signal 18 delay circuit 19 inverter 20 three-input NOR 21 two-input NOR 22 three-input NOR 23 reset signal 24 Data signal 25 Static latch 26 Inverter 27 System clock switching signal 28 Inverter 29 Inverted system clock switching signal 30 System clock CK0 31 System clock CK1 32 System clock CK2 33 System clock CK3 34 2-input NAND 35 2-input NAND 36 2-input NA D 37 Selection frequency division signal 38 Delay circuit 39 Inverter 40 2-input NOR 41 Inverter 42 Inverted reset signal 43 System clock enable signal 44 3-input NAND 45 3-input NAND 46 3-input NAND 47 Inverter 48 Inverter 49 Inverter 50 Inverter 101 Inverter 101 Oscillator 102 Primary clock signal 103 Inverter 104 Inverted primary clock signal 105 First frequency divider 106 First frequency divider 107 Second frequency divider 108 Second frequency divider 109 Third frequency divider 110 Third frequency divider 111 Fourth frequency Frequency divider circuit 112 Fourth divided signal 114 Reset signal 115 Data signal 116 Static latch 117 Inverter 118 System clock switching signal 119 Inverter 120 Inverted system clock switching signal 1 1 two-input NAND 122 two-input NAND 123 two-input NAND 124 first selection division signal 125 inverter 126 inverted first selection division signal 127 second selection division circuit 128 second selection division signal 129 inverter 130 inverted second selection Divided signal 131 2-input NAND 132 2-input NAND 133 2-input NAND 134 2-input NAND 135 inverter 136 inverter 137 inverter 138 inverter 139 system clock CK0 140 system clock CK1 141 system clock CK2 142 system clock CK3 143 3-input NAND 144 inverter 145 Subsystem clock CKD0 146 2-input NAND 147 Inverter 148 Clock width control signal 301 2-input NAND 303 Inver Data 305 2-input NAND 307 inverter 309 inverter 311 transfer 313 inverter 315 transfer 317 inverter 401 transfer 403 inverter 405 inverter 407 2-input NAND 501 inverter 503 capacitor 505 inverter 507 capacitor 509 inverter 511 capacitor 513 inverter

Claims (8)

[Claims] An oscillator circuit for supplying a primary clock; a first timing given by the fixed primary clock number; and a second timing given by a primary clock number that changes based on the setting of the cycle of the system clock. And a control signal for controlling the dynamic holding operation is provided as a first timing given by the fixed number of primary clocks to control the static holding operation. Wherein the control signal is provided as a second timing given by the number of primary clocks that changes based on the setting of the cycle of the system clock. 2. A first oscillation circuit (1) for outputting a primary clock signal; a primary clock signal (2) output from the first oscillation circuit being input; and an inverted primary clock signal (4) output. A first inverter (3), a first frequency divider circuit that receives the primary clock signal, the inverted primary clock signal, and a reset signal (23) and outputs a first frequency-divided signal (6) 5) a second frequency divider circuit (7) that receives the first frequency-divided signal and the reset signal and outputs a second frequency-divided signal (8); the second frequency-divided signal; A third frequency divider circuit (9) that receives a reset signal and outputs a third frequency-divided signal (10); a third frequency-divided signal that receives the third frequency-divided signal and the reset signal; Fourth frequency divider (11) for outputting 12)
The first frequency-divided signal is input, and the inverted first frequency-divided signal (15)
A second inverter (14) for outputting the second divided signal, and an inverted second divided signal (17)
, The second frequency-divided signal, and the inverted system clock switching signal (29) output from the sixth inverter (28), and the NAND of these two inputs is input. A first two-input NAND (34) for executing an operation, the reset signal, a data signal (24), and a system clock CK1 (31) are input, and an output signal is output to a fifth inverter (26). A first static latch (25), a fifth inverter (26) that receives an output signal output from the first static latch, and outputs a system clock switching signal (27); A sixth inverter (28) that receives a system clock switching signal (27) output from the inverter and outputs an inverted system clock switching signal (29); A second two-input NAND (35) that receives a divide-by-4 signal (12) and a system clock switching signal output from the fifth inverter (26), and performs a NAND operation on the two input signals. ), The signal output from the first two-input NAND (34) and the signal output from the second two-input NAND (35) are input, and a NAND operation of the input two signals is performed. The third 2 which executes and outputs the selected frequency-divided signal (37)
An input NAND (36), and an inverted first output from the second inverter (14).
A fourth inverter (19) that receives a frequency-divided signal (15) and outputs an inverted signal based on the signal; and an inverted first inverter that is output from the second inverter (14).
A first delay circuit (18) that receives a frequency-divided signal and outputs a delay signal based on the signal; the second frequency-divided signal (8); and the fourth inverter (1).
A three-input NOR (20) which receives the inverted signal output from the first delay circuit (18) and the delay signal output from the first delay circuit (18), and performs a NOR operation on the two input signals; A second delay circuit (38) that receives a selected frequency-divided signal (37) output from the third two-input NAND (36) and outputs a delay signal based on the signal; A seventh inverter (39) that receives the selected frequency-divided signal output from the input NAND (36) and outputs an inverted signal based on the signal; and a delay output from the second delay circuit (38). And a second two-input NOR (40) for performing a NOR operation on these signals and a reset signal (23). I An eighth inverter (41) that outputs an inverted reset signal (42) based on the reset signal; a signal output from the three-input NOR (20);
The signal output from the 3-input NOR (22) is input,
A first two-input NO that performs a NOR operation on these signals
R (21), a signal output from the first two-input NOR (21), a signal output from the second two-input NOR (40), and an output from the eighth inverter (41). The inverted reset signal (42) is input, and N
A second three-input NOR (22) for performing an OR operation; the first frequency-divided signal (6); and the second frequency-divided signal (8)
And a system clock enable signal (43) output from the first two-input NOR (21), and a first three-input NA for executing NAND operation of these signals.
ND (44), and the inverted first output from the second inverter (14).
A frequency-divided signal (15), the second frequency-divided signal (8), and a system clock enable signal output from the first two-input NOR are input, and a second operation for performing NAND operation on these signals is performed. , The first frequency-divided signal (6), and the third inverter (1).
6) and the inverted second frequency-divided signal output from the first 2
A third three-input NAND (46) that receives a system clock enable signal output from an input NOR and executes a NAND operation on these signals; and a signal output from the first three-input NAND (44). And a ninth inverter (47) that outputs a system clock CK0 (30) and a signal output from the second three-input NAND (45) and outputs a system clock CK1 (31). A tenth inverter (48); an eleventh inverter (49) that receives a signal output from the third three-input NAND (46) and outputs a system clock CK2 (32); A twelfth inverter (50) for receiving a signal and outputting a system clock CK3 (33). Road equipment. 3. The first frequency dividing circuit (5), the second frequency dividing circuit (7), the third frequency dividing circuit (9), and the fourth frequency dividing circuit (9).
A frequency dividing circuit (11), a C terminal to which the primary clock signal or the frequency dividing signal output from the preceding frequency dividing circuit is input, a CB terminal to which the inverted primary clock signal or the output signal is input, An R terminal to which the reset signal is input, a 2C terminal to output a divided signal, and an output terminal to output an output signal.
A primary clock signal input from the C terminal, or
A first transfer (311) in which a frequency-divided signal output from a previous frequency divider circuit is input to the P side and an output signal input from the CB terminal is input to the N side; and a reset signal input from the R terminal And the output signal output from the 26th inverter (313),
A first operation for performing a NAND operation on these two input signals is described below.
A two-input NAND (301), a primary clock signal input from the C terminal, or
The frequency-divided signal output from the preceding frequency divider circuit is input to the N side, the output signal input from the CB terminal is input to the P side, and the output signal from the eleventh two-input NAND (301) is input. And the eleventh two-input NAND (301)
26th inverter (313) for outputting an output signal to the inverter
A twenty-third inverter (303) for inputting an output signal from the eleventh two-input NAND (301); and an output signal input from the CB terminal to the P side and a nuclear power source input from the C terminal. A clock signal or a frequency-divided signal output from the previous frequency divider is input to the N side,
A second transfer (315) to which a signal output from the twenty-third inverter (303) is input; and a twenty-fifth input to which an output signal input from the 2CB terminal is input and an output signal is output based on the input signal. And the output signal input from the CB terminal is input to the N side, and the primary clock signal input from the C terminal or the frequency-divided signal output from the previous frequency divider circuit is input to the P side. Input,
A 27th inverter (317) that receives a signal output from the twelfth two-input NAND (305) and outputs a signal to the twelfth two-input NAND (305); the reset signal; 31
12) a twelfth two-input NAND that receives the signal output from 7) and performs a NAND operation on the two input signals
3. The integrated circuit according to claim 2, further comprising: (305) a twenty-fourth inverter (307) that receives a signal output from the twelfth two-input NAND and outputs a signal to the 2CB terminal. Circuit device. 4. The first static latch (25).
Are the reset signal and the 29th inverter (40
5), and a thirteenth two-input NAND (4
07), the signal output from the thirteenth two-input NAND (407) is input, the signal output from the twenty-eighth inverter (403) is input to the N side, and the third transfer (40)
The signal output from the N side of 1) is input to the P side and the 29th inverter (405) that outputs an output signal is connected to the N side of the third transfer (401), and the output is A twenty-eighth inverter (403) connected to the P-side of the third transfer; an output of the twenty-eighth inverter (403) is connected to the P-side; and an input of the twenty-eighth inverter is connected to the N-side. 4. The integrated circuit device according to claim 2, further comprising a third transfer (401). 5. The first delay circuit (18) and the second delay circuit (38) are connected to the second inverter (14) or the third two-input NAND (36). A 30th inverter (501) to which the output inverted first frequency-divided signal is input; a 31st inverter (505) to which a signal output from the 30th inverter (501) is input; A 32nd inverter (509) to which a signal output from the inverter (505) is input; and a 33rd inverter (51) to which a signal output from the 32nd inverter (509) is input and output a signal.
3) a first capacitor (503) connected in series between a point between the thirtieth inverter and the thirty-first inverter; GND; and a thirty-first inverter and a thirty-second inverter. A second capacitor (507) connected in series with GND, a point between the 32nd inverter and the 33rd inverter, and a series between GND. The integrated circuit device according to any one of claims 2 to 4, further comprising a third capacitor (511) connected thereto. 6. A second oscillation circuit (101) that outputs a primary clock signal (102); a thirteenth inverter (103) that receives the primary clock signal and outputs an inverted primary clock signal; A first frequency divider circuit (105) to which a clock signal, the inverted primary clock signal, and a reset signal are input and that outputs a first frequency-divided signal and an output signal; and the first frequency-divider circuit (105). The first frequency-divided signal (106) output from the first frequency-dividing circuit, the output signal output from the first frequency-divider circuit, and the reset signal (114) are input, and the second frequency-divided signal (108) is output. A third frequency dividing circuit (10) which receives the reset signal and the second frequency dividing signal and outputs a third frequency dividing signal (110);
9), the reset signal and the third frequency-divided signal are input, and the fourth frequency-divided circuit (11) outputs the fourth frequency-divided signal (112).
1), the first frequency-divided signal, and the second frequency-divided signal are input, and a first operation for executing a NAND operation on the input two signals is performed.
A four-input two-input NAND (146); a thirty-fourth inverter (147) receiving a signal output from the fourteenth two-input NAND (146) and outputting a clock width control signal (148); The signal is input and the fourteenth inverter (11
7) that outputs a signal to the second static latch (11).
6), the signal output from the second static latch (116) is input, and the system clock switching signal (118)
A fourteenth inverter (117) for outputting the third divided signal and the fourteenth inverter (11
7) The system clock switching signal (11
8), and a fifth two-input NAND (122) that outputs a signal to a sixth two-input NAND; and an inverted system clock switch that receives the system clock switching signal (120) and inverts this signal. A fourth two-input NAND that receives a fifteenth inverter (119) that outputs a signal, the first frequency-divided signal, and the inverted system clock switching signal, and performs a NAND operation on the two input signals; (121), the signal output from the fourth two-input NAND (121) and the signal output from the fifth two-input NAND (122) are input, and the first selected frequency-divided signal (124 ), And a sixteenth inverter (125) that receives the first selected frequency-divided signal (124) and outputs the inverted signal, and a sixth two-input NAND (123) that outputs the inverted signal. The signal output from the NAND (123) and the signal output from the sixteenth inverter (125) are input, and the second selection frequency dividing circuit (127) outputs the second selection frequency dividing signal (128). ) And a second selected frequency-divided signal output from the second selected frequency-divided circuit (127), and an inverted second selected frequency-divided signal (130).
A seventeenth inverter (129) for outputting the first selected frequency-divided signal and the second selected frequency-divided signal, and performing a NAND operation on the inputted two signals. A NAND (131), a first output which receives a signal output from the seventh two-input NAND and outputs a system clock CK0 (139);
, The first selected frequency-divided signal, the second selected frequency-divided signal, and the clock control signal output from the thirty-fourth inverter. A fourth three-input NAND (143) for executing a NAND operation, a twenty-second inverter (144) receiving a signal output from the fourth three-input NAND and outputting a subsystem clock CKD0 (145); A signal output from the sixteenth inverter (125) and a second selection frequency-divided signal (128) output from the second selection frequency-dividing circuit are input, and NAND operation of the two input signals is performed. 8th input NAND (13
2), a nineteenth inverter (136) that receives a signal output from the eighth two-input NAND (132) and outputs a system clock CK1 (140), and a seventeenth inverter (129). The output inverted second selection frequency-divided signal and the first selection frequency-divided signal output from the sixth two-input NAND are input.
Ninth two-input NAN for performing NAND operation of two signals
D (133) and a signal output from the ninth two-input NAND, and output a system clock CK2 (141).
0, an inverted second selection frequency-divided signal (130) output from the seventeenth inverter (129), and a signal output from the sixteenth inverter. Tenth two-input NAND for performing NAND operation of two signals
(134), and a second signal which receives the signal output from the tenth two-input NAND and outputs the system clock CK3 (142).
An integrated circuit device, comprising: one inverter (138). 7. The first frequency divider (105), the second frequency divider (105)
The frequency dividing circuit (107), the third frequency dividing circuit (109), and the fourth frequency dividing circuit (111) generate the primary clock signal or the frequency divided signal output from the preceding frequency dividing circuit. A C terminal for input, a CB terminal for inputting the inverted primary clock signal or output signal, an R terminal for inputting the reset signal, a 2C terminal for outputting a frequency-divided signal, and a 2 for outputting an output signal.
A primary clock signal input from the C terminal, or
A first transfer (311) in which a frequency-divided signal output from a previous frequency divider circuit is input to the P side and an output signal input from the CB terminal is input to the N side; and a reset signal input from the R terminal And the output signal output from the 26th inverter (313),
An eleventh two-input NAND (301) that performs a NAND operation on these two input signals, and a primary clock signal input from the C terminal, or
The frequency-divided signal output from the preceding frequency divider circuit is input to the N side, the output signal input from the CB terminal is input to the P side, and the output signal from the eleventh two-input NAND (301) is input. And the eleventh two-input NAND (301)
26th inverter (313) for outputting an output signal to the inverter
A twenty-third inverter (303) for inputting an output signal from the eleventh two-input NAND (301); and an output signal input from the CB terminal to the P side and a nuclear power source input from the C terminal. A clock signal or a frequency-divided signal output from the previous frequency divider is input to the N side,
A second transfer (315) to which a signal output from the twenty-third inverter (303) is input; and a twenty-fifth input to which an output signal input from the 2CB terminal is input and an output signal is output based on the input signal. And the output signal input from the CB terminal is input to the N side, and the primary clock signal input from the C terminal or the frequency-divided signal output from the previous frequency divider circuit is input to the P side. Input,
A 27th inverter (317) that receives a signal output from the twelfth two-input NAND (305) and outputs a signal to the twelfth two-input NAND (305); the reset signal; 31
12) a twelfth two-input NAND that receives the signal output from 7) and performs a NAND operation on the two input signals
7. The integrated circuit according to claim 6, further comprising: (305), and a twenty-fourth inverter (307) that receives a signal output from the twelfth two-input NAND and outputs a signal to the 2CB terminal. Circuit device. 8. The second static latch (11)
6) receives the reset signal and the signal output from the twenty-ninth inverter (405), and outputs the NA of the two signals.
Thirteenth two-input NAND (407) for performing ND operation
And the signal output from the thirteenth two-input NAND (407) is input, output from the twenty-eighth inverter (403) and input to the N side, and the N signal of the third transfer (401) is input.
A 29th inverter (405) that inputs a signal output from the P-side to the P-side and outputs an output signal, an input is connected to the N-side of the third transfer (401), and an output is the third transfer (401). A twenty-eighth inverter (403) connected to the P-side of the transfer; an output of the twenty-eighth inverter (403) being connected to the P-side; and an input of the twenty-eighth inverter being connected to the N-side. 8. The integrated circuit device according to claim 6, further comprising three transfer devices (401).