JPH118394A - Semiconductor device and manufacture of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a TFT using crystalline silicon film which is capable of crystallizing silicon through heat treatment at a temperature lower than when conventional temperature and eliminating the effects of a crystal grain boundary. SOLUTION: An activated layer 102 is partially exposed as shown in (D) and nickel element, a metallic element which accelerates crystallization of silicon, is introduced. The region where the nickel element has been introduced becomes a source/drain region later on. By heat treatment crystal growth of nickel is from the selectively introduced region to the masked region (a channel region is formed in this region) as shown in (E). The growing end of the crystallization collides in the center of the region becoming the channel, and the crystal grain boundary 108 is formed there. The use of nickel enables lowering the temperature, the grain boundary are similarly formed for all TFTs, and the effects of the grain boundary is averaged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
The present invention relates to a structure of a thin film transistor (hereinafter, referred to as a TFT) and a manufacturing method thereof.

[0002]

2. Description of the Related Art A TFT using a silicon film formed on a glass substrate or a quartz substrate is known. Currently, an amorphous silicon TFT using an amorphous silicon film as an active layer is mainly commercialized.

[0003] The TFT is mainly used in an active matrix circuit of an active matrix type liquid crystal display device.

A TFT using an amorphous silicon film as an active layer
Are disadvantageous in that only the N-channel type is put into practical use and the operation speed is very low. (Because of these drawbacks, it can be said that it is used only for active matrix circuits)

Techniques for solving this problem include:
There is a method of using a crystalline silicon film as a silicon film constituting an active layer.

As a method for obtaining a crystalline silicon film, there are a method by irradiating a laser beam and a method by heating.

[0007] In the method using laser light irradiation, an amorphous silicon film formed by a CVD method or the like is crystallized by irradiating laser light.

In the heating method, an amorphous silicon film formed by a CVD method or the like is crystallized by heating.

In the crystallization method by laser light irradiation, commercial laser oscillation devices have not reached the level of practical use.
There is a problem mainly in the stability of oscillation. Therefore, there is a problem in the uniformity of the film quality of the obtained crystalline silicon film and the productivity.

[0010] On the other hand, the heating method has a problem that although a stable film quality can be obtained, it is difficult to use a glass substrate because the heating temperature is high. In addition, due to a clear polycrystalline state, the existence of a crystal grain boundary exists as an unstable element.

For example, when a large number of TFTs are simultaneously formed on the same substrate, the formation positions and states of the grain boundaries existing in the active layers (particularly, channel regions) of the individual TFTs vary from one TFT to another. This causes a variation in the characteristics of each TFT.

In such a situation, how to lower the heat treatment temperature in crystallization by heating becomes an issue. Another problem is to obtain a manufacturing process in which a clear crystal grain boundary is not formed or in which the existence of a crystal grain boundary can be controlled.

[0013]

SUMMARY OF THE INVENTION An object of the invention disclosed in this specification is to provide a technique for solving the above-mentioned problem.

That is, it is an object to provide a technique capable of solving the following problems. (1) Crystallization by heat treatment is performed at a lower temperature than before. (2) Eliminate the influence of grain boundaries.

[0015]

Means for Solving the Problems One of the inventions disclosed in this specification is an active layer, a gate insulating film formed on the active layer, a gate electrode formed on the gate insulating film, In the active layer, the tip portion grown from the source and drain regions has a structure in which the tip portion collides with the center of the channel region, and the source and drain regions have a higher crystallization of silicon than in the channel region. It is characterized in that a promoting metal element is contained at a higher concentration.

In the above structure, it is most preferable to use nickel as a metal element for promoting crystallization of silicon. Nickel is excellent in reproducibility and effect of crystallization, and can perform gettering with phosphorus most effectively.

Metal elements that promote crystallization of silicon include Fe, Co, Ni, Ru, Rh, Pd, Os, and I.
r, Pt, Cu, Au, Ge, Pd, Pd, In, Sb
One or a plurality of elements selected from the following can be used.

In the above structure, the region where the crystal has grown is:
It has a structure in which a crystal grain boundary extends in a direction in which the crystal grows, and a crystal structure extends in a column in the direction.

This crystal structure can be obtained particularly remarkably when crystal growth utilizing nickel is performed.

According to another aspect of the invention, there is provided a manufacturing process of a structure having an active layer, a gate insulating film formed on the active layer, and a gate electrode formed on the gate insulating film,
A step of selectively introducing a metal element that promotes crystallization of silicon into a region serving as a source and a drain, and performing a heat treatment to perform crystal growth from the region serving as the source and the drain toward a region serving as a channel region. A step of introducing phosphorus into the source and drain regions, and a step of performing heat treatment to move the metal element from the channel region to the source and drain regions. It is characterized by the following.

In the above structure, the step of introducing a metal element includes a method using a solution containing the metal, a CV
D method, sputtering method, gas adsorption method, ion implantation method, diffusion method and the like can be used.

The introduction of phosphorus can be carried out in a similar manner.

According to another aspect of the present invention, there is provided a manufacturing process of a structure having an active layer, a gate insulating film formed on the active layer, and a gate electrode formed on the gate insulating film,
Removing the gate insulating film on the source and drain regions, holding a metal element that promotes silicon crystallization in contact with the source and drain regions, and subjecting the source and drain to heat treatment A step of performing crystal growth from a region to be a channel region to a region to be a channel region; a step of introducing phosphorus to the region to be a source and a drain; and performing a heat treatment from the region to be a channel region to the source and a drain. And moving the metal element toward the region to be formed.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG.
02 is exposed, and a nickel element which is a metal element for promoting crystallization of silicon is introduced therein. The region into which the nickel element has been introduced will later become a source / drain region.

By performing a heat treatment, FIG.
As shown in (E), the crystal is grown from the region into which nickel has been selectively introduced to the masked region (a channel region will be formed later in this region).

The tip of crystal growth collides with a central region serving as a channel region, and a crystal grain boundary 108 is formed there.

Thereafter, as shown in FIG. 2A, the regions 201 and 203 are doped with phosphorus, and then a heat treatment is performed, so that the regions 202 and 203 are also removed from the regions 201 and 203.
Nickel is moved to the area of.

Thus, the nickel concentration in the region 202 is reduced. At this time, the nickel concentration in the region 202 is set to 1 × 10 ¹⁷ atom cm ⁻³ or less.

It is preferable that the nickel concentration in the source and drain regions is 1000 times or more as compared with the Ni concentration in the channel region. It is desirable that the concentration of phosphorus in the source and drain regions is three times or more as compared with the Ni concentration in the final state.

In the above process, the direction axis of the crystal growth and the direction axis of the movement of the metal element from the region serving as the channel region toward the regions serving as the source and the drain coincide with or substantially coincide with each other.

By doing so, it is possible to reduce the probability that the movement of carriers in the axial direction is hindered by crystal grain boundaries, and it is possible to obtain a TFT having high mobility.

In the above process, by using nickel, crystallization can be performed by a heat treatment at a lower temperature than in the prior art.

Further, since the crystal grain boundary is always formed at the center of the channel region, it is possible to suppress the influence of the crystal grain boundary from affecting the variation in TFT characteristics.

[0034]

【Example】

[Embodiment 1] FIG. 1 shows a manufacturing process of this embodiment. First, an amorphous silicon film (not shown) is formed on a glass substrate 101 by a thickness of 50 nm.
The film is formed by the reduced pressure thermal CVD method to a thickness of 3 mm. (Figure 1
(A))

Here, a Corning 1737 glass substrate (strain point 667 ° C.) is used as the glass substrate. In addition to a glass substrate, a quartz substrate or a semiconductor substrate over which an insulating film is formed can be used as a substrate.

The amorphous silicon film is formed by the low pressure thermal CVD method because the silicon film formed by the low pressure thermal CVD method has a low concentration of hydrogen contained in the film and is easily crystallized. .

After an amorphous silicon film (not shown) is formed, the film is patterned to form a pattern 102. This pattern is crystallized in a later step and further becomes an active layer of the TFT.

Next, a silicon oxide film 103 is formed to a thickness of 100 nm. Part of the silicon oxide film will later become a gate electrode of the TFT.

Next, a microcrystalline silicon film having a strong N-type is formed and patterned to form a pattern 104. This pattern 104 becomes a gate electrode of the TFT. Thus, the state shown in FIG.

Next, a silicon oxide film 105 is formed to a thickness of 100 nm by a plasma CVD method. (FIG. 1 (B))

Then, the silicon oxide film 105 is etched using a dry etching method having vertical anisotropy. At this time, by adjusting the etching conditions, the silicon oxide film can be left in the portion indicated by reference numeral 106. This technique is known as sidewall technology. (Figure 1
(B))

Thus, as shown in FIG. 1C, the side wall 10 made of a silicon oxide film
A state in which 0 remains can be obtained.

Next, the exposed silicon oxide film 103 is etched by a dry etching method having vertical anisotropy. Thus, as shown in FIG.
Is obtained.

The active layer 102 is formed in a region other than the region where the gate electrode 104 and the side wall 100 exist.
Is obtained.

Then, a nickel acetate solution adjusted to a predetermined concentration is applied to obtain a state in which the nickel element is held in contact with the surface as indicated by 107. In this state, a state is obtained in which the nickel element is held in contact with the exposed region of the active layer pattern 102. (Fig. 1 (D))

The concentration of nickel in the nickel acetate solution is 100 ppm. This concentration range is 10p
It can be selected from the range of pm to 10,000 ppm.

Next, in a nitrogen atmosphere, at 570.degree.
A heat treatment for 0 hour is performed. In this step, arrow 1
The crystal growth indicated by 07 proceeds. This crystal growth
A collision occurs near the center of the gate electrode 104, and a crystal grain boundary 108
To form

As will become clear later, in this step, nickel element is introduced into the regions to be the source and drain regions, and crystal growth proceeds from the regions toward the channel region.

The tip of the crystal growth proceeding from the source and drain regions (more precisely, the regions that will later become the source and drain) and the channel regions at the center of the channel region (more precisely, the region that will later become the channel region). The parts collide with each other, and crystal grain boundaries as shown by 108 in FIG.

When a large number of TFTs are manufactured at the same time, the crystal grain boundaries are formed in the same portions in each TFT in the same manner.

In this way, when a large number of TFTs are manufactured, the influence of the crystal grain boundaries can be made the same for each TFT, and the variation in the characteristics of each TFT can be suppressed.

That is, by employing the manufacturing process shown in this embodiment, the position and the state of the crystal grain boundary formed in the active layer can be controlled.
In this case, variations in characteristics in the case of manufacturing the semiconductor device can be suppressed.

Next, doping of phosphorus is performed by a plasma doping method. In this step, as shown in FIG. 2A, the regions 201 and 203 are doped with phosphorus in a self-aligned manner. Also, doping is not performed on the region 202. It is to be noted that a region 201 is later a source region, and a region 203
Region becomes a drain region.

Next, heat treatment is performed at 600 ° C. for 2 hours in a nitrogen atmosphere. In this step, the nickel element existing in the region 202 along the route indicated by 204 is 2
It is sucked out in areas 01 and 203.

The above heating temperature can be selected from the range of 550 ° C. to 800 ° C. If the temperature is higher than this temperature range, diffusion of phosphorus occurs, and the purpose of segregating with nickel in a specific region cannot be achieved.

If the heating is performed at a temperature lower than the above-mentioned temperature range, the rate of movement of nickel is small, and the treatment cannot be carried out in an industrially effective time. Naturally, the gettering effect of nickel is reduced.

Thus, the nickel element existing in the region 202 is gettered in the regions 201 and 203. (FIG. 2 (B))

Next, the silicon nitride film 2 is formed by the plasma CVD method.
05 is formed to a thickness of 200 nm, and an acrylic resin film 206 is further formed. Here, the thickness of the acrylic resin film is 700 nm at the minimum. (Fig. 2 (C))

In addition to the acrylic resin, materials such as polyimide, polyamide, polyimide amide and epoxy can be used.

Next, a contact hole is formed, and FIG.
As shown in (D), the source electrode 207 and the drain electrode 2
08 is formed.

In this embodiment, the region 211 immediately below the gate electrode becomes a channel region. And 209 and 2
The ten regions become high resistance regions called offset regions. As described above, an N-channel TFT is completed.

In the TFT shown in this embodiment, the nickel element is diffused from the regions to be the source and drain regions, whereby the crystal is grown toward the region to be the channel region.

In this way, when a large number of TFTs are manufactured, a crystal grain boundary can be formed near the center of the channel region in each TFT. Thus, it is possible to suppress the characteristics from being varied among the TFTs.

[Embodiment 2] This embodiment is an example in which the structure of the gate electrode is improved in the structure shown in Embodiment 1. Here, an example in which a structure in which a phosphorus-doped silicon film and a titanium silicide film are stacked as a gate electrode is shown.

Examples of the structure of the gate electrode include a stacked structure of a silicon film having one conductivity type and molybdenum silicide, a stacked structure of a silicon film having one conductivity type and tungsten silicide, and the like.

[Embodiment 3] This embodiment is an example in which, in the structure shown in Embodiment 1, doping of phosphorus in the step shown in FIG. 2A is performed by diffusion.

In this embodiment, an example is shown in which a PSG film is formed in the state shown in FIG. 2A and phosphorus is diffused into the exposed active layer.

Except for the case of forming a PSG film, a solution containing phosphorus is applied, and then a heat treatment is performed.
Phosphorus is diffused into regions 201 and 203.

[Embodiment 4] This embodiment shows an example in which nickel is introduced by ion implantation in the manufacturing process shown in Embodiment 1.

In this case, in the step shown in FIG. 1D, the ionized nickel is accelerated and implanted.
The exposed region of the active layer is doped with nickel. The rest is the same as the manufacturing process shown in the first embodiment.

[Embodiment 5] This embodiment shows an example of a semiconductor device using the TFT shown in this specification.

FIG. 3A shows a portable information processing terminal. This information processing terminal includes an active matrix type liquid crystal display or an active matrix type EL display in a main body 2001, and further includes a camera unit 2002 for taking in information from outside.

The camera unit 2002 includes an image receiving unit 2003 and operation switches 2004.

It is considered that the information processing terminal will become thinner and lighter in order to improve its portability.

In such a configuration, it is preferable that the peripheral drive circuit, the arithmetic circuit, and the memory circuit on the substrate on which the active matrix type display 2005 is formed be integrated with TFTs.

FIG. 3B shows a head mounted display. This device includes an active matrix type liquid crystal display and an EL display 2102 in a main body 2101. The main body 2101 can be attached to the head with a band 2103.

FIG. 3C shows a car navigation system. This device has a main body 2201 provided with a liquid crystal display device 2202 and operation switches 2203, and an antenna 2
It has a function of displaying geographic information and the like according to the signal received at 204.

FIG. 3D shows a mobile phone.
This device includes an active matrix type liquid crystal display device 2304, operation switches 2305, a sound input portion 2303, a sound output portion 2302, and an antenna 2306 in a main body 2301.
It has.

Recently, a configuration in which a portable information processing terminal shown in (A) and a mobile phone shown in (D) are combined has been commercialized. Even in such a configuration, a configuration in which an active matrix type display and other circuits are integrated with TFTs on the same substrate is useful.

FIG. 3E shows a portable video camera. This is because the main body 2401 has an image receiving unit 2406,
An audio input unit 2403, operation switches 2404, an active matrix liquid crystal display 2402, and a battery 2405 are provided.

FIG. 3F shows a projection type liquid crystal display device. In this configuration, a light source 2502 and an active matrix type liquid crystal display device 2
503, an optical system 2504, and a function of displaying an image on a screen 2505 arranged outside the apparatus.

Here, as the liquid crystal display device, either a transmission type or a reflection type can be used.

In the devices shown in (A) to (E), an active matrix type display using EL elements can be used instead of the liquid crystal display device.

A TFT utilizing the invention disclosed in this specification
Can suppress variations in characteristics when a large number of TFTs are manufactured.
This is suitable for a configuration requiring a circuit.

[Embodiment 6] This embodiment shows an example in which a structure in which a P-channel TFT and an N-channel TFT are combined in a complementary manner is provided.

FIGS. 4 and 5 show the manufacturing process of this embodiment. First, an amorphous silicon film is formed on a glass substrate 301, and the amorphous silicon film is subjected to panning to form patterns 302 and 303 shown in FIG.

Here, reference numeral 402 denotes an active layer of a P-channel TFT, and reference numeral 403 denotes an active layer of an N-channel TFT.

Next, a silicon oxide film 304 serving as a gate insulating film
Is formed. Further, gate electrodes 405 and 406 are formed using molybdenum silicide. (FIG. 4 (A))

Next, according to the manufacturing steps shown in FIGS. 1B and 1C, sidewalls 407 and 408 made of silicon oxide are formed on the side surfaces of the gate electrode. (FIG. 4 (B))

Further, the exposed silicon oxide film 404 is removed by a dry etching method having vertical anisotropy. Thus, the state shown in FIG. 4C is obtained.

Here, 409 and 410 are the remaining silicon oxide films. The silicon oxide films 409 and 410 existing immediately below the gate electrodes 405 and 406 serve as gate insulating films.

Next, a nickel acetate solution was applied and
As shown by 1, a state is obtained in which the nickel element is held in contact with the surface. (FIG. 4 (D))

Next, by performing a heat treatment at 620 ° C. for 4 hours, crystal growth as indicated by 412 and 413 is performed. This crystal growth is performed by the active layer patterns 402 and 40
In 3, the region proceeds from the region where the nickel element is held in contact with the region below the region where the gate electrode and the sidewall are formed. (FIG. 4 (D))

A crystal grain boundary 400 is formed at a portion where the tip of crystal growth collides.

Next, the nickel element adhering to the surface is removed by washing. Then, doping of phosphorus is performed by a plasma doping method.

Thus, the state shown in FIG. 4E is obtained.
Here, the regions 414, 416, 417, and 419 are doped with phosphorus. Also, doping is not performed in the regions 415 and 418.

Next, at a temperature of 600 ° C. and 2
Perform heat treatment for a time. In this step, FIG.
The movement of the nickel element takes place along the paths indicated by arrows 501 and 502.

That is, the nickel element existing at 415 in FIG. 4E is gettered in the regions 414 and 416. The nickel element present at 418 in FIG. 4E is gettered in regions 417 and 419.

Next, a region to be an N-channel TFT is covered with a resist mask 503, and boron is doped. Here, boron doping is performed under conditions that cancel out the influence of the phosphorus that has been doped earlier. Generally, FIG.
It is necessary to perform boron doping at a dose higher than the phosphorus doping in the above.

In this way, the regions 504 and 505 are doped with boron, and a region is formed which is strongly influenced by boron to determine the conductivity type. That is, the P-type region 504,
505 is formed. (Accurately, the conductivity type becomes clear after activation)

The region 415 is not doped.

Next, the resist mask 503 is removed. Then, laser light irradiation is performed to anneal the active layer portion damaged in the doping process and activate the dopant.

Next, a silicon nitride film 506 is formed as an interlayer insulating film. Further, an acrylic resin film 507 is formed. Then, a contact hole is formed, and a P-channel type TF
A source electrode 508 and a drain electrode 509 of T are formed. Further, a source electrode 510 and a drain electrode 509 of the N-channel TFT are formed.

Thus, the P-channel type T shown in FIG.
TF in which FT and N-channel type TFT are configured to be complementary
Complete the T circuit.

The regions denoted by 511, 512, 513, and 514 are offset regions (high-resistance regions) provided adjacent to the channel regions 515 and 516. This offset region is formed in a self-aligned manner by the sidewall 407 shown in FIG.

The structure shown in FIG. 5C is a shift register circuit, a buffer circuit, and other circuits which form the basis of an integrated circuit.

[Embodiment 7] This embodiment is an example in which a P-channel TFT is manufactured based on the manufacturing process shown in Embodiment 1.

In the present embodiment, the steps up to the step shown in FIG. 2B are the same as the manufacturing steps shown in the first embodiment.

When the state shown in FIG. 2B is obtained, boron doping is performed. At this time, boron is doped with a dose higher than the dose of phosphorus doped earlier.

That is, phosphorus is doped into the N ⁺ -type region by doping with boron to the extent that its conductivity type is inverted, and the region is inverted to a P ⁺ -type or P ⁺⁺ -type region.

In this way, P-type source and drain regions containing phosphorus and gettering nickel can be formed.

Then, a P-channel type TFT can be manufactured.

[0113]

According to the invention disclosed in this specification, (1) crystallization by heat treatment is performed at a lower temperature than before. (2) The characteristics of the TFT can be made uniform by eliminating the influence of crystal grain boundaries. Can be solved.

[Brief description of the drawings]

FIG. 1 illustrates a manufacturing process of a TFT.

FIG. 2 is a diagram showing a manufacturing process of a TFT.

FIG. 3 is a diagram showing an example of an apparatus using a TFT.

FIG. 4 shows a P-channel type TFT and an N-channel type TF.
The figure which shows the example at the time of manufacturing simultaneously T.

FIG. 5 shows a P-channel type TFT and an N-channel type TF.
The figure which shows the example at the time of manufacturing simultaneously T.

[Explanation of symbols]

Reference Signs List 101 glass substrate 102 active layer 103 gate insulating film 104 gate electrode made of silicon 105 silicon oxide film 106 part where silicon oxide film remains 100 sidewall 107 made of silicon oxide 107 nickel element held in contact with surface 108 crystal growth collides Grain region 201 formed by doping 201 a region doped with phosphorus (source region) 202 a region not doped with phosphorus 203 a region doped with phosphorus (drain region) 204 a gettering path of phosphorus 205 silicon nitride film 206 acrylic Resin film 207 Source electrode 208 Drain electrode 209 Offset region (high resistance region) 210 Offset region (high resistance region) 211 Channel region

Claims (12)

[Claims] An active layer, a gate insulating film formed on the active layer, and a gate electrode formed on the gate insulating film, wherein a crystal grows from a source and a drain region in the active layer. The source and drain regions contain a higher concentration of a metal element that promotes silicon crystallization than the channel region. Semiconductor device. 2. An active layer, a gate insulating film formed on the active layer, and a gate electrode formed on the gate insulating film, wherein a crystal is grown from a source and a drain region in the active layer. The source and drain regions have thin film transistors in which a metal element that promotes crystallization of silicon is contained at a higher concentration than the channel region. Semiconductor device. 3. The semiconductor device according to claim 1, wherein nickel is used as a metal element for promoting crystallization of silicon. 4. The method according to claim 1, wherein the metal element for promoting crystallization of silicon is Fe, Co, Ni, or Ni.
Ru, Rh, Pd, Os, Ir, Pt, Cu, Au, G
A semiconductor device, wherein one or more elements selected from e, Pd, Pd, In, and Sb are used. 5. The crystal growth region according to claim 1, wherein the crystal-grown region has a structure in which a crystal grain boundary extends in a direction in which the crystal grows, and a crystal structure extends in a columnar shape in the direction. A semiconductor device. 6. A semiconductor device according to claim 1, wherein a crystal grain boundary is formed in a portion where a front end portion of the central crystal growth collides with the channel region. 7. A manufacturing process of a structure having an active layer, a gate insulating film formed on the active layer, and a gate electrode formed on the gate insulating film, wherein the structure comprises a source and a drain. Selectively introducing a metal element that promotes crystallization of silicon into the region; performing a heat treatment to grow crystal from the region serving as the source and the drain toward the region serving as a channel region; And a step of introducing phosphorus into a region serving as a drain, and a step of performing a heat treatment to move the metal element from the region serving as the channel region toward the region serving as the source and drain. A method for manufacturing a semiconductor device. 8. A manufacturing process of a structure having an active layer, a gate insulating film formed on the active layer, and a gate electrode formed on the gate insulating film, wherein the structure comprises a source and a drain. Removing the gate insulating film over the region; holding a metal element that promotes crystallization of silicon in contact with the region serving as the source and the drain; and performing a heat treatment to form a channel from the region serving as the source and the drain. A step of performing crystal growth toward a region to be a region, a step of introducing phosphorus into the region to be the source and the drain, and a step of performing a heat treatment from the region to be the channel region to the region to be the source and drain. Transferring the metal element by the method described above. 9. The method for manufacturing a semiconductor device according to claim 7, wherein nickel is used as a metal element for promoting crystallization of silicon. 10. The method according to claim 7, wherein Fe, Co, N is used as a metal element for promoting crystallization of silicon.
i, Ru, Rh, Pd, Os, Ir, Pt, Cu, A
A method for manufacturing a semiconductor device, wherein one or more elements selected from u, Ge, Pd, Pd, In, and Sb are used. 11. The method according to claim 7, wherein a direction axis of the crystal growth coincides with or substantially coincides with a direction axis of movement of the metal element from a region serving as a channel region toward a region serving as a source and a drain. A method for manufacturing a semiconductor device. 12. The method according to claim 7, wherein the metal element is moved from a region to be a channel region to a region to be a source and a drain.
A method for manufacturing a semiconductor device, wherein the metal element is gettered to source and drain regions.