JPH118351A - Semiconductor device and mounting method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the electrostatic protection ability with a min. occupied area by providing electrostatic protective pads shorted to the substrate of a semiconductor chip on this chip, having terminal pads for connecting outer lead wires. SOLUTION: Electrostatic protective pads 1 shorted to a substrate of a semiconductor chip are disposed on this chip, having terminal pads 2 for connecting outer lead wires and located at the corners of a chip 3. Since the chip 3 is generally rectangular planar, the protective pads 1 are disposed at its four corners. To the normal terminal pads 2, elements for protecting internal circuit elements electrically connected to the pads 2 are connected through Al wirings. The one of the protective elements connected to one pad 2 is for the substrate, and the other is for the power source.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an electrostatic discharge protection element for a semiconductor integrated circuit and a technique for mounting the same.

[0002]

2. Description of the Related Art As a countermeasure for electrostatic protection of a semiconductor integrated circuit,
2. Description of the Related Art A method of forming an electrostatic discharge protection element having a pair of two diodes for a substrate and a power supply in a semiconductor chip has been widely known. In this case, the electrostatic breakdown protection element (hereinafter, referred to as a protection element) has a size having a sufficient electrostatic resistance and is connected to all terminal pads of the semiconductor chip.

As a specific example of this type of protection element, for example, a high-concentration N-type buried layer is formed on a P-type semiconductor substrate, and a junction between the high-concentration N-type buried layer and the P-type semiconductor substrate is formed. In many cases, the first diode made of is used as a protection element for the substrate. For a power supply, for example, a high-concentration N-type buried layer is formed in a P-type semiconductor substrate, and an N-type epitaxial layer is grown thereon. A collector-base indirect transistor formed by forming an insulating separation layer reaching the P-type semiconductor substrate between the first semiconductor and the P-type diffusion layer and the N-type diffusion layer on the N-type epitaxial layer. In many cases, the second diode composed of the two is used as a protection element for the power supply.

[0004] Incidentally, since the protection element needs to have a size having a sufficient electrostatic resistance, the ratio of the protection element to the chip area increases as the degree of integration increases. For this reason, this protection element is one obstacle in achieving high integration.

To solve this problem, Japanese Patent Laid-Open No.
A technique disclosed in Japanese Patent Publication No. 299855 has been proposed. In this technique, as described above, the diode occupation area of the diode with respect to the chip area is reduced by forming the ESD protection diode of the power supply and the ESD protection substrate, which are formed independently of each other, in the same region. This is to improve the degree of integration of a semiconductor integrated circuit.

[0006]

FIG. 4 is a schematic diagram of a chip corner portion of an arrangement example of a conventional electrostatic discharge protection element (diode). With the progress of the semiconductor integrated circuit assembly technology, the size of the normal terminal pad 2 provided on the chip 3 is
It is getting very small. In addition, miniaturization of internal circuit elements has progressed, and the area occupied by the internal circuit elements has been reduced. This means that the area occupied by the terminal pad 2 is relatively smaller than that of the protection element 4. Reference numeral 5 denotes an aluminum wiring connecting the terminal pad 2 and the protection element 4.

In the technique described in Japanese Patent Application Laid-Open No. Hei 4-299855, the area occupied by the diodes is reduced by forming two types of diodes in the same region. Requires a sufficient area. Therefore, there is a limit in reducing the area of the diode itself in relation to the overvoltage. For this reason, the ratio of the area of the protection element to the whole chip increases,
There is a fundamental problem that the chip size cannot be reduced.

The present invention has been made in view of the above points, and provides a semiconductor device having an electrostatic protection element having a high electrostatic protection capability with a minimum occupation area, thereby improving the degree of integration. The purpose is to be able to achieve. Another object of the present invention is to provide a method of mounting a semiconductor device which can function extremely effectively as a measure against electrostatic protection when mounting the semiconductor device.

[0009]

In order to solve the above-mentioned problems, the present invention provides a semiconductor chip having a plurality of terminal pads for connecting to an external lead wire, the semiconductor chip having a short circuit with the substrate of the semiconductor chip itself. Pads are arranged. In that case, it is also very suitable to place the pad for electrostatic protection at the corner of the semiconductor chip. Further, when the semiconductor chip has a flat rectangular shape, pads for electrostatic protection can be arranged at the four corners. Further, the substrate of the semiconductor chip may be a silicon-based semiconductor substrate. Further, the semiconductor chip may be configured to include an electrostatic discharge protection element connected to the terminal pad. On the other hand, the mounting method of the present invention is a method for protecting internal elements of a semiconductor chip from static electricity charged on the substrate when the semiconductor chip is mounted on the substrate by a mounting apparatus, wherein the semiconductor chip is mounted on the substrate. A pad for electrostatic protection that is short-circuited with the substrate of the semiconductor chip itself is provided at a portion where the semiconductor chip itself comes into contact, and discharge is performed from the substrate of the semiconductor chip itself to the mounting device via the pad. In that case, it is very preferable to place the pad for electrostatic protection at a corner of the semiconductor chip. Further, a glass substrate can be used as a substrate on which the semiconductor chip is mounted. In addition, the pads for electrostatic protection can be provided in addition to the usual terminal pads required for connecting the semiconductor chip to the external leads. Further, the semiconductor chip may be provided with an electrostatic discharge protection element connected to the terminal pad.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to FIGS. FIG. 1 is a schematic plan view of a semiconductor device according to the present embodiment, FIG. 2 is a schematic diagram of a semiconductor chip corner portion, and FIG. 3 is a cross-sectional view showing a pad portion short-circuited to a substrate.

In the semiconductor device according to the present embodiment, an electrostatic protection pad short-circuited to a substrate 13 of the semiconductor chip 3 itself is provided on a semiconductor chip 3 having a normal terminal pad 2 for connection to an external lead wire. 1 is provided.

The pad 1 for electrostatic protection is located at a corner of the semiconductor chip 3 for the reason described later. Therefore, since the semiconductor chip 3 is generally rectangular in a plane,
Pads 1 for electrostatic protection are arranged at the four corners.

An ordinary terminal pad 2 has an internal circuit element (not shown) electrically connected to the terminal pad 2.
Are connected via an aluminum wiring 5. One of the protection elements 4 and 4 connected to one pad 2 is for a substrate, and the other is for a power supply.

An electrostatic protection pad 1 short-circuited to a substrate.
As shown in FIG. 3, the semiconductor substrate 13 of the chip 3 itself is provided with an impurity diffusion layer 12 of the same type as the semiconductor substrate 13 (P-type in the case of a P-type semiconductor substrate). By providing the wiring layer 10, the semiconductor substrate 13
Is formed. Reference numeral 11 denotes a field oxide film functioning as an insulating layer.

The substrate of the semiconductor chip 3 itself for providing the pads 1 is a well-known silicon-based semiconductor substrate. Of course, it may be another semiconductor substrate, or may be an N-type or P-type semiconductor substrate. . In other words, the present invention can be applied to almost any semiconductor chip that requires an electrostatic protection measure.

By the way, the semiconductor device provided with the pad 1 short-circuited to the semiconductor substrate 13 is, for example, C
hip On Glass product (hereinafter referred to as COG product)
In the case of a semiconductor device applied to a semiconductor device, wiring connected to the outside of the semiconductor device is provided on a glass substrate, and the surface of the semiconductor device is bonded to the glass substrate. At this time, the application of static electricity is most affected.

When the semiconductor device is mounted on the glass substrate, the corner of the chip of the semiconductor device comes into contact with the glass substrate first. Therefore, the static electricity charged on the glass substrate is transferred to the chip 3 before the normal terminal pad 2 of the semiconductor device.
Is applied to the pad 1 which is short-circuited with the semiconductor substrate 13 disposed at the corner, and can escape from the semiconductor substrate 13 to the mounting device side. That is, since the mounting apparatus normally mounts the semiconductor substrate while holding it, by short-circuiting the pad 1 to the semiconductor substrate, it becomes possible to ground the mounting apparatus from the semiconductor substrate.

As a result, the static electricity charged on the glass substrate can be reduced, and the static electricity applied to each terminal pad 2 can be reduced accordingly. Therefore, the area of the protection element 4 (diode) against static electricity can be substantially reduced or eliminated.
As a result, the problem of the protection element 4 which has been an obstacle to high integration can be fundamentally solved, and the degree of integration can be significantly improved.

After mounting on a glass substrate, a process of sealing the glass substrate and the semiconductor device with a resin is usually performed, so that static electricity is not directly applied to each terminal pad 2 of the semiconductor device.

Further, when the number of terminal pads of the semiconductor device is large, the conventional protection element needs a sufficient area in relation to the electrostatic withstand capability. Therefore, the chip size is determined by the area of the protection element and the number of terminal pads. Would. However, if the area of the protection element 4 can be reduced as in the present embodiment, the interval between the terminal pads 2 can be reduced, and the size of the chip 3 can be reduced.

Therefore, even if the pads 1 for electrostatic protection which are short-circuited with the semiconductor substrate 13 are newly provided at the corners of the chip 3, the area of the protection element 4 connected to each terminal pad 2 can be reduced. Therefore, as compared with the conventional chip size, the influence on the chip size caused by newly disposing the pad 1 at the corner of the chip 3 is extremely small.

On the other hand, such COG mounting often requires a dummy pad for electrostatic protection. In this case, if the dummy pad is a pad that is short-circuited to the semiconductor substrate as described in the present embodiment, the chip size is not affected at all, and the chip size can be made smaller than in the past.

This will be described with reference to FIGS. 2 and 4. In FIG. 4, for example, one side of the pad 2 is 50 μm.
m, the side parallel to the chip end of the protection element 4 is 60 μm, and the distance between the protection element 4 and the pad 2 is 20 μm, the length occupied by one pad 2 including the protection element 4 is 210 μm. Here, when the present invention is applied, as shown in FIG. 2, assuming that the side parallel to the chip end of the protection element 4 can be 40 μm, the length occupied by one pad 2 including the protection element 4 is: 170 μm.

Therefore, by applying the present invention, the length occupied by one pad 2 including the protection element 4 can be reduced by 20%. Therefore, even if the substrate of the present invention and the pad 1 as a show are arranged at the corners of the chip 3, the length of each side can be reduced by about 20%, and the degree of integration of the entire chip can be improved.

In the description of the mounting method in the embodiment, the case of COG mounting has been described as an example. However, the substrate on which the semiconductor device is mounted is made of another material that requires countermeasures against static electricity, like the glass substrate. Of course, the present invention can be applied to a substrate. In addition, the short-circuited pad is not limited to the corner of the chip. It may be provided.

[0026]

As described above, according to the present invention, a semiconductor chip is provided with an electrostatic protection pad short-circuited to a substrate. The area occupied in the chip can be reduced or eliminated. By reducing the occupied area, the degree of integration of the semiconductor integrated circuit can be improved. Further, by arranging the pad that is short-circuited to the substrate at a position where the semiconductor chip first comes into contact with the substrate, it is possible to function extremely effectively as a measure for protecting the semiconductor device from static electricity during mounting.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a chip corner portion of the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view of a pad portion short-circuited to a substrate of the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a schematic diagram of a chip corner portion showing an example of a conventional protection element arrangement.

[Explanation of symbols]

 Reference Signs List 1 pad short-circuited to substrate 2 normal terminal pad 3 chip (semiconductor chip) 4 protective element (diode) 5 aluminum wiring 10 wiring layer (pad) 11 field oxide film 12 impurity diffusion layer of same type as substrate 13 semiconductor substrate

Claims (10)

[Claims] 1. A semiconductor device comprising: a semiconductor chip having a plurality of terminal pads for connecting to an external lead wire; and an electrostatic protection pad short-circuited to a substrate of the semiconductor chip itself. . 2. The semiconductor device according to claim 1, wherein said pad for electrostatic protection is located at a corner of a semiconductor chip. 3. The semiconductor chip has a planar rectangular shape,
The semiconductor device according to claim 1, wherein the pads for electrostatic protection are arranged at four corners of the semiconductor device. 4. The semiconductor device according to claim 1, wherein said substrate is a silicon-based semiconductor substrate. 5. The semiconductor device according to claim 1, wherein said semiconductor chip includes an electrostatic discharge protection element connected to said terminal pad. 6. A method for protecting an internal element of a semiconductor chip from static electricity charged on the substrate when the semiconductor chip is mounted on the substrate by a mounting device, wherein the semiconductor chip first contacts the substrate. A pad for electrostatic protection short-circuited to the substrate of the semiconductor chip itself, and discharging from the substrate of the semiconductor chip itself to the mounting device via the pad. 7. The semiconductor device according to claim 6, wherein said pad for electrostatic protection is located at a corner of a semiconductor chip. 8. The method according to claim 6, wherein the substrate on which the semiconductor chip is mounted is a glass substrate. 9. The semiconductor device according to claim 6, wherein said pad for electrostatic protection is provided in addition to a normal terminal pad necessary for connecting a semiconductor chip to an external lead.
3. The method for mounting a semiconductor device according to claim 1. 10. The method according to claim 6, wherein the semiconductor chip includes an electrostatic discharge protection element connected to the terminal pad.