JPH118298A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce scratches by providing a stopper film in a laminated structure that sandwiches, for example, an oxide film on an element formation region as a structure at planarizing. SOLUTION: A first deposited film 33, a second silicon oxide film 34, and a second deposited film 35 constitute a stopper film 3. Then, the second deposition film 35, the second silicon oxide film 34, and the first deposition film 33, the first silicon oxide film 2, and a semiconductor substrate 1 are successively etched, and a groove 5 where a bottom part reaches the inside of the semiconductor substrate 1 is formed. At that time, the depth of the groove 5 is set so that the breakdown voltage among wells becomes sufficiently large electrically, when an embedded element separation region is formed, and the stopper film 3 is a film for protecting the element formation region when flattening the irregularities of an embedded material, thus preventing damages due to scratches which are generated on the semiconductor substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for flattening a semiconductor device having a buried element isolation region.

[0002]

2. Description of the Related Art Semiconductor devices such as ICs and LSIs are manufactured through a design process, a mask making process, a wafer manufacturing process, a wafer processing process, an assembly process, an inspection process, and the like. Conventionally, as a method of embedding an arbitrary material such as metal, polysilicon, silicon oxide film (SiO ₂ ) in a trench such as a contact hole in a wafer processing step, and then flattening the surface thereof, etch back RIE (Reactiv) is used.
e Ion Etching) method is known, but this etch back RIE method requires many steps such as application of an etch back resist, that RIE damage easily occurs on the wafer surface, that good planarization is difficult, In addition, since a vacuum system is used, the structure is complicated and there are various problems such as the use of a dangerous etching gas. Therefore, recently, a chemical mechanical polishing (hereinafter, referred to as CMP (Chemical Mechanical Polishing)) method has been used instead of the etch-back RIE. This CMP is
The polishing is performed by a polishing apparatus (hereinafter, referred to as a CMP apparatus). By using this CMP apparatus, for example, a silicon oxide film is buried, and polishing is stopped by a stopper film, whereby the surface can be completely planarized.

[0003]

A flattening process using a CMP device for a semiconductor device having a buried element isolation structure will be described with reference to FIGS.
The figures are a manufacturing process sectional view showing a structure necessary for forming a conventional buried element isolation region, and a sectional view showing a problem thereof. Conventionally, in order to realize a buried element isolation region, for example, a first silicon oxide film 2 is deposited as a protective film on the semiconductor substrate 1 to a thickness of about 20 nm, and then a first silicon oxide film 2 is formed by a chemical vapor deposition method. Oxide film 2
A polycrystalline silicon film 3 is deposited to a thickness of about 300 nm. Subsequently, a second silicon oxide film 4 is deposited to a thickness of about 300 nm on the polycrystalline silicon film 3 by the same chemical vapor deposition method. At this time, the polycrystalline silicon film 3 is used as a stopper material when flattening is performed thereafter (FIG. 14A). After that, a photoresist (not shown) is formed by combining photolithography and anisotropic etching, and the second silicon oxide film 4 is etched into a predetermined shape. Using the silicon oxide film 4 as a mask, the polycrystalline silicon film 3, the first silicon oxide film 2, and the semiconductor substrate 1 are sequentially etched to form a groove 5 in the semiconductor substrate 1. At this time, the depth of the groove 5 is
When the buried element isolation region is formed, it is set so that the withstand voltage between the wells is sufficiently high.

After the second silicon oxide film 4 is further removed, a material T for filling the trench 5 is formed by chemical vapor deposition.
Insulating film such as EOS / O ₃ film (third silicon oxide film)
6 is deposited to a thickness of about 1000 nm (FIG. 14B). Thereafter, the third silicon oxide film 6 is chemically and mechanically polished (Ch
The surface is planarized using emical mechanical polishing (hereinafter referred to as CMP). The polycrystalline silicon film 3, which is a stopper material for CMP, is removed by an isotropic etching method or the like using the first silicon oxide film 2 as a protective film.
In order to stabilize the removal of the polycrystalline silicon film 3, the silicon oxide film formed on the surface of the polycrystalline silicon film 3 is removed in advance using a diluted hydrogen fluoride aqueous solution or the like. By the way, when the buried element isolation region formed by such a method is flattened by CMP, the slurry as the polishing agent causes the polycrystalline silicon film 3 as the stopper material to be deeply scratched, thereby causing a scratch. (Fig. 15
(A)). If the scratches are deep enough to reach the semiconductor substrate 1 or the first silicon oxide film 2, they develop into scratches 7 that cause the semiconductor substrate 1 to be lost in the subsequent step of removing the polycrystalline silicon film 3. (FIG. 15
(B)).

[0005] The transistor formed in the flawed region becomes a defective element, and causes problems such as causing a bit defect later. Further, it is known that the scratches generated at the time of CMP are reduced by hardening the embedding material. As a method of hardening the embedding material, for example, a high-temperature heating process at 700 ° C. is performed before the CMP. It is known that the occurrence thereof is reduced by applying the method to a filling material (silicon oxide film) which is a polishing film. However, if the embedding material is cured at the stage of FIG. 14B before performing the CMP process, there is a problem that cracks are formed in the wafer due to volume shrinkage of the entire embedding material, thereby deteriorating element characteristics. The present invention has been made under such circumstances,
Provided is a method for manufacturing a semiconductor device with less occurrence of scratches in a method of flattening the surface of a buried material such as a TEOS film by using P.

[0006]

SUMMARY OF THE INVENTION The present invention is directed to a semiconductor device having a buried element isolation region, which has a stacked structure in which an oxide film or the like is interposed on an element formation region as a structure for planarization by a CMP method. It is to provide a film. That is, the method for manufacturing a semiconductor device according to the present invention includes:
Forming an oxide film on the semiconductor substrate, forming a planarization stopper film on the oxide film, etching the planarization stopper film, the oxide film and the semiconductor substrate to form a groove in the semiconductor substrate. Forming an insulating film on the semiconductor substrate so as to fill the groove, and flattening the surface of the insulating film by chemical mechanical polishing. The stopper film is characterized by having a laminated structure of a plurality of layers made of different materials. By forming the stopper film in a laminated structure in this manner, it is possible to prevent scratches generated at the time of CMP with the oxide film or the like and prevent the surface of the element formation region from being damaged by the scratches.

Further, according to the present invention, there is provided a method of flattening an embedding material such as a TEOS / O ₃ film, wherein the embedding material is once flattened to the extent that the embedding material remains on the stopper film to reduce the volume of the embedding material. After the above-described heat treatment at a high temperature is performed to cure the embedding material, C
This is to perform planarization by MP. That is, in the method of manufacturing a semiconductor device according to the present invention, a step of forming an oxide film on a semiconductor substrate, a step of forming a first planarization stopper film on the oxide film, a step of forming the first planarization stopper film, Forming a groove in the semiconductor substrate by etching the oxide film and the semiconductor substrate; forming an insulating film on the semiconductor substrate so as to fill the groove; Flattening the insulating film to reduce the volume of the insulating film, heat-treating the semiconductor substrate at a high temperature of 700 ° C. or higher after performing the first planarization, And a step of performing second planarization by chemical mechanical polishing until the first planarization stopper film is exposed. In this method, the occurrence of scratches can be reduced by heat-treating the filling material during flattening.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. First, an embodiment of the first invention will be described with reference to FIGS. The figure is a cross-sectional view of the manufacturing process of the semiconductor device. The embodiment of the present invention is characterized in that a stopper film used for flattening has a laminated structure. First, for example, a first silicon oxide film 2 having a thickness of about 20 nm is deposited as a protective film on a semiconductor substrate 1 such as a P-type silicon semiconductor. Next, a first deposited film 33 is deposited by T1 [nm] using a chemical vapor deposition method or the like. The first deposited film 33 may be any film as long as the film has a sufficiently high selectivity to the filling material, such as a polycrystalline silicon film, a silicon nitride film, a metal film containing silicon,
Examples include a titanium nitride (TiN) film, a conductive film of carbon or a metal containing carbon, a tungsten (W) film, and the like.

After that, a second silicon oxide film 34 is formed on the first deposited film 33 by using a chemical vapor deposition method or the like.
m]. The second silicon oxide film 34 is formed of C
During the planarization process using MP, the slurry that is the abrasive
Is a stopper film for preventing the deposited film 33 from being damaged. Thereafter, in order to further improve the stopper performance of the scratch, heat treatment is performed at a high temperature of, for example, 600 ° C. or more in a nitrogen atmosphere or an oxygen atmosphere. However, in the present invention, such a heat treatment is not an essential component. Subsequently, a second deposition film 35 is deposited on the second silicon oxide film 34 by using a chemical vapor deposition method or the like by about T2 [nm] (FIG. 1A). Here, like the first deposited film 33, the second deposited film 35 may be any film as long as the film has a sufficiently high selection ratio with respect to the filling material. For example, a polycrystalline silicon film, a silicon nitride film, a silicon , A titanium nitride (TiN) film, a conductive film of carbon or a metal containing carbon, a tungsten film, and the like. The stacked first deposited film 33, second silicon oxide film 34 and second deposited film 35 constitute the stopper film 3.

Next, by combining photolithography and anisotropic etching, etc., a second deposited film 35 and a second silicon oxide are sequentially formed into a predetermined shape using a patterned photoresist (not shown). Film 34, first deposited film 3
3. Etching the first silicon oxide film 2 and the semiconductor substrate 1 to form a groove 5 whose bottom reaches inside the semiconductor substrate 1 (FIG. 1B). At this time, the depth of the groove 5 is set such that the withstand voltage between the wells is sufficiently high when the buried element isolation region is formed. The stopper film 3 is a film that protects the element formation region when the unevenness of the filling material is flattened, and the combination of the first deposited film 33 and the second deposited film 35 is free. That is, in the present invention, the same film may be selected for each, and films of different materials may be selected. Then, after removing the photoresist,
Using a chemical vapor deposition method, an insulating film 6 serving as a filling material is deposited to such an extent that the groove 5 is completely filled (FIG. 2A). As the filling material 6, for example, a TEOS / O ₃ film, which is a silicon oxide film formed in an ozone atmosphere, is used. TEO
The S film is made of an organic oxysilane Si (OC ₂ H ₅ ) ₄ of 60.
It is obtained by pyrolysis at 0 ° C to 900 ° C. This raw material is liquid at room temperature, is heated and evaporated at about 30 ° C., and is led to a reactor together with a carrier gas.

[0011] Then, from normal pressure to reduced pressure CVD (Chemical Vapo)
ur deposition) method, a uniform film is formed. This film can relatively secure mass productivity. After that, the filling material 6 is flattened by the CMP method. At this time, the slurry, which is a polishing agent for CMP, may scratch the stopper film 3, but the scratch stops at the second silicon oxide film 34 existing between the first deposited film 33 and the second deposited film 35. The semiconductor substrate 1 or the first silicon oxide film 2 is not scratched (FIG. 2B). Here, in order to minimize scratches, the slurry should be as small as possible (1
μm or less) is desirable. The thickness T1 of the first deposited layer 33 is set to increase the margin in the CMP process and to reduce the level difference after the stopper film 3 is peeled off.
[Nm] and the thickness T2 [nm] of the second deposited film 35 are preferably set so as to maintain the following relational expression (1). T1 ≦ T2 (1) Subsequently, the stopper film 3 having a laminated structure, which is a stopper material for CMP, is removed by an isotropic etching method or the like using the silicon oxide film 2 as a protective film. Here, the first silicon oxide film 2 forms the semiconductor substrate 1 when the stopper film 3 is peeled off.
Needless to say, the film thickness is sufficient to protect the film.

When the first and second deposited films 33 and 35 are removed by isotropic etching or the like, it is preferable that the first and second deposited films 33 and 35 have an etching selectivity with respect to the second silicon oxide film 34. Specifically, for example, the etching rate of the second deposited film 35 is α [nm / min], the film thickness is T 2,
The etching rate of the silicon oxide film 34 is β [nm /
min], the thickness T of the second silicon oxide film 34
ox [nm] is preferably set so as to maintain the following relational expression (2). Tox> β · T 2 / α (2) In the semiconductor device formed in this way, even if a scratch is made by the CMP process, the semiconductor device stops at the second silicon oxide film 34, so that the stopper film 3 is removed at the same time. The scratch is removed, and as a result, a good buried element isolation region having no defect in the semiconductor substrate 1 is formed.
(A)). Then, the semiconductor substrate 1 is provided with
Annealing is performed in a nitrogen atmosphere at about 00 ° C. to harden the filling material. Next, a MOS transistor with few defects is formed in the element region of the semiconductor substrate 1 in which the element isolation region made of the filling material 6 is formed. That is, an N-type source / drain region 8 is formed in the element region, and the source / drain region 8 is formed.
A gate electrode 9 made of polycrystalline silicon or the like is formed on the drain region 8 via the gate oxide film 2 (FIG. 3B).

Next, an embodiment of the second invention will be described with reference to FIGS. Each of the drawings is a cross-sectional view showing a manufacturing process of the semiconductor device. The embodiment of the present invention is characterized in that the stopper film has a laminated structure and that the stopper film is made of polycrystalline silicon. First, for example, a first silicon oxide film 2 having a thickness of about 20 nm is deposited as a protective film on the semiconductor substrate 1. Next, a first polycrystalline silicon film 33 is deposited to a thickness of about 100 nm using a chemical vapor deposition method. Thereafter, the first polycrystalline silicon film 33 is oxidized in an oxygen atmosphere, and a second silicon oxide film 34 is deposited on the surface of the first polycrystalline silicon film 33 to a thickness of about 20 nm. At this time, the second silicon oxide film 34 may be deposited by using a chemical vapor deposition method. If the second silicon oxide film 34 is deposited by using a chemical vapor deposition method, the second silicon oxide film is cured (shrinkage in volume) in order to cure the second silicon oxide film.
For example, heat treatment is performed at a high temperature of 600 ° C. or more in a nitrogen atmosphere or an oxygen atmosphere. Next, a second polycrystalline silicon film 35 is deposited on the second silicon oxide film 34 to a thickness of about 200 nm using a chemical vapor deposition method or the like (FIG. 4).
(A)).

Next, a patterned photoresist (not shown) is formed by combining photolithography and anisotropic etching and the like, and the second polysilicon film 35 and the second polysilicon film 35 are sequentially formed into a predetermined shape. The silicon oxide film 34, the first polycrystalline silicon film 33, the first silicon oxide film 2, and the semiconductor substrate 1 are etched to form a groove 5 having a bottom surface provided in the semiconductor substrate 1 (FIG. 4B). ). Here, the depth of the groove 5 is set so as to have a sufficient withstand voltage between the wells when the buried element isolation region is formed. Although not shown, after depositing the second polycrystalline silicon film 35,
Further, a silicon oxide film is formed by a chemical vapor
After the silicon oxide film is etched by photolithography and anisotropic etching and the like, and the photoresist is removed, the silicon oxide film is used as a mask to form a second shape in order by anisotropic etching and the like. Polycrystalline silicon film 35,
Second silicon oxide film 34, first polycrystalline silicon film 3
3. The groove 5 may be formed by etching the first silicon oxide film 2 and the semiconductor substrate 1. In this manner, the stopper film 3 having a laminated structure including the first polycrystalline silicon film 33, the second silicon oxide film 34, and the second polycrystalline silicon film 35 is formed. The stopper film 3 is a film that protects the element formation region when the unevenness is flattened. Subsequently, after removing a photoresist or a silicon oxide film (not shown) as a mask material, a third silicon oxide film 6 as a filling material is removed by a chemical vapor deposition method so that the trench 5 is sufficiently filled. It is deposited (FIG. 5A).

Thereafter, the structure is planarized by using the CMP method. At this time, slurry serving as a polishing agent for CMP may damage the stopper film 3, but the second silicon oxide film 34 existing between the first polycrystalline silicon film 33 and the second polycrystalline silicon film 35 may cause the stopper film 3. The scratch stops and the semiconductor substrate 1 or the first silicon oxide film 2 can be prevented from being scratched (FIG. 5B). Here, in order to minimize scratches, it is desirable that the slurry has as small a grain size as possible (1 μm or less). continue,
Stopper film 3 of laminated structure which is a stopper material for CMP
Is to be removed by isotropic etching or the like using the silicon oxide film 2 as a protective film. However, in order to stabilize the peeling of the second polycrystalline silicon film 35, the second Preferably, the silicon oxide film formed on the surface of the second polycrystalline silicon film 35 is removed in advance.

The semiconductor device thus formed has a C
Scratch second even if scratched during MP
Since the stopper stops at the silicon oxide film 34, the scratch is removed at the same time as the stopper film 3 is removed. As a result, a good buried element isolation without a defect in the semiconductor substrate 1 is formed (FIG. 6). Then, the semiconductor substrate 1 is annealed to the semiconductor substrate 1 at about 1000 ° C. to 1200 ° C. in a nitrogen atmosphere to cure the filling material. A MOS transistor having an N-type source / drain region 8, a gate oxide film 2, and a gate electrode 9 is formed in the element region of the semiconductor substrate 1 (see FIG. 3B). Next, FIGS.
An embodiment of the third invention will be described with reference to FIG. Each of the drawings is a cross-sectional view showing a manufacturing process of the semiconductor device. The embodiment of the present invention is characterized in that the planarization is performed in two steps, and a high-temperature heating step is inserted between the two planarization steps.

First, for example, a first silicon oxide film 2 is deposited on the semiconductor substrate 1 as a protective film to a thickness of about 20 nm. Thereafter, the polycrystalline silicon film 3 is formed by using a chemical vapor deposition method.
Is deposited to a thickness of about 300 nm, and then a second silicon oxide film 4 is deposited to a thickness of about 300 nm using the same chemical vapor deposition method (FIG. 7A). This polycrystalline silicon film 3
It is used as a first stopper film when flattening is performed thereafter. Here, the case where a polycrystalline silicon film is used has been described. However, the present invention is not limited to this polycrystalline silicon film, and the present invention is not limited to this polycrystalline silicon film. A film, a conductor film of a metal containing silicon, a titanium nitride (TiN) film, a conductor film of a metal containing carbon or carbon, a tungsten film, or the like can also be used. Also, the second silicon oxide film 4
Is used as a mask material when etching the polycrystalline silicon film 3, the first silicon oxide film 2, and the semiconductor substrate 1. Subsequently, the silicon oxide film 4 is etched into a predetermined shape using a patterned photoresist by combining photolithography and anisotropic etching or the like, and then the photoresist is removed. Thereafter, the polycrystalline silicon film 3, the first silicon oxide film 2, and the semiconductor substrate 1 are sequentially etched by anisotropic etching or the like using the second silicon oxide film 4 as a mask to provide a bottom surface in the semiconductor substrate 1. The groove 5 to be formed is formed (FIG. 7B). The depth of the groove 5 is set so that the withstand voltage between the wells is sufficiently high when the buried element isolation region is formed.

Next, after a third silicon oxide film 6 serving as an embedding material is deposited to a thickness of 1200 nm using a chemical vapor deposition method, the third silicon oxide film 6 deposited in the wide groove 51 formed in the semiconductor substrate 1 is deposited. On the oxide film 6, a carbon film 10 as a second stopper material is deposited. The second stopper film may be made of any material that can have a high selectivity with respect to the silicon oxide film when performing the CMP. For example, in addition to the carbon film, a polycrystalline silicon film, a silicon nitride film, a titanium nitride (TiN 8) a conductive film such as a metal containing carbon, a tungsten film and the like (FIG. 8).
(A)). After that, the structure is planarized to the surface of the second stopper film 10 using CMP or the like,
The carbon film 10 serving as the second stopper film is removed by a dry etching method including an oxygen atmosphere. In this case, it is desirable that the polishing is performed so that the polycrystalline silicon 3 serving as the first stopper film is not exposed. This is because, if the high-temperature heat treatment, which is the next step, is performed in a state where the first stopper film is exposed, the surrounding filling material shrinks in volume, and the first stopper film becomes a protruding convex shape. This is because if CMP is performed in this state, the slurry is likely to be caught on the protruding portions, thereby easily causing scratches.

Subsequently, for example, at 700 ° C. or more, 1000
Heat treatment at a temperature of not more than 10 ° C. (for example, 950 ° C.) for 10 minutes or more (up to about 60 minutes) in a nitrogen atmosphere or an oxygen atmosphere, preferably in a nitrogen atmosphere similar to the case where the filling material 6 is finally cured. 8 to make the embedding material 6 partially hardened and changed to the heat-treated embedding material 6 ′ so as to prevent scratching even when CMP is performed (FIG. 8).
(B)). In this method, since the volume of the filling material is reduced by flattening once, the volume shrinkage in the high-temperature heating step can be reduced. As a result, no enormous volume shrinkage occurs, so that cracks in the semiconductor substrate 1 can be suppressed. Thereafter, CMP is performed again until the polycrystalline silicon film 3 serving as the first stopper is exposed (FIG. 9A).
Here, since the filling material 6 'is partially cured, the polishing rate of the polycrystalline silicon film 3, which is the first stopper film, and the filling material 6' is reduced by CMP. As a result, the first
The unevenness of the polycrystalline silicon film 3 serving as the stopper film and the filling material 6 'is reduced, and the slurry is caught by the unevenness, and the possibility (probability) of generating scratches is reduced. Here, in order to minimize scratches, it is desirable that the slurry has as small a grain size as possible (1 μm or less).

Subsequently, the polycrystalline silicon film 3, which is a first stopper film of CMP, is removed by an isotropic etching method or the like using the silicon oxide film 2 as a protective film. Here, preferably, the silicon oxide film formed on the surface of the polycrystalline silicon film 3 is removed in advance using a diluted hydrogen fluoride aqueous solution in order to stabilize the peeling of the polycrystalline silicon film 3. Then, the semiconductor substrate 1 is heat-treated (annealed) at about 1000 ° C. to 1200 ° C. in a nitrogen atmosphere to finally cure the burying material 6 ′ as an element isolation region. The buried element isolation region formed by such a method reduces the possibility that the slurry as the polishing agent will deeply scratch the polycrystalline silicon film 3 as the stopper material when planarizing by the CMP. The scratch reaching the first silicon oxide film 2 and the semiconductor substrate 1 can be eliminated. Therefore, the step of removing the polycrystalline silicon film 3 serving as the first stopper film does not develop into a scratch that causes the semiconductor substrate 1 to be deficient, and finally a good buried element isolation region having no deficiency in the semiconductor substrate 1 is formed. (Fig. 9
(B)). The N-type source /
A MOS transistor including the drain region 8, the gate oxide film 2, and the gate electrode 9 is formed (FIG. 10).

Next, the CMP process will be described in comparison with a conventional example with reference to FIG. The figure is a flowchart showing the CMP in the method for manufacturing a semiconductor device. Conventionally, CMP is performed by dividing the CMP into two times, the stopper film is removed, and then the semiconductor substrate is heat-treated to harden the filling material. However, in the third embodiment, the CMP is performed between the first and second CMPs. Since a heat treatment step is inserted to slightly reduce the volume of the filling material, the occurrence of cracks is eliminated. For example, when forming an STI structure element isolation region in an SRAM or the like, a trench (groove) is dug in a silicon semiconductor substrate (wafer), and then a burying material T is formed.
The grooves are filled with an EOS / O ₃ film, and the CMP is performed twice to perform planarization. It has been found that the TEOS / O ₃ film changes its film quality (that is, hardens) when a densify (annealing) step is performed. Also, TEOS / O
_If densification is performed in a state where the _three films are deposited, a large amount of deposition causes a large amount of volume shrinkage, which causes a large crack in the semiconductor substrate. Therefore, TEOS /
O ₃ film is cut to some extent to reduce the volume.

At a certain point, a densify step is performed to make the CMP polishing rates of the TEOS / O ₃ film and the stopper film close to each other, and a second CMP is performed. Prevent the occurrence of cracks by carrying out the densification process when the volume was reduced scraping TEOS / O ₃ film in the first CMP, a and the TEOS / O ₃ film by the tightly TEOS / O ₃ film by densifying step Since the CMP polishing rate with the stopper film becomes close, TEOS /
The step at the interface between the O ₃ film and the stopper film can be reduced. For this reason, it is possible to reduce the possibility that the slurry serving as the abrasive is caught at the stepped portion, thereby preventing the occurrence of scratches. In the third embodiment, the second stopper film 10 is deposited when the wide groove portion 51 as shown in FIG. 7B is not particularly formed, for example, by providing a dummy element region. Instead, the first CMP may be performed while controlling so that the polycrystalline silicon film 3 serving as the first stopper film is not exposed. HV with excellent controllability during polishing
By using S (high-viscosity slurry), the second stopper film 10 is not deposited again, and for example, the concave portion of the filling material 6 above the polycrystalline silicon film 3 is directly subjected to the first C
It is possible to selectively remove with MP.

In the present invention, the polycrystalline silicon film 3
Alternatively, a carbon film can be used. The carbon film as a stopper film used when polishing the silicon oxide film can have a polishing rate ratio of 20 or more with respect to the silicon oxide film, and can stop etching by polishing at a desired position. . Moreover, metal contamination does not matter. The carbon film can be easily removed by burning it in an oxidizing atmosphere. This combustion can be performed simultaneously with the final heat treatment of the silicon oxide film. Next, referring to FIG.
The MP method will be described. The figure is an enlarged perspective view of a suction disk holding a semiconductor wafer and a polishing disk of a CMP apparatus. The CMP apparatus includes a polishing board 11. A drive shaft (not shown) is connected to the center of the polishing machine 11 via a polishing machine receiver (not shown). A polishing cloth 12 for polishing a semiconductor wafer is mounted on the polishing board 11. The polishing cloth 12 is made of foamed polyurethane or polyurethane nonwoven fabric. The drive shaft is rotated by a motor to rotate the polishing plate receiver and the polishing plate 11. The semiconductor wafer (not shown) is arranged at a position facing the polishing cloth 12, and is sucked on a suction plate 13 to which a suction cloth (not shown) is attached by vacuum suction or the like.

The suction disk 13 is connected to a drive shaft 14, and the semiconductor wafer held by the suction disk 13 is pressed against or separated from the polishing pad 12 by the movement of the drive shaft 14 to polish the semiconductor wafer. When polishing a semiconductor wafer, an abrasive (slurry) containing abrasive particles such as ceria (CeO ₂ ) and silica (SiO ₂ ) is supplied from the abrasive tank to the polishing cloth 12 via the abrasive supply pipe 15. Do. Therefore, the abrasive supply pipe 15 has a nozzle at the tip thereof disposed near the suction plate 13 that holds the semiconductor wafer above the polishing cloth 12,
An abrasive is injected into a processing point of the polishing cloth 12. The abrasive supply pipe 15 is movable to an arbitrary position on the polishing cloth 12. Abrasive (slurry) is pH
Abrasive particles are uniformly dispersed in a solvent such as about 11 to 12 aqueous alkaline solution or pure water, and the abrasive particles are made of a material such as silicon nitride other than ceria and silica as described above.

The generation of the scratch is affected by the particle size of the abrasive particles contained in the slurry as described above. FIG.
FIG. 14 is a characteristic diagram showing a relationship between a slurry composed of abrasive particles having a predetermined particle diameter and the number of scratches generated on a wafer by performing CMP using the slurry in the manufacturing process shown in FIGS. 14 and 15. . The vertical axis indicates the number of scratches generated on the wafer [pieces / mm ² ], and the horizontal axis indicates the type of abrasive particles used in the slurry. As shown in the figure, when CMP is performed using a slurry using abrasive particles having a particle diameter of 0.7 μm or less or a slurry using abrasive particles having a particle diameter of 1.0 μm or less, scratches are less likely to occur, but the particle diameter is small. When CMP is performed with a slurry using abrasive particles exceeding 1.0 μm or abrasive particles whose particle diameter is not controlled, scratches become 0.66 [particles / mm].
² ] may also occur. That is, in the embodiment of the present invention, similarly to the conventional manufacturing process, performing CMP using a slurry having a particle diameter of 1.0 μm or less is effective in suppressing the occurrence of scratches.

[0026]

According to the present invention, a C
Even if a scratch occurs in the planarization process by MP, the scratch is stopped at the oxide film of a part of the stopper film having a laminated structure, so that the scratch is removed at the same time as passing through a subsequent step of peeling the stopper film, Finally, damage due to scratches generated in the semiconductor substrate can be prevented, and as a result, a buried element isolation region without damage can be formed on the semiconductor substrate. Also,
After a flattening process is performed to the extent that the filling material remains on the first stopper film in order to reduce the volume of the filling material,
Partial hardening of the burying material by applying a heating process at a temperature of not less than 00 ° C. and not more than 1000 ° C. has an effect of suppressing the above-described phenomenon of cracking the semiconductor substrate by using a process of cutting down to the first stopper film. Can be.

[Brief description of the drawings]

FIG. 1 is a sectional view of a manufacturing process of a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of the semiconductor device of the present invention.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of the semiconductor device of the present invention.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of the semiconductor device of the present invention.

FIG. 5 is a sectional view showing a manufacturing process of the semiconductor device of the present invention.

FIG. 6 is a sectional view showing a manufacturing process of the semiconductor device of the present invention.

FIG. 7 is a sectional view showing a manufacturing process of the semiconductor device of the present invention.

FIG. 8 is a sectional view showing a manufacturing process of the semiconductor device of the present invention.

FIG. 9 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of the present invention.

FIG. 10 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of the present invention.

FIG. 11 is a flowchart illustrating a CMP method used in the present invention.

FIG. 12 is a CM used in the method of manufacturing a semiconductor device according to the present invention.
The partial perspective view of a P apparatus.

FIG. 13 is a characteristic diagram showing the number of scratches on a semiconductor substrate by the CMP process of the present invention.

FIG. 14 is a sectional view showing a manufacturing process of a conventional semiconductor device.

FIG. 15 is a sectional view showing a manufacturing process of a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... 1st silicon oxide film, 3 ... Stopper film, 4 ... Silicon oxide film, 5 ... Groove, 6 ... Embedding material (silicon oxide film) , 6 ': heat-treated buried material, 7: deficiency (scratch) of semiconductor substrate due to scratch, 8: source / drain region, 9: gate electrode, 10
..Second stopper film (carbon film), 11: polishing board, 12: polishing cloth, 13: suction board, 1
4 ... drive shaft, 15 ... abrasive supply pipe, 33 ... first deposited film (first polycrystalline silicon film), 34 ... second silicon oxide film, 35 ... Second deposited film (second polycrystalline silicon film).

Claims (15)

[Claims] A step of forming an oxide film on the semiconductor substrate; a step of forming a planarization stopper film on the oxide film; and etching the planarization stopper film, the oxide film and the semiconductor substrate. Forming a groove in a semiconductor substrate, forming an insulating film on the semiconductor substrate so as to fill the groove, and planarizing the surface of the insulating film by chemical mechanical polishing. The method of manufacturing a semiconductor device, wherein the planarization stopper film has a laminated structure of a plurality of layers made of different materials. 2. The method according to claim 1, wherein the planarization stopper film has a stacked structure including an oxide film and a plurality of stacked films sandwiching both surfaces thereof. 3. The method according to claim 1, wherein the oxide film forming the planarization stopper film is made of a thermal oxide film of silicon. 4. The semiconductor device according to claim 1, wherein said oxide film forming said planarization stopper film is formed by a chemical vapor deposition method. Production method. 5. The semiconductor device according to claim 4, wherein the oxide film formed by using the chemical vapor deposition method is subjected to a heat treatment at a high temperature of 600 ° C. or more to reduce the volume. Method. 6. The laminated film sandwiching the oxide film constituting the planarization stopper film is made of a material having an etching selectivity with respect to the oxide film. 13. The method for manufacturing a semiconductor device according to item 5. 7. The method of manufacturing a semiconductor device according to claim 2, wherein the stacked films sandwiching the oxide film forming the planarization stopper film are made of the same material. 8. The method of manufacturing a semiconductor device according to claim 2, wherein the stacked film sandwiching the oxide film forming the planarization stopper film is made of polycrystalline silicon. 9. The method according to claim 1, wherein the thickness of the oxide film forming the planarization stopper film is Tox, and the thickness of the laminated film sandwiching the oxide film is T.
2. When the etching rate when the laminated film laminated on the oxide film is peeled off is α [nm / min], and the etching rate of the oxide film under the condition is β [nm / min], the following relational expression is used. 3. The method according to claim 2, wherein
A method for manufacturing a semiconductor device according to claim 8. Tox> β · T2 / α 10. A laminated film sandwiching the oxide film constituting the planarization stopper film, wherein a thickness of the laminated film laminated on the oxide film is T2, and a laminated film laminated on the oxide film is formed below the oxide film. 10. The method of manufacturing a semiconductor device according to claim 2, wherein the following relational expression is satisfied when the film thickness of the semiconductor device is T1. T1 ≦ T2 11. A step of forming an oxide film on a semiconductor substrate; a step of forming a first planarization stopper film on the oxide film; and a step of forming the first planarization stopper film, the oxide film, and the semiconductor. Etching a substrate to form a groove in the semiconductor substrate; forming an insulating film on the semiconductor substrate so as to fill the groove; and performing a first planarization of the insulating film, Reducing the volume of the insulating film, and removing the semiconductor substrate after the first planarization.
A step of performing a heat treatment at a high temperature of 0 ° C. or more, and a step of performing a second planarization until the first planarization stopper film is exposed by chemical mechanical polishing of the thermally treated insulating film. A method for manufacturing a semiconductor device, comprising: 12. The first planarization is performed using a second planarization stopper film formed on the insulating film above the groove, and the second planarization is performed. 12. The method according to claim 11, wherein the second planarization stopper film is removed before. 13. The method according to claim 11, wherein the first planarization is performed using a chemical mechanical polishing method.
A method for manufacturing a semiconductor device according to claim 12. 14. The method according to claim 11, wherein the first planarization is performed to such an extent that a filling material remains on the first planarization stopper film. A method for manufacturing a semiconductor device. 15. The method according to claim 1, wherein the heat treatment at a high temperature of 700 ° C. or more is performed in a nitrogen atmosphere.
The method of manufacturing a semiconductor device according to claim 1.