JPH118261A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH118261A JPH118261A JP15719097A JP15719097A JPH118261A JP H118261 A JPH118261 A JP H118261A JP 15719097 A JP15719097 A JP 15719097A JP 15719097 A JP15719097 A JP 15719097A JP H118261 A JPH118261 A JP H118261A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- base material
- holes
- cutting
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
Landscapes
- Wire Bonding (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、母基材を複数のス
ルーホールを横切る線に沿って切断することによって、
基板の端部にスルーホール切断され形成されるアウター
リードを設ける半導体装置の製造方法に関するものであ
る。The present invention relates to a method for cutting a base material along a line crossing a plurality of through holes.
The present invention relates to a method for manufacturing a semiconductor device having an outer lead formed by cutting through holes at an end of a substrate.
【０００２】[0002]
【従来の技術】ＱＦＮ等のリードレスの半導体装置を作
製するにあたり、半導体装置の基板の端部に半円凹部と
して形成されるアウターリードを設けるために、従来か
ら母基材にスルーホールを複数個穿設し、該スルーホー
ルをメッキ処理した後にスルーホールを横切る線に沿っ
て母基材を切断することによって、半導体装置の基板を
母基材から切り出すと共に、基板の端部にスルーホール
が切断されることによって形成される半円凹部のアウタ
ーリードを設ける、という手法が行われている。2. Description of the Related Art In manufacturing a leadless semiconductor device such as a QFN, a plurality of through holes have conventionally been formed in a base material in order to provide outer leads formed as semicircular recesses at an end of a substrate of the semiconductor device. After drilling the individual pieces and plating the through holes, the base material is cut along a line crossing the through holes to cut out the substrate of the semiconductor device from the base material, and the through holes are formed at the ends of the substrate. A method of providing an outer lead of a semicircular recess formed by cutting is used.
【０００３】[0003]
【発明が解決しようとする課題】しかし、母基材を切断
する際は母基材にかけられる切断荷重のために母基材に
歪みが生じ、そのため母基材の板厚が厚くなる程、また
はスルーホール間のピッチが狭くなる程、スルーホール
を横切る線に沿って母基材を切断する際に、スルーホー
ルの切断部分のメッキのめくれやはがれの発生率が大き
くなり、スルーホールの切断歩留りが著しく悪くなるも
のであった。However, when cutting the base material, the base substrate is distorted due to the cutting load applied to the base material, so that as the thickness of the base material increases, or The narrower the pitch between the through holes, the greater the rate of plating turn-up and peeling of the cut portion of the through hole when cutting the base material along the line crossing the through hole, and the cut yield of the through hole Was significantly worse.
【０００４】本発明は上記の点に鑑みてなされたもので
あり、母基材の板厚が厚い場合であっても、あるいはス
ルーホール間のピッチが狭い場合であっても、スルーホ
ールの切断歩留りが良好な半導体装置の製造方法を提供
することを目的とするものである。[0004] The present invention has been made in view of the above points, and it is possible to cut through holes even when the base material is thick or the pitch between the through holes is narrow. It is an object of the present invention to provide a method for manufacturing a semiconductor device having a good yield.
【０００５】[0005]
【課題を解決するための手段】本発明の請求項１に記載
の半導体装置Ａの製造方法は、母基材２２に長円形の孔
を穿設することによって形成されるスルーホール２０を
複数設け、該スルーホール２０にめっき処理した後、各
スルーホール２０の短径側を横切る線に沿って母基材２
２を切断することによって、基板１の端部にスルーホー
ル２０が切断されることによって形成されるアウターリ
ード１０を設けた半導体装置Ａを得ることを特徴とする
ものである。According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a plurality of through holes are formed by forming an oblong hole in a base material. After plating the through holes 20, the base material 2 is cut along a line crossing the minor diameter side of each through hole 20.
2, a semiconductor device A having an outer lead 10 formed by cutting a through hole 20 at an end of the substrate 1 is obtained.
【０００６】また本発明の請求項２に記載の半導体装置
Ａの製造方法は、母基材２２に二つの丸孔２１ａを穿設
位置をずらして一部重なるように穿設することによって
形成されるスルーホール２１を複数設け、該スルーホー
ル２１にめっき処理した後、各スルーホール２１の二つ
の丸孔２１ａの重なり位置を横切る線に沿って母基材２
２を切断することによって、基板１の端部にスルーホー
ル２１が切断されることによって形成されるアウターリ
ード１０を設けた半導体装置Ａを得ることを特徴とする
ものである。A method of manufacturing a semiconductor device A according to a second aspect of the present invention is formed by drilling two round holes 21a in a base material 22 so as to partially overlap with each other by shifting the drilling positions. After a plurality of through holes 21 are provided, and the through holes 21 are plated, the base material 2 is cut along a line crossing the overlapping position of the two round holes 21 a of each through hole 21.
2, a semiconductor device A provided with an outer lead 10 formed by cutting a through hole 21 at an end of the substrate 1 is obtained.
【０００７】また本発明の請求項３に記載の半導体装置
Ａの製造方法は、請求項２の構成に加えて、二つの丸孔
２１ａを、各中心間の距離が丸孔２１ａの直径の１／２
〜１／４の間になるように母基材２２に穿設することに
よってスルーホール２１を形成することを特徴とするも
のである。According to a third aspect of the present invention, in addition to the configuration of the second aspect, in addition to the configuration of the second aspect, the two round holes 21a are formed such that the distance between the centers is one of the diameter of the round hole 21a. / 2
The through hole 21 is formed by piercing the base material 22 so as to be between １ ／ and １ ／.
【０００８】[0008]
【発明の実施の形態】以下、本発明の実施の形態を説明
する。先ず、図４に示すような一般的なＱＦＮの半導体
装置Ａの製造方法について説明する。先ず、半導体装置
Ａの基板１を切り出すための母基材２２を用意する。半
導体装置Ａの基板１はこの母基材２２から方形に複数枚
切り出されるものである。この母基材２２に、基板１を
切り出す際の方形の切断線に沿ってほぼ等間隔にスルー
ホールを複数穿設し、このスルーホールに水洗処理及び
デスミア処理を施し、該スルーホールの内面、及び母基
材２２の上部及び下部のスルーホールの穿設位置の周辺
部分に銅メッキ、ニッケルメッキ、及び金メッキ処理を
施す。このように形成したメッキ部分は、スルーホール
の内面の部分のものが側部電極７、基板１上部における
スルーホールの穿設位置の周辺部分のものが上部電極
２、基板１下部におけるスルーホールの穿設位置の周辺
部分のものが下部電極８となり、それぞれがアウターリ
ード１０の構成要素となるものである。Embodiments of the present invention will be described below. First, a method for manufacturing a general QFN semiconductor device A as shown in FIG. 4 will be described. First, a base material 22 for cutting out the substrate 1 of the semiconductor device A is prepared. A plurality of substrates 1 of the semiconductor device A are cut out from the base material 22 in a rectangular shape. A plurality of through holes are formed in the base material 22 at substantially equal intervals along a rectangular cutting line when the substrate 1 is cut out, and the through holes are subjected to a washing process and a desmear process. In addition, copper plating, nickel plating, and gold plating are performed on the periphery of the upper and lower through holes at the positions where the through holes are formed. The plated portion formed in this way is the side electrode 7 on the inner surface of the through hole, the upper electrode 2 on the periphery of the through hole drilling position in the upper portion of the substrate 1, and the through electrode in the lower portion of the substrate 1. The part around the drilling position is the lower electrode 8, and each is a component of the outer lead 10.
【０００９】そして、スルーホールを横切る線に沿って
母基材２２に、金型打抜き等による切断や、ルーター等
による外形加工を行うことによって、半導体装置Ａの基
板１を母基材２２から切り出すと共に、基板１の端部に
スルーホールが切断されることによって形成されるアウ
ターリード１０を設ける。このアウターリード１０はス
ルーホールの内面部分に形成される側部電極７、基板１
上部におけるスルーホールの穿設位置の周辺部分に形成
される上部電極２、及び基板１下部におけるスルーホー
ルの穿設位置の周辺部分に形成される下部電極８から構
成されるものである。Then, the substrate 1 of the semiconductor device A is cut out from the mother substrate 22 by cutting the mother substrate 22 along a line crossing the through hole by punching a die or the like, or performing external processing by a router or the like. In addition, an outer lead 10 formed by cutting a through hole is provided at an end of the substrate 1. The outer lead 10 is formed on the side electrode 7 formed on the inner surface of the through hole and the substrate 1.
The upper electrode 2 is formed in the upper part around the through hole drilling position, and the lower electrode 8 is formed in the lower part of the substrate 1 around the through hole drilling position.
【００１０】なお、母基材２２における、基板１が切り
出される部分には、アウターリード１０が形成される部
分を含む基材１の周縁部分を残して、ダム３の形成によ
る方形の囲いを設けるか、あるいは方形に座ぐり加工
し、母基材２２上のダム３で囲った部分の内側、あるい
は座ぐり加工した内部には、半導体チップ４を搭載する
ための方形のチップ搭載部１２を、ダム３で囲った部分
あるいは座ぐり加工した部分の周縁を残して、ダム３で
囲った部分あるいは座ぐり加工した部分よりもやや小さ
い大きさに形成しておくものである。A portion of the mother substrate 22 from which the substrate 1 is cut out is provided with a rectangular enclosure formed by the dam 3 except for the peripheral portion of the substrate 1 including the portion where the outer leads 10 are formed. A square chip mounting portion 12 for mounting the semiconductor chip 4 is provided inside the portion surrounded by the dam 3 on the base material 22 or inside the damped portion. It is formed to have a size slightly smaller than the portion surrounded by the dam 3 or the counterbored portion while leaving the periphery of the portion surrounded by the dam 3 or the counterbored portion.
【００１１】また、母基材２２には、各上部電極２に接
続され、各上部電極２からチップ搭載部１２を形成する
部分の周辺まで延びる放射状の回路１１を形成し、必要
であればソルダーレジスト印刷、金メッキ処理を行って
おくものである。また半導体チップ４の搭載は、半導体
チップ４をチップ搭載部１２に載置し、ワイヤボンディ
ング方式を用いて半導体チップ４の電極５と回路１１と
を金属細線６で接続した後、封止樹脂９をダム３で囲っ
た部分または座ぐり加工した部分に注入して樹脂成形す
ることによって行うものである。A radial circuit 11 connected to each upper electrode 2 and extending from each upper electrode 2 to a periphery of a portion where the chip mounting portion 12 is formed is formed on the base material 22. The resist printing and the gold plating process are performed. The semiconductor chip 4 is mounted by mounting the semiconductor chip 4 on the chip mounting portion 12, connecting the electrodes 5 of the semiconductor chip 4 and the circuit 11 with the thin metal wires 6 using a wire bonding method, and then sealing the resin 9. Is injected into a portion surrounded by the dam 3 or a counterbored portion to form a resin.
【００１２】上記の半導体装置Ａの製造工程のうち、ス
ルーホールの穿設加工においては、従来は母基材２２の
所定の位置に丸孔を穿設していたものであるが、母基材
２２を切断する際に母基材２２にかけられる切断荷重の
ために母基材２２に歪みが生じるものであり、その歪み
は母基材２２の板厚が厚くなる程、またはスルーホール
間のピッチが狭くなる程大きくなる。スルーホールをこ
のように丸孔として形成している場合には、母基材２２
の板厚がある程度以上厚い場合、またはスルーホール間
のピッチがある程度以上狭い場合は、この歪みの発生の
ために、スルーホールを横切る線に沿って母基材２２を
切断する際の、スルーホールの切断部分のメッキのめく
れやはがれの発生率が大きくなり、そのためスルーホー
ルの切断歩留りが著しく悪くなるものであった。In the above-described process of manufacturing the semiconductor device A, in the process of drilling a through hole, a round hole is conventionally drilled at a predetermined position on the mother substrate 22. The cutting force applied to the base material 22 when cutting the base material 22 causes distortion in the base material 22. The distortion is caused by increasing the thickness of the base material 22 or the pitch between the through holes. It becomes large so that becomes narrow. When the through hole is formed as a round hole as described above, the base material 22
When the thickness of the base material is thicker than a certain degree, or when the pitch between the through holes is narrower than a certain degree, when the base material 22 is cut along a line crossing the through hole due to the distortion, The rate of occurrence of plating turn-up and peeling at the cut portion of the above becomes large, and as a result, the cutting yield of the through-hole is remarkably deteriorated.
【００１３】そこで請求項１の発明では、図１（ａ）及
び（ｂ）に示すように、半導体装置Ａの基板１を方形に
複数切り出すための母基材２２にスルーホール２０を穿
設する際には、長円形のスルーホール２０を、その長円
の長径が切断線１３と垂直になるように、切断線１３に
沿ってほぼ等間隔に穿設し、該スルーホール２０の内
面、及び母基材２２の上部及び下部のスルーホール２０
の穿設位置の周辺部分に銅メッキ、ニッケルメッキ、及
び金メッキ処理を施す。Therefore, according to the first aspect of the present invention, as shown in FIGS. 1A and 1B, a through hole 20 is formed in a base material 22 for cutting a plurality of substrates 1 of a semiconductor device A into a square. In this case, the oblong through hole 20 is formed at substantially equal intervals along the cutting line 13 so that the major axis of the oval is perpendicular to the cutting line 13, and the inner surface of the through hole 20 and Upper and lower through holes 20 of base material 22
Copper plating, nickel plating, and gold plating are applied to the peripheral portion of the drilling position.
【００１４】そして母基材２２から基材１を切り出す際
には、各スルーホール２０の短径側を横切る切断線１３
に沿って母基材２２に、金型打抜き等による切断や、ル
ーター等による外形加工を行うことによって、半導体装
置Ａの基板１を母基材２２から切り出すと共に、基板１
の端部にスルーホールが切断されることによって形成さ
れるアウターリード１０を設ける。この際、アウターリ
ード１０は、上記メッキ部分が形成する、スルーホール
２０の内面部分に形成される側部電極７、基板１上部に
おけるスルーホールの穿設位置の周辺部分に形成される
上部電極２、及び基板１下部におけるスルーホールの穿
設位置の周辺部分に形成される下部電極８から構成され
るものである。この場合、長円形のスルーホール２０を
切断して形成されるアウターリード１０の側部電極７の
面積は図３（ａ）に示すように、丸孔のスルーホールを
切断して形成される図４に示す従来のアウターリード１
０の側部電極７の面積と比較して大きくなっているもの
である。このように、側部電極７の面積は、丸孔を穿設
してスルーホールを設けた場合に形成される側部電極７
の面積と比較して大きくすることができ、そのためスル
ーホール２０を短径方向に横切る切断線１３に沿って母
基材２２を切断する際、母基材２２の板厚がある程度以
上厚い場合、またはスルーホール２０間のピッチがある
程度以上狭い場合であっても、母基材２２の歪みのため
にスルーホール２０の切断部分のメッキのめくれやはが
れが起こり難くなり、そのためスルーホール２０の切断
歩留りを向上することができるものである。When cutting the base material 1 from the base material 22, the cutting line 13 crossing the short diameter side of each through hole 20.
The substrate 1 of the semiconductor device A is cut out from the base material 22 by cutting the base material 22 by die-cutting or the like, or performing external processing by a router or the like along the base material 22.
Are provided with outer leads 10 formed by cutting through holes. At this time, the outer lead 10 is formed by the side electrode 7 formed on the inner surface of the through hole 20 formed by the plated portion, and the upper electrode 2 formed on the upper portion of the substrate 1 around the position where the through hole is formed. , And a lower electrode 8 formed in a lower portion of the substrate 1 around a position where a through hole is formed. In this case, as shown in FIG. 3A, the area of the side electrode 7 of the outer lead 10 formed by cutting the oblong through hole 20 is formed by cutting the circular through hole. Conventional outer lead 1 shown in FIG.
This is larger than the area of the side electrode 7 of zero. As described above, the area of the side electrode 7 is equal to the side electrode 7 formed when a round hole is formed and a through hole is provided.
When the base material 22 is cut along the cutting line 13 that crosses the through hole 20 in the minor diameter direction, the thickness of the base material 22 is larger than a certain amount. Alternatively, even when the pitch between the through holes 20 is narrower than a certain degree, the plating of the cut portion of the through hole 20 is not easily turned or peeled off due to the distortion of the base material 22, and therefore, the cutting yield of the through hole 20 is reduced. Can be improved.
【００１５】なお、側部電極７の面積を充分広くとるた
めに、この母基材２２から基材１を切り出す切断線１３
は、長円形のスルーホール２０の長径上における、この
長径の一端部からの長さが、長径の１／５〜４／５の範
囲内を通るようにするのが好ましい。また、母基材２２
にスルーホール２０を穿設する際には、図１（ａ）のよ
うに楕円形孔にスルーホール２０を形成する他に、図１
（ｂ）に示すもののように、小判形孔にスルーホール２
０を形成してもよいものである。In order to make the area of the side electrode 7 sufficiently large, a cutting line 13 for cutting the base material 1 from the base material 22 is used.
It is preferable that the length from one end of the major axis on the major axis of the oblong through hole 20 passes within a range of 1/5 to 4/5 of the major axis. The base material 22
When the through hole 20 is formed in the hole, the through hole 20 is formed in the oval hole as shown in FIG.
As shown in (b), the through hole 2
0 may be formed.
【００１６】なお、母基材２２における、基板１が切り
出される部分には、アウターリード１０が形成される部
分を含む基材１の周縁部分を残して、ダム３の形成によ
る方形の囲いを設けるかあるいは方形に座ぐり加工し、
母基材２２上のダム３で囲った部分の内側、あるいは座
ぐり加工した内部には、半導体チップ４を搭載するため
の方形のチップ搭載部１２を、ダム３で囲った部分ある
いは座ぐり加工した部分の周縁を残して、ダム３で囲っ
た部分あるいは座ぐり加工した部分よりもやや小さい大
きさに形成しておくものである。A portion of the mother substrate 22 from which the substrate 1 is cut out is provided with a rectangular enclosure formed by the dam 3 except for the peripheral portion of the substrate 1 including the portion where the outer leads 10 are formed. Or countersunk into a square,
A rectangular chip mounting portion 12 for mounting the semiconductor chip 4 is provided inside the portion surrounded by the dam 3 on the mother base material 22 or inside the spotted portion. The remaining portion is formed to have a slightly smaller size than the portion surrounded by the dam 3 or the counterbored portion, leaving the periphery of the portion.
【００１７】また、母基材２２には、各上部電極２に接
続され、各上部電極２からチップ搭載部１２を形成する
部分の周辺まで延びる放射状の回路１１を形成し、必要
であればソルダーレジスト印刷、金メッキ処理を行って
おくものである。また、半導体チップ４の搭載は、半導
体チップ４をチップ搭載部１２に載置し、ワイヤボンデ
ィング方式を用いて半導体チップ４の電極５と回路１１
とを金属細線６で接続した後、封止樹脂９をダム３で囲
った部分または座ぐり加工した部分に注入して樹脂成形
することによって行うものである。A radial circuit 11 connected to each upper electrode 2 and extending from each upper electrode 2 to the periphery of a portion where the chip mounting portion 12 is formed is formed on the base material 22. The resist printing and the gold plating process are performed. The semiconductor chip 4 is mounted by mounting the semiconductor chip 4 on the chip mounting portion 12 and using the wire bonding method to connect the electrode 5 of the semiconductor chip 4 and the circuit 11.
Are connected by a thin metal wire 6, and then the sealing resin 9 is injected into a portion surrounded by the dam 3 or a counterbored portion to form a resin.
【００１８】また、請求項２の発明では、図２（ａ）及
び（ｂ）に示すように、半導体装置Ａの基板１を方形に
複数切り出すための母基材２２にスルーホール２１を穿
設する際には、二つの丸孔２１ａを、その穿設位置を切
断線１３に対して垂直方向にずらして一部重なるように
穿設することによって形成されるスルーホール２１を、
切断線１３に沿ってほぼ等間隔に複数設け、該スルーホ
ール２１の内面、及び母基材２２の上部及び下部のスル
ーホール２１の穿設位置の周辺部分に銅メッキ、ニッケ
ルメッキ、及び金メッキ処理を施す。According to the second aspect of the present invention, as shown in FIGS. 2A and 2B, through holes 21 are formed in a base material 22 for cutting a plurality of substrates 1 of a semiconductor device A into a square. In doing so, a through hole 21 formed by drilling two round holes 21a so that the drilling positions thereof are shifted in the vertical direction with respect to the cutting line 13 and partially overlap with each other,
A plurality of copper plating, nickel plating, and gold plating treatments are provided at substantially equal intervals along the cutting line 13 on the inner surface of the through hole 21 and the peripheral portions of the upper and lower through holes 21 where the through hole 21 is formed. Is applied.
【００１９】そして母基材２２から基材１を切り出す際
には、各スルーホール２１の二つの丸孔２１ａの重なり
位置を切断線１３に沿って、母基材２２に、金型打抜き
等による切断や、ルーター等による外形加工を行うこと
によって、半導体装置Ａの基板１を母基材２２から切り
出すと共に、基板１の端部にスルーホール２１が切断さ
れることによって形成されるアウターリード１０を設け
る。この際、アウターリード１０は、上記メッキ部分が
形成する、スルーホール２１の内面部分にメッキが施さ
れて形成される側部電極７、基板１上部におけるスルー
ホール２１の穿設位置の周辺部分にメッキが施されて形
成される上部電極２、及び基板１下部におけるスルーホ
ール２１の穿設位置の周辺部分にメッキが施されて形成
される下部電極８から構成されるものである。この場
合、二つの丸孔２１ａの重なり位置でスルーホール２１
を切断して形成されたアウターリード１０の側部電極７
の面積は図３（ｂ）に示すように、丸孔のスルーホール
の中心を切断して形成される図４に示すアウターリード
１０の側部電極７の面積と比較して大きくなっているも
のである。このように側部電極７の面積は、丸孔を穿設
してスルーホールを設けた場合に形成される側部電極７
の面積と比較して大きくすることができ、そのためスル
ーホール２１の丸孔の重なり部分を横切る切断線１３に
沿って母基材２２を切断する際、母基材２２の板厚があ
る程度以上厚い場合、またはスルーホール２１間のピッ
チがある程度以上狭い場合であっても、母基材２２の歪
みのためにスルーホール２１の切断部分のメッキのめく
れやはがれが起こり難くなり、そのためスルーホール２
１の切断歩留りを向上することができるものである。When cutting the base material 1 from the base material 22, the overlapping position of the two round holes 21a of each through hole 21 is cut along the cutting line 13 into the base material 22 by die punching or the like. The substrate 1 of the semiconductor device A is cut out from the mother substrate 22 by cutting or performing external processing by a router or the like, and the outer lead 10 formed by cutting the through hole 21 at the end of the substrate 1 is removed. Provide. At this time, the outer lead 10 is formed on the side electrode 7 formed by plating the inner surface portion of the through hole 21 formed by the plated portion, and on the peripheral portion of the upper portion of the substrate 1 around the drilling position of the through hole 21. The upper electrode 2 is formed by plating, and the lower electrode 8 is formed by plating a portion of the lower part of the substrate 1 around a position where the through hole 21 is formed. In this case, the through hole 21 is located at the position where the two round holes 21a overlap.
Side electrode 7 of outer lead 10 formed by cutting
As shown in FIG. 3B, the area of the outer lead 10 is larger than the area of the side electrode 7 of the outer lead 10 shown in FIG. 4 formed by cutting the center of the through hole of the round hole. It is. As described above, the area of the side electrode 7 is limited by the side electrode 7 formed when a round hole is formed and a through hole is provided.
Therefore, when cutting the base material 22 along the cutting line 13 crossing the overlapping portion of the round holes of the through holes 21, the thickness of the base material 22 is larger than a certain level. In this case, or even when the pitch between the through holes 21 is narrower than a certain degree, the plating of the cut portion of the through hole 21 is unlikely to occur due to the distortion of the base material 22.
1 can improve the cutting yield.
【００２０】なお、スルーホール２１を設ける際、穿設
する二つの丸孔２１ａの各中心間の距離が狭過ぎると、
形成される側部電極７の面積を充分広くすることができ
ず、また穿設する二つの丸孔２１ａの各中心間の距離が
広過ぎると基板１の端部における側部電極７の開口部の
幅が狭くなり、側部電極７を外部の回路と接続すること
が困難になるため、二つの丸孔２１ａの各中心間の距離
は丸孔２１ａの直径の１／２〜１／４の間になるように
穿設するのが好ましい。When the through hole 21 is provided, if the distance between the centers of the two round holes 21a to be formed is too small,
If the area of the formed side electrode 7 cannot be made sufficiently large, and if the distance between the centers of the two round holes 21a to be formed is too large, the opening of the side electrode 7 at the end of the substrate 1 Becomes narrow, and it becomes difficult to connect the side electrode 7 to an external circuit. Therefore, the distance between the centers of the two round holes 21a is 1/2 to 1/4 of the diameter of the round holes 21a. It is preferable to make a hole so as to be between them.
【００２１】なお、母基材２２における、基板１が切り
出される部分には、アウターリード１０が形成される部
分を含む基材１の周縁部分を残して、ダム３の形成によ
る方形の囲いを設けるかあるいは方形に座ぐり加工し、
母基材２２上のダム３で囲った部分の内側、あるいは座
ぐり加工した内部には、半導体チップ４を搭載するため
の方形のチップ搭載部１２を、ダム３で囲った部分ある
いは座ぐり加工した部分の周縁を残して、ダム３で囲っ
た部分あるいは座ぐり加工した部分よりもやや小さい大
きさに形成しておくものである。A portion of the mother substrate 22 from which the substrate 1 is cut out is provided with a rectangular enclosure formed by the dam 3 except for the peripheral portion of the substrate 1 including the portion where the outer leads 10 are formed. Or countersunk into a square,
A rectangular chip mounting portion 12 for mounting the semiconductor chip 4 is provided inside the portion surrounded by the dam 3 on the mother base material 22 or inside the spotted portion. The remaining portion is formed to have a slightly smaller size than the portion surrounded by the dam 3 or the counterbored portion, leaving the periphery of the portion.
【００２２】また、母基材２２には、各上部電極２に接
続され、各上部電極２からチップ搭載部１２を形成する
部分の周辺まで延びる放射状の回路１１を形成し、必要
であればソルダーレジスト印刷、金メッキ処理を行って
おくものである。また、半導体チップ４の搭載は、半導
体チップ４をチップ搭載部に載置し、ワイヤボンディン
グ方式を用いて半導体チップ４の電極５と回路１１とを
金属細線６で接続した後、封止樹脂９をダム３で囲った
部分または座ぐり加工した部分に注入して樹脂成形する
ことによって行うものである。A radial circuit 11 connected to each upper electrode 2 and extending from each upper electrode 2 to a periphery of a portion where the chip mounting portion 12 is formed is formed on the base material 22. The resist printing and the gold plating process are performed. The semiconductor chip 4 is mounted by mounting the semiconductor chip 4 on the chip mounting portion, connecting the electrodes 5 of the semiconductor chip 4 and the circuit 11 with thin metal wires 6 using a wire bonding method, and then sealing the resin 9. Is injected into a portion surrounded by the dam 3 or a counterbored portion to form a resin.
【００２３】[0023]
【発明の効果】上記のように本発明の請求項１に記載の
半導体装置の製造方法は、母基材に長円形の孔を穿設す
ることによって形成されるスルーホールを複数設け、該
スルーホールにめっき処理した後、各スルーホールの短
径側を横切る線に沿って母基材を切断することによっ
て、基板の端部にスルーホールが切断されることによっ
て形成されるアウターリードを設けるようにしたので、
スルーホールの内面にメッキによって形成される電極の
面積が大きくなり、母基材の板厚が厚い場合、あるいは
スルーホール間のピッチが狭い場合に、母基材の切断時
に母基材が歪んでも、スルーホールの切断部分のメッキ
のめくれやはがれが発生し難くなり、その結果スルーホ
ールの切断歩留りを向上することができるものである。As described above, in the method of manufacturing a semiconductor device according to the first aspect of the present invention, a plurality of through holes formed by forming an oblong hole in a base material are provided. After plating the holes, by cutting the base material along a line crossing the short diameter side of each through hole, an outer lead formed by cutting the through hole at the end of the substrate is provided. Because it was
If the area of the electrode formed by plating on the inner surface of the through hole becomes large and the thickness of the base material is large, or if the pitch between the through holes is small, the base material may be distorted when cutting the base material. This makes it difficult for plating to be turned or peeled off at the cut portion of the through hole, and as a result, the cutting yield of the through hole can be improved.
【００２４】また本発明の請求項２に記載の半導体装置
の製造方法は、母基材に二つの丸孔を穿設位置をずらし
て一部重なるように穿設することによって形成されるス
ルーホールを複数設け、該スルーホールにメッキ処理し
た後、各スルーホールの二つの丸孔の重なり位置を横切
る線に沿って母基材を切断することによって、基板の端
部にスルーホールが切断されることによって形成される
アウターリードを設けたため、スルーホールの内面にメ
ッキによって形成される電極の面積が大きくなり、母基
材の板厚が厚い場合、あるいはスルーホール間のピッチ
が狭い場合に、母基材の切断時に母基材が歪んでも、ス
ルーホールの切断部分のメッキのめくれやはがれが発生
し難くなり、その結果スルーホールの切断歩留りを向上
することができるものである。According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein two round holes are formed in a mother substrate so as to be partially overlapped with each other at different positions. After plating the through holes, by cutting the base material along a line crossing the overlapping position of the two round holes of each through hole, the through hole is cut at the end of the substrate In this case, the outer lead formed by this method is provided, so that the area of the electrode formed by plating on the inner surface of the through hole becomes large, and when the thickness of the base material is large or the pitch between the through holes is small, Even if the base material is distorted during cutting of the base material, it is difficult for plating turn-up or peeling of the cut portion of the through hole to occur, and as a result, the cutting yield of the through hole can be improved. Than it is.
【００２５】また本発明の請求項３に記載の発明は、請
求項２の半導体装置の製造方法において、二つの丸孔
を、各中心間の距離が丸孔の直径の１／２〜１／４の間
になるように母基材に穿設することによってスルーホー
ルを形成するため、スルーホールの内面の面積を充分広
くすることができ、母基材の板厚が厚い場合、あるいは
スルーホール間のピッチが狭い場合に、母基材の切断時
に母基材が歪んでも、スルーホールの切断部分のメッキ
のめくれやはがれが発生し難くなり、その結果スルーホ
ールの切断歩留りを向上することができると共に、基板
に、スルーホールの内面にメッキによって形成される電
極の、基板の端部における開口部の幅を充分広くとるこ
とができ、スルーホールの内面に形成される電極を外部
の回路と接続することを容易にすることができるもので
ある。According to a third aspect of the present invention, in the method for manufacturing a semiconductor device of the second aspect, the two round holes are formed such that the distance between the centers is 1/2 to 1/1 / the diameter of the round hole. 4, the through hole is formed by piercing the base material so as to be located between the base material 4 and the inner surface area of the through hole can be sufficiently increased. When the base pitch is narrow, even if the base material is distorted when cutting the base material, plating turn-up or peeling of the cut portion of the through hole is less likely to occur, and as a result, the cutting yield of the through hole can be improved. In addition, the width of the opening at the end of the substrate of the electrode formed by plating the inner surface of the through hole on the substrate can be made sufficiently large, and the electrode formed on the inner surface of the through hole can be connected to an external circuit. Connect In which it is to be facilitated.
【図面の簡単な説明】[Brief description of the drawings]
【図１】（ａ）及び（ｂ）は、本発明の実施の形態の一
例を示す平面図である。FIGS. 1A and 1B are plan views showing an example of an embodiment of the present invention.
【図２】（ａ）及び（ｂ）は、本発明の実施の形態の他
の例を示すものであり、（ａ）は平面図、（ｂ）はロ部
分の拡大図である。FIGS. 2A and 2B show another example of the embodiment of the present invention, wherein FIG. 2A is a plan view and FIG. 2B is an enlarged view of a portion B.
【図３】（ａ）及び（ｂ）は、本発明の実施の形態の一
例の一部の平面図である。FIGS. 3A and 3B are partial plan views of an example of an embodiment of the present invention.
【図４】従来の半導体装置の一例を示すものであり、
（ａ）は平面図、（ｂ）はイ−イ断面図である。FIG. 4 illustrates an example of a conventional semiconductor device.
(A) is a top view, (b) is an ii sectional view.
Ａ 半導体装置 １ 基板 １０ アウターリード ２０、２１ スルーホール ２１ａ 丸孔 ２２ 母基材 A Semiconductor device 1 Substrate 10 Outer lead 20, 21 Through hole 21a Round hole 22 Base material
Claims (3)
って形成されるスルーホールを複数設け、該スルーホー
ルにめっき処理した後、各スルーホールの短径側を横切
る線に沿って母基材を切断することによって、基板の端
部にスルーホールが切断されることによって形成される
アウターリードを設けた半導体装置を得ることを特徴と
する、半導体装置の製造方法。1. A plurality of through-holes formed by drilling an oblong hole in a mother base material, and after plating the through-holes, along a line crossing the minor diameter side of each through-hole. A method for manufacturing a semiconductor device, comprising: obtaining a semiconductor device provided with outer leads formed by cutting through holes at an end of a substrate by cutting a base material.
て一部重なるように穿設することによって形成されるス
ルーホールを複数設け、該スルーホールにめっき処理し
た後、各スルーホールの二つの丸孔の重なり位置を横切
る線に沿って母基材を切断することによって、基板の端
部にスルーホールが切断されることによって形成される
アウターリードを設けた半導体装置を得ることを特徴と
する、半導体装置の製造方法。2. A plurality of through-holes formed by drilling two round holes in a mother substrate so as to partially overlap each other while shifting the drilling position, plating the through-holes, and plating each through-hole. Obtaining a semiconductor device provided with an outer lead formed by cutting a through hole at an end of a substrate by cutting a base material along a line crossing an overlapping position of two round holes of the hole A method for manufacturing a semiconductor device, comprising:
直径の１／２〜１／４の間になるように母基材に穿設す
ることによってスルーホールを形成することを特徴とす
る請求項２に記載の半導体装置の製造方法。3. A through hole is formed by drilling two round holes in a base material such that the distance between the centers is between 1/2 and 1/4 of the diameter of the round hole. The method for manufacturing a semiconductor device according to claim 2, wherein:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15719097A JPH118261A (en) | 1997-06-13 | 1997-06-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15719097A JPH118261A (en) | 1997-06-13 | 1997-06-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH118261A true JPH118261A (en) | 1999-01-12 |
Family
ID=15644179
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15719097A Withdrawn JPH118261A (en) | 1997-06-13 | 1997-06-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH118261A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002353530A (en) * | 2001-05-22 | 2002-12-06 | Canon Inc | Laminated electromechanical energy conversion element and manufacturing method therefor |
| US7195953B2 (en) | 2003-04-02 | 2007-03-27 | Yamaha Corporation | Method of manufacturing a semiconductor package using a lead frame having through holes or hollows therein |
| US7397112B2 (en) | 2004-12-24 | 2008-07-08 | Yamaha Corporation | Semiconductor package and lead frame therefor |
| JP2009027103A (en) * | 2007-07-24 | 2009-02-05 | Citizen Electronics Co Ltd | Circuit board with through-hole and manufacturing method therefor |
-
1997
- 1997-06-13 JP JP15719097A patent/JPH118261A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002353530A (en) * | 2001-05-22 | 2002-12-06 | Canon Inc | Laminated electromechanical energy conversion element and manufacturing method therefor |
| US7195953B2 (en) | 2003-04-02 | 2007-03-27 | Yamaha Corporation | Method of manufacturing a semiconductor package using a lead frame having through holes or hollows therein |
| KR100877640B1 (en) * | 2003-04-02 | 2009-01-12 | 야마하 가부시키가이샤 | Lead frame |
| US7397112B2 (en) | 2004-12-24 | 2008-07-08 | Yamaha Corporation | Semiconductor package and lead frame therefor |
| JP2009027103A (en) * | 2007-07-24 | 2009-02-05 | Citizen Electronics Co Ltd | Circuit board with through-hole and manufacturing method therefor |
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| Date | Code | Title | Description |
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| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20040907 |